electronic+system+design 1

8/13/2019 Electronic+System+Design 1

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PAAVAI ENGINEERING COLLEGE

PAAVAI NAGAR, NH-7, PACHAL, NAMAKKAL-637018

Name:

Branch: .

Register No:

Roll No:

Certified that this is bonafide record of work done by the above student

of the.laboratory

during the year 20 ! 202

"ignature of #ab $n charge "ignature of %ead of the &e'artment

"ubmitted for the (ractical )*amination held on ..

$nternal )*aminer )*ternal )*aminer


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CONTENTS

EX.NO: 1DATE:

2

EXP.

NO.DATE

NAME OF THE EXPERIMENT

PAGE

NO.

MARKS

AWARDEDREMARKS

+odeling of "e,uential &igital "ystem

-sing %

2+odeling of "e,uential &igital "ystem

-sing )R$#/

1&esign nd $m'lementation of #-

-sing 3(

4"imulation of N+/" nd C+/" circuits

-sing "($C)

5 &esign nd $m'lementation /f +ultirate

"ystems -sing &"(

6"earching nd "orting lgorithms -sing

6 Bit +icro'rocessor

7"imulation of 8+3 -sing "imulation

(ackages


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MODELING OF SE!ENTIAL DIGITAL S"STEM !SING VHDL

AIM:

9o model and simulate the se,uential digital system using %.

TOOLS RE!IRED:

ilin* $") ;.i

(C

PROCED!RE:

9he ilin* $") ;.i is o'ened. $n the file menu New (ro -' counter> &own

counter> and "hift Register@ have been designed and saved.

"ynta* is verified by using Check "ynta* o'tion in 'rocess navigator bar.

"imulation is done by selecting Behavioral simulation from source window and

the corres'onding file is selected.

$n the 'rocess navigator tool 9)"9 B)NC% waveform is selected and the in'ut is

given and the file is saved.

9hen the ilin* $") "imulator is chosen and the simulated out'ut waveform will

be generated.

PROGRAM:

1


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D-FLIPFLOP

library $)))A

use $)))."9/$C64.##A

use $)))."9/$CR$9%.##A

use $)))."9/$C-N"$N)&.##A

!!!! -ncomment the following library declaration if instantiating

!!!! any ilin* 'rimitives in this code.

!!library -N$"$+A

!!use -N$"$+.Com'onents.allA

entity gfhgh is

(ort ? d : in "9/$CA

clk : in "9/$CA

, : out "9/$CA

,b : out "9/$C@Aend gfhghA

architecture Behavioral of gfhgh is

begin

'rocess?clk@

begin

if?clkDD@then

,Ed after 0 nsA

,bEnot d after 20 nsA

end ifAend 'rocessA

end BehavioralA

LOGIC DIAGRAM FOR D-FLIPFLOP:

4


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TR!TH TA#LE:

O!TP!T WAVEFORM FOR D-FLIPFLOP

!PCO!NTER

5


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library $)))A

use $)))."9/$C64.##A

use $)))."9/$CR$9%.##A

use $)))."9/$C-N"$N)&.##A



!!library -N$"$+A


entity u'24 is

(ort ? clk : in "9/$CA

rst : in "9/$CA

, : out "9/$C)C9/R?1 downto 0@@A

end u'24A

architecture Behavioral of u'24 is

signal dataout:stdlogicvector?1 downto 0@A

begin

'rocess?clk>dataout@

begin

if?clk Devent and clkDD@then

if?rstDD@then dataoutEF0000FA

else dataoutEdataoutGA

end ifA

end ifA

,EdataoutA

end 'rocessA

end BehavioralA

LOGIC DIAGRAM FOR !P CO!NTER:

6


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O!TP!T WAVEFORM FOR !PCO!NTER

DOWNCO!NTER

7


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library $)))A

use $)))."9/$C64.##A

use $)))."9/$CR$9%.##A

use $)))."9/$C-N"$N)&.##A

!!!! -ncomment the following library declaration if instantiating!!!! any ilin* 'rimitives in this code.

!!library -N$"$+A


entity u'24 is

(ort ? clk : in "9/$CA

rst : in "9/$CA

, : out "9/$C)C9/R?1 downto 0@@A

end u'24A

architecture Behavioral of u'24 issignal dataout:stdlogicvector?1 downto 0@A

begin

'rocess?clk>dataout@

begin

if?clk Devent and clkDD@then

if?rstDD@then dataoutEF0000FA

else dataoutEdataout!A

end ifA

end ifA

,EdataoutA

end 'rocessA

end BehavioralA

LOGIC DIAGRAM FOR DOWN CO!NTER:

H


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F RES

O!TP!T WAVEFORM FOR DOWNCO!NTER

SHIFT REGISTER

;


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library $)))A

use $)))."9/$C64.##A

use $)))."9/$CR$9%.##A

use $)))."9/$C-N"$N)&.##A



!!library -N$"$+A


entity sisosat is

(ort ? rs : in "9/$CA

d : in "9/$CA

clr : in "9/$CA

clk : in "9/$CA

, : out "9/$C@Aend sisosatA

architecture Behavioral of sisosat is

signal s:stdlogicvector?1 downto 0@A

begin

'rocess?clk@

begin

if?clkDevent and clkDD@then

if?clrDD@then

sEF0000FA

elsif rsEDD then

s?1@EdA

s?2@Es?1@A

s?@Es?2@A

s?0@Es?@A

end ifA

end ifA

,Es?0@A

end 'rocessA

end BehavioralA

LOGIC DIAGRAM FOR SHIFT REGISTER:

0


11/54

O!TP!T WAVEFORM FOR SHIFTREGISTER


12/54

RES!LT:

9hus the se,uential systems were designed and simulated using %.

2


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EX.NO: $

DATE:

MODELING OF SE!ENTIAL DIGITAL S"STEM !SING VERILOG

AIM:

9o model and simulate the se,uential digital system using )R$#/.

TOOLS RE!IRED:

ilin* $") ;.i

(C

PROCED!RE:

9he ilin* $") ;.i is o'ened. $n the file menu New (ro -' counter>

&own counter> and "hift Register@ have been designed and saved.

"ynta* is verified by using Check "ynta* o'tion in 'rocess navigator bar.

"imulation is done by selecting Behavioral simulation from source window and

the corres'onding file is selected.

$n the 'rocess navigator tool 9)"9 B)NC% waveform is selected and the in'ut is

given and the file is saved.

9hen the ilin* $") "imulator is chosen and the simulated out'ut waveform will

be generated

1


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PROGRAM FOR D-FLIPFLOP:

module dff?,> d> clk> rst@A

out'ut ,A in'ut dA

in'ut clkA

in'ut rstA

reg ,A

alwaysI?'osedge clk or negedge rst@

if?rst0@

,Db0A

else

,dA

endmodule

4


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O!TP!T WAVE FORM FOR D FLIP FLOP:

5


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!P CO!NTER:

module u'?,> clk> clear@A

out'ut J1:0K ,A

in'ut clkA in'ut clearA

regJ1:0K,A

alwaysI?'osedge clear or negedge clk@

begin

if?clear@

,E4Dd0A

else

,E,GA

end

endmodule

6


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O!TP!T WAVE FORM FOR !PCO!NTER

7


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DOWN CO!NTER:

module down?,> clk> clear@A

out'ut J1:0K ,A

in'ut clkA in'ut clearA

regJ1:0K,A

alwaysI?'osedge clear or negedge clk@

begin

if?clear@

,E4Dd0A

else

,E,!A

end

endmodule

H


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O!TP!T WAVE FORM FOR DOWN CO!NTER

;


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SHIFT REGISTER:

module sr?s0> s> in> clk> clr> ,@A

in'ut s0A

in'ut sA

in'ut inA

in'ut clkA

in'ut clrA

out'ut J1:0K,A

regJ1:0K,A

alwaysI?'osedge clk or negedge clr@

begin

if?clr0@,4Db0000A

if?s0@

,L,J1:K>inMA

else if?s@

,L,J1:K>inMA

end

endmodule

20


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O!TP!T WAVE FORM FOR SHIFT REGISTER

2


22/54

RES!LT:

9hus the se,uential systems were designed and simulated using )R$#/.

22


23/54


24/54

PROGRAM

library ieeeA

use ieee.stdlogic64.allA

use ieee.stdlogicunsigned.allA

use ieee.stdlogicarith.allA

entity #- is

'ort? : in stdlogicvector? downto 0@A

B: in stdlogicvector? downto 0@A

"el: in stdlogicvector? downto 0@A

Res: out stdlogicvector? downto 0@@Aend #-A

architecture behv of #- is

begin

'rocess?>B>"el@

begin

!! use case statement to achieve

!! different o'erations of #-

case "el is

when F00F P

Res E G BA

when F0F P

Res E G ?not B@ G A

when F0F P

Res E and BA

when FF P

Res E or BA

when others P

Res E FFA

end caseA

end 'rocessAend behvA

24


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SIM!LATED O!TP!T:

PIN ASSIGNMENTS:

25


26/54

RES!LT:

26


27/54

9hus the #- unit was designed using % and is im'lemented in 3( kit.

EX.NO: %DATE:

SIM!LATION OF NMOS AND CMOS LOGIC GATES !SING SPICE.

AIM:

9o &esign N+/" and C+/" logic ates using "($C) and simulate it.

TOOLS RE!IRED:

+$CR/Q$N& 1

PROCED!RE:

/'en +$CR/Q$N& 1.Clientdsch1com'lete.

Click file and save it.

"elect foundarycmos02o'en.

+ake a verilog filecoding convert 'rogramok.

/'en +$CR/Q$N&13ile"elect foundarycmos02.rulok.

Com'ilecom'ile verilog file3ilename.vo'en.

Com'ileclick back to editor/ut'ut will be generated.

iew"imulateoltage vs 9ime.

27


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SCHEMATIC DIAGRAM FOR NAND GATE !SING NMOS:

2H


29/54

LA"O!T:

2;


30/54

SIM!LATED O!TP!T:

10


31/54

SCHEMATIC DIAGRAM FOR NAND GATE !SING CMOS LOGIC:

1


32/54

LA"O!T:

12


33/54

SIM!LATED O!TP!T:

11


34/54

SCHEMATIC DIAGRAM FOR NOR GATE !SING CMOS LOGIC:

14


35/54

LA"O!T:

15


36/54

SIMULATED OUTPUT:

16


37/54

RES!LT:

9hus the C+/" and N+/" logic gates were simulated using "($C).

17


38/54

EX.NO: &DATE:

DESIGN AND IMPLEMENTATION OF M!LTIRATE S"STEMS !SING DSP

AIM :

9o design and im'lement &ecimation and $nter'olation using &"( (rocessor.

TOOLS RE!IRED:

CC"tudio1.

&"( (rocessor.

PROCED!RE:

/'en 671&""tart(ass will a''ear.

"elect 671&" CC"tudio 1.o'en

&ebugconnect.

/'en 'ro


39/54

PROGRAM:

DECIMATION:

TincludeEstdio.hP

TincludeEmath.hP

Tdefine length 50

Tdefine & 2

Tdefine length&?int@?lengthU&@

float &Jlength!&KAfloat VCJ50K>V"J50KA

void sine?@A

void decimate?@A

void main?@

L

sine?@A

M

void sine?@

L

int nA

float w0>fA

f50A

w02W1.4WfA

VCJ0Kcos?w0@A

V"J0Ksin?w0@A

for?nAnE50AnGG@

L

VCJnK?VCJ0KWVCJn!K@!?V"J0KWV"Jn!K@A

V"JnK?VCJ0KWV"Jn!K@G?V"J0KWVCJn!K@A

M

decimate?@AM

void decimate?@

L

int nA

for?n0AnElengthU2AnGG@

L

&JnKV"J2WnKA

M

M

1;


40/54

O!TP!T WAVEFORM:

40


41/54

INTERPOLATION:

TincludeEstdio.hP

TincludeEmath.hP

Tdefine length 50

Tdefine & 2

Tdefine length&?int@?lengthU&@

float &Jlength!&KA

float VCJ50K>V"J50KA

float $JlengthKA

void sine?@Avoid decimate?@A

void inter'olate?@A

void main?@

L

sine?@A

M

void sine?@

L

int nA

float w0>fA

f50A

w02W1.4WfA

VCJ0Kcos?w0@A

V"J0Ksin?w0@A

for?nAnE50AnGG@

L

VCJnK?VCJ0KWVCJn!K@!?V"J0KWV"Jn!K@A

VCJnK?VCJ0KWV"Jn!K@G?V"J0KWVCJn!K@A

M

decimate?@A

Mvoid decimate?@

L

int nA


L

&JnKV"J2WnKA

M

inter'olate?@A

M

void inter'olate?@

Lint nA

4


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L

$J2WnK&JnKA

M


L$J2WnGK?$J?2Wn@KG$J2W?nG2@K@U2A MM

O!TP!T WAVEFORM:

42


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RES!LT:

41


44/54

9hus inter'olation and decimation 'rogram was 'erformed using &"( 'rocessor.

EX.NO: 6

DATE:

SEARCHING AND SORTING ALGORITHMS !SING

16-#IT MICROPROCESSOR

AIM:

9o find the numbers in a given array using 6 bit micro'rocessor.

@ #argest2@ "mallest

1@ &escending

4@ scending

TOOLS RE!IRED:

H0H6 kit

PROCED!RE:

9he assembly language code is entered the micro'rocessor kit by ty'ing O.

9he starting address is given.

9he 'neumonics are entered in the kit and its corres'onding o'codes are generated by

the kit itself.

Reset/ and starting address)nter for e*ecution of the 'rogram.

gain Reset and ty'e "B ?substitute byte@ for 'roviding the in'ut.

ive the in'ut address and the corres'onding in'uts.

Reset/ and starting address)nter.

Reset"B out'ut address)nter

9he /ut'ut will be dis'layed.

44


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PROGRAM FOR LARGEST N!M#ER IN A DATA ARRA":

+/ "$> 0100%

+/ C> J"$K

+/ > 0000

BC $NC "$

$NC "$

C+( > J"$KX) /

+/ >J"$K

/ #//( BC

+/ J015K>

$N9 1

PROGRAM FOR SMALLEST N!M#ER IN A DATA ARRA":

+/ "$> 0100%

+/ C>J"$K

+/ > ;;;;

BC $NC "$

$NC "$

C+( >J"$K

XB /

+/ >J"$K

/ #//( BC

+/ J015K>

$N9 1

45


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O!TP!T FOR LARGEST N!M#ER:

&9: R)"-#9:

1000 ! 04 105 ! H6

100 ! 00 1052 ! ;51002 ! 52

1001 ! ;4

1004 ! H6

1005 ! 71

1006 ! 67

1007 ! 15

100H ! H6

100; ! ;5

O!TP!T FOR SMALLEST N!M#ER:

&9: R)"-#9:

1000 ! 04 105 ! 67

100 ! 00 1052 ! 15

1002 ! 52

1001 ! ;4

1004 ! H6

1005 ! 71

1006 ! 67

1007 ! 15

100H ! H6

100; ! ;5

46


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PROGRAM TO SORT AN ARRA" IN DESCENDING ORDER:

C#C

+/ C>J1000%K

&)C C

#: (-"% C

+/ "$>2000

#2:+/ >J"$K

+/ B>J"$G2K

C+( B>

XB) #1

C% >B

+/ J"$K>

+/ J"$G2K>B

#1:$NC "$

$NC "$

#//( #2

(/( C#//( #

%#9

PROGRAM TO SORT AN ARRA" IN ASCENDING ORDER:

C#C

+/ C>J1000%K

&)C C

#: (-"% C

+/ "$>2000

#2:+/ >J"$K

+/ B>J"$G2K

C+( B>

X) #1

C% >B

+/ J"$K>

+/ J"$G2K>B

#1:$NC "$

$NC "$#//( #2

47


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(/( C

#//( #

%#9

O!TP!T FOR DESCENDING ORDER:

&9: R)"-#9:

1000 ! 04

100 ! 00

2000 Y 01 2000 Y 0H

200 Y 00 200 Y 00

2002 Y 05 2002 Y 06

2001 Y 00 2001 Y 00

2004 Y 0H 2004 Y 05

2005 Y 00 2005 Y 00

2006 Y 06 2006 Y 01

2007 Y 00 2007 Y 00

O!TP!T FOR ASCENDING ORDER:

&9: R)"-#9:

1000 ! 04100 ! 00

2000 Y 01 2000 Y 01

200 Y 00 200 Y 00

2002 Y 05 2002 Y 05

2001 Y 00 2001 Y 00

2004 Y 0H 2004 Y 06

2005 Y 00 2005 Y 00

2006 Y 06 2006 Y 0H

2007 Y 00 2007 Y 00

4H


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4;


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RES!LT:

9hus the arrays of numbers were sorted using 6 bit micro'rocessor.

EX.NO: 7

DATE:

SIM!LATION OF MF !SING SIM!LATION PACKAGE

AIM:

9o simulate the 8uadrature +irror 3ilter ?8+3@ using the simulation 'ackage

?+9#B@.

TOOLS RE!IRED:

+9#B

PROCED!RE:

"elect 3ileNew+!file

9y'e the 'rogram.

"ave it.

Run the 'rogram to get the desired waveform.

50


51/54

PROGRAM:

Z #oad scaling filter associated with an orthogonal wavelet.

#oad db0A

"ub'lot ?12@A stem ?db0@A title ?Ddb0 low!'ass filterD@A

Z Com'ute the ,uadrature mirror filter.,mfdb0 ,mf?db0@A

sub'lot?122@A stem?,mfdb0@A title?D8+3 db0 filterD@A

Z Check for fre,uency condition ?necessary for orthogonality@:

Z abs?fft?filter@@[2 G abs?fft?,mf?filter@@[2 at each

Z fre,uency.

m fft?db0@A

mt fft?,mfdb0@A

fre, J:length?db0@KUlength?db0@A

sub'lot?121@A 'lot?fre,>abs?m@@A

title?D9ransfer modulus of db0D@

sub'lot?124@A 'lot?fre,>abs?mt@@A

title?D9ransfer modulus of 8+3 db0D@

sub'lot?125@A 'lot?fre,>abs?m@.[2 G abs?mt@.[2@A

title?DCheck 8+3 condition for db0 and 8+3 db0D@

*label?D abs?fft?db0@@[2 G abs?fft?,mf?db0@@[2 D@

5


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O!TP!T:

52


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51


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RES!LT:

9hus the 8uadrature +irror 3ilter ?8+3@ was simulated using +9#B software.

electronic+system+design 1

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