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SCHOOL FOR ELECTRICAL, ELECTRONIC AND COMPUTER ENGINEERING

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Figure 3.1 Basic Common-Emitter Design Layout ................... 2

Figure 3.2 Basic Class-AB Output stage Design Layout ............ 3

Figure 3.3 Modified Widlar Current Source Design Layout ......... 4

Figure 4.1 Basic Common-Emitter Design Layout ................... 5

Figure 4.2 Basic Cascode Design Layout .......................... 8

Figure 4.3 Common-Emitter Circuit - AC Analysis ................ 11

Figure 4.4 Common-Emitter Circuit - DC Analysis ................ 12

Figure 4.5 Common-Emitter Circuit - AC Simulation results ...... 12

Figure 4.6 Cascode Circuit - AC Analysis ....................... 13

Figure 4.7 Common-Emitter Circuit - DC Analysis ................ 13

Figure 4.8 Cascode Circuit - AC Simulation results ............ 14

Figure 5.1 Basic Common-Emitter Design Layout1................. 14

Figure 5.2 Class-AB amplifier with VBE multiplier, simulated .... 16

Figure 5.3 Class-AB amplifier with VBE multiplier, results ...... 16

Figure 6.1 Modified Widlar Current-Source Circuit .............. 17

Figure 6.2 Modified Widlar Current-Source ..................... 19

Figure 6.3 Modified Widlar Current-Source - Results ........... 19

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1. INTRODUCTION .................................................1

2. PURPOSE ......................................................1

3. LITERATURE ...................................................2

3.1 Design Problem D7.72 ................................ ............ 2

3.2 Design Problem D8.49 ................................ ............ 3

3.3 Design Problem D10.87 ................................ ........... 4

4. DESIGN - Problem D7.72 .......................................5

4.1 Common-Emitter ................................ ................. 5

4.1.1 Common-Emitter - Design Entities ...................................... 5

4.1.2 Common-Emitter - Design Procedure ..................................... 6

4.2 Cascode Design ................................ ................. 8

4.2.1 Cascode - Design Entities ............................................ 8

4.2.2 Cascode - Design Procedure ........................................... 9

4.3 Design Simulations ................................ ............. 11

4.3.1 Simulation and Results - Common-Emitter Amplifier .................. 11

5.1 Simulation and Results - Cascode Amplifier ..................... 13

5. DESIGN - Problem D8.49......................................14

5.1 Class-AB Output Stage ................................ .......... 145.1.1 Class-AB Output Stage - Design Entities ............................. 15

5.1.2 Class-AB Output Stage - Design Procedure ............................ 15

5.2 Design Simulations ................................ .......... 15

5.2.1 Simulation and Results - Class-AB Amplifier........................ 16

6. DESIGN - Problem D10.87 .....................................17

6.1 Modified Widlar Current-Source ................................ . 17

6.1.1 Modified Widlar Current-Source - Design Entities .................. 17

6.1.2 Modified Widlar Current-Source - Design Procedure .................. 17

6.2 Design Simulations ................................ .......... 19

6.2.1 Simulation and Results - Modified Widlar Current-Source ........... 19

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As referred to the section 2, three simulations have been conducted, in

order to investigate the design procedures and functioning of various

electronic circuit types. Section 3 contains basic information on the

circuit type, with applicable design equations. Sections 4, 5 and 6 each

describes the simulation and design process of each respective problem.

The aim of the simulation problems give students the opportunity to

improve on their simulation skills and to build confidence in designing

and verifying circuit designs. Three problems must be completed in order

to facilitate a successful outcome. This encompasses the performing of

hand calculations and design of a preliminary circuit. Hereafter the

design must be simulated in PSPICE and improved further to ensure a well-

functioning circuit and minimizing fiddling time.

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3.1 Design Problem D7.72The single stage common emitter amplifier circuit shown in figure 3.1 uses what is called Voltage Divider

Biasing. This type of biasing arrangement uses two resistors as a voltage divider network and is commonly

used in the design of BJT amplifier circuits.

Figure 3.1 Basic Common-Emitter Design Layout

Before attempting to design a transistor amplifier circuit, we look at some very important design equations.The most commonly used equations are listed below, to aid in the design effort. The first few equations are

derived from Ohm's Law, whilst the last few equations deal with transistor gain.

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3.2 Design Problem D8.49The Class-AB amplifier, shown infigure 3.2, implements a VBE multiplier to provide a tuneable bias voltage VBB

to the transistors Q9 and Q10. This enables accurate biasing to suit transistor type and specification. This

configuration yields characteristics close to that of a Class-B amplifier.

Figure 3.2 Basic Class-AB Output stage Design Layout

Before attempting to design a transistor amplifier circuit, we look at some very important design equations.

The most commonly used equations are listed below, to aid in the design effort.


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3.3 Design Problem D10.87The modified Widlar current source, shown in figure 3.3, provides the advantage that resistances may be

limited to the kilo ohm range. This is vital in the applications of IC designs, as large resistance values are

difficult to implement and fabricate.

Figure 3.3 Modified Widlar Curren t Source Design Layout

Before attempting to design a transistor amplifier circuit, we look at some very important design equations.

The most commonly used equations are listed below, to aid in the design effort.


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4.1 Common-EmitterThe single stage common emitter amplifier circuit shown in figure 4.1 is the physical model that is to be

designed and implemented. The various design components have been encircled, and are described in theproceeding section.

Figure 4.1 Basic Common-Emitter Design Layout

4.1.1 Common-Emitter - Design Entities

- Entity 1

With entity 2 basically functioning as a Thevenin equivalent circuit, we need to separate the two

"sources" i.e. the signal source and the Thevenin Source, by introducing a blocking or coupling

capacitor, which acts as an open circuit to DC input. One must also remember thus, that RS does not

affect the bias of the transistor. The capacitor charges to the DC bias source, VB, to satisfy Kirchhoff's

voltage law and the DC bias is in series with the signal source.

DESIGN GOAL: for f flow = 10Hz, set the value of C1 so that its voltage drop VC1 is negligible at the

lowest operating frequency flow.

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- Entity 2

This type of biasing arrangement uses two resistors as a potential divider network. This method of

biasing the transistor greatly reduces the effects of varying Beta by holding the base bias at a

constant steady voltage level allowing for best stability. The quiescent Base voltage is determined by

the potential divider network formed by the two resistors.

- Entities 3 & 4

The capacitor across the emitter resistance R2_2 increases the current gain to the beta of the

particular transistor used. This value is determined using the resistor R2_1 as reference. We

implement this entity when maximum gain is desired.

4.1.2 Common-Emitter - Design Procedure

First, we decide upon certain initial values and components to be used. The input voltage, Vcc, is a

source providing V+ = 10V and V- = -10V, connected to the circuit as in figure 4.1. The collector

current must be in the range of Ic = 500uA. The transistor Beta, or DC current gain is 75. The

transistor to be used, is the 2N2222 NPN transistor.

Using the formula for DC gain, we can calculate the base current as:

To calculate the collector resistance, we use the first equation given in section 3, and we assume that

half of the supply voltage is dropped over R1. This ensures that the amplifier remains in the linear

operating range of the transistor:

We need to determine how much voltage is to appear across the emitter resistor, R2, before we

calculate its actual value. A good value is between 5 and 10 percent of Vcc. We choose 7.5%, which

is about 1.5V. This voltage represents VR2 = 1.5V. Therefore:

Because the voltage drop across the base to emitter of a silicon transistor is always 0.7V, the voltage

from the base to V- is 1.5V + 0.7V = 2.2V. This is the voltage drop across resistor R4. In order to

provide a stable base voltage, resistor R4 should have a current of about 5 to 10 times the base

current. We assume 9 times the base current for a total of 59.99uA. The value of R4 is thus:


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If the voltage drop across R4 is 2.2V, the voltage drop across R3 must be the remainder, or 20V - 2.2V

= 17.8V. The current through R3 is the sum of the current through R4 and the base, thus 6.66uA +

59.99uA = 66.66uA. We calculate the value for R3 as follows:

In order to choose a value for the bypass capacitor C1, we assume that the voltage drop across the

capacitor is in the order of . Using equation 3, we calculate the bypass capacitor C1, with

=> Rb = 32.24k:

In order to achieve reasonable gain with this circuit, we split R2 into R2_1 and R2_2, make R2_1 = 30


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4.2 Cascode DesignThe Cascode amplifier circuit shown in figure 4.2 is the physical model that is to be designed and

implemented. The various design components have been encircled, and are described in the proceeding

section.

Figure 4.2 Basic Cascode Design Layout

4.2.1 Cascode - Design Entities

- Entity 1

With entity 2 basically functioning as a Thevenin equivalent circuit for transistor Q2, we need to

separate the two "sources" i.e. the signal source and the Thevenin Source, by introducing a blocking

or coupling capacitor, which acts as an open circuit to DC input. One must also remember thus, that

RS does not affect the bias of the transistor. The capacitor charges to the DC bias source, VB, to

satisfy Kirchhoff's voltage law and the DC bias is in series with the signal source.

DESIGN GOAL: for f flow = 10Hz, set the value of C1 so that its voltage drop VC1 is negligible at the

lowest operating frequency flow.

1

2

3


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- Entity 2

This type of biasing arrangement uses two resistors as a potential divider network, for each

transistor. This method of biasing the transistor greatly reduces the effects of varying Beta by holding

the base bias at a constant steady voltage level allowing for best stability. The quiescent Base voltage

is determined by the potential divider network formed by the two resistors, relative to each

transistor.

- Entity 3

The capacitor across the emitter resistance R7 increases the current gain to the beta of the particular

transistor used. This value is determined using the resistor R4 as reference. We implement this

entity when maximum gain is desired.

4.2.2 Cascode - Design Procedure

First, we decide upon certain initial values and components to be used. The input voltage, Vcc, is a

source providing V+ = 10V and V- = -10V, connected to the circuit as in figure 4.2. The collector

current must be in the range of Ic = 500uA. The transistor Beta or DC current gain of both transistors

is 75. The transistors to be used are the 2N2222 NPN transistors.

Using the formula for DC gain, we can calculate the base current of transistor Q1 as:

The base current of transistor Q2 can be calculated similarly as:

To calculate the collector resistance, we use the first equation given in section 3.2, and we assume

that a quarter of the supply voltage is dropped over R1. This ensures that the amplifier remains in

the linear operating range of the transistor:

We need to determine how much voltage is to appear across Q2's emitter resistor, RE, before we

calculate its actual value. A good value is between 5 and 10 percent of Vcc. We choose 7.5%, which

is about 1.5V. This voltage represents VR2 = 1.5V. Therefore:

Because the voltage drop across the base to emitter of a silicon transistor is always 0.7V, the voltage

from the base to V- is 1.5V + 0.7V = 2.2V. This is the voltage drop across resistor R5. In order to

provide a stable base voltage, resistor R5 should have a current of about 5 to 10 times the base

current. We assume 9 times the base current for a total of 60.84uA. The value of R5 is thus:


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The voltage drop across R3 is equivalent to the voltage drop across the transistor Q1, thus:

If the voltage drop across R5 is 2.2V and R3 is 0.7V, the voltage drop across R2 must be the remainder,

or 20V - 2.2V - 0.7V = 17.1V. The current through R2 is the sum of the current through R3 and the

base of Q1, thus 6.66uA + 67.6uA = 74.26uA. We calculate the value for R2 as follows:

In order to choose a value for the bypass capacitor C1, we assume that the voltage drop across the

capacitor is in the order of . Using equation 3, we calculate the bypass capacitor C1, with

=> Rb = 8.05k:

In order to achieve reasonable gain with this circuit, we split RE into R4 and R7, make R4 = 20


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4.3 Design SimulationsThe Cascode amplifier circuit shown in figure 4.2 is the physical model that is to be designed and

implemented. The various design components have been encircled, and are described in the proceeding

section.

In this section, the circuits that were designed in section 4 are simulated, with resulting gain graphs

illustrated, proving that the designs are within specification.

4.3.1 Simulation and Results - Common-Emitter Amplifier

Figure 4.3 Common-Emitter Circuit - AC Analysis


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Figure 4.4 Common-Emitter Circuit - DC Analysis

Figure 4.5 Common-Emitter Circuit - AC Simulation results

In the above graph, the green line represents the voltage across the load; the purple line represents the

voltage gain in dB; and red represents the input signal voltage. The gain provided is +34dB, with a lower cut-

off frequency of + 10Hz.


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4.3.2 Simulation and Results - Cascode Amplifier

Figure 4.6 Cascode Circui t - AC Analysis

Figure 4.7 Common-Emitter Circuit - DC Analysis


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Figure 4.8 Cascode Circuit - AC Simulation results

In the above graph, the red line represents the voltage across the load; the green line represents the voltage

gain in dB; and purple represents the input signal voltage. The gain provided is +34.1dB, with a lower cut-off

frequency of + 12Hz.


5.1 Class-AB Output StageThe Class-AB amplifier output stage with VBE multiplier circuit shown infigure 5.1 is the physical model that is to

be designed and simulated. The two main design components have been encircled, and are described in the

proceeding section.

Figure 5.1 Basic Common-Emitter Design Layout1

1

2


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5.1.2 Class-AB Output Stage - Design Procedure

First, we decide upon certain initial values and components to be used. Through observation, we can

deduce that transistors Q9 and Q10 will have to be able to transfer large amounts of current, and

hence, have high power dissipation capabilities. Therefore, Tip31 and Tip32 power BJT's were

chosen. We therefore assume a beta, or DC current gain of 20 and 50 respectively.

From the specification, we can determine the peak output voltage using the equation for average

power:

Since the peak output voltage must be no more that 80% of V+, it follows that:

At this peak output voltage, the emitter current of Q9 is approximately equal to the load currentand

therefore:

We want the VBE multiplier to bias the circuit such that VBB is equal to 2VBEQx = 3.2V

Therefore the resistance pair, R1 and R2 must be chosen such that a voltage drop of 3.2 occurs:

5.2 Design Simulations

In this section, the circuits that were designed in section 5.1 are simulated, with resulting voltage and power

graphs illustrated, proving that the designs are within specification.

5.1.1 Class-AB Output Stage - Design Entities

- Entity 1

Entity one represents the VBE multiplier, which provides entity 2 with a voltage bias of 3.2V.


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5.2.1 Simulation and Results - Class-AB Amplifier

Figure 5.2 Class-AB amplifier with VB E multiplier, simulated

Figure 5.3 Class-AB amplifier with VB E multiplier, results


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6.1.2 Modified Widlar Current-Source - Design Procedure

First, we decide upon certain initial values and components to be used. The circuit is biased by

voltages V+ = 9V and V- = -9V, connected to the circuit as infigure 6.1. The output current must be in

the range of IO = 200A. The transistors' Beta values, or DC current gain values are assumed to be

150. The saturation current of the transistors is IS = 10-14

A, and have an early voltage of VA = 120V.

The transistors to be used, are the 2N2222 NPN transistors.

Using the formula for the output current, we can calculate the base-emitter voltage as:


6.1Modified Widlar Current-SourceThe single stage common emitter amplifier circuit shown infigure 4.1 is the physical model that is to be designed

and implemented. The various design components have been encircled, and are described in the proceeding

section.

Figure 6.1 Modified Widlar Current-Source Circuit

6.1.1 Modified Widlar Current-Source - Design Entities

- Entity 1

Entity 1 represents a two-transistor current source, also called a current mirror, as described in section 3.

The output impedance, RO, has a magnitude of 5.0M.

DESIGN GOAL: we need to determine the values for the resistors which will guarantee an output current,

IO, of 200A.

1VC2

IREF

IO

RO


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The calculation of parameters r2, gm2 and rO2 follows from the equations:

To calculate the emitter resistance of transistor Q2, it follows from the equations that:

Finally, we must calculate the power dissipation of each resistor. This is done using the equation for

power:

The circuit, using the determined values has been simulated, and the results are included in section

6.2 In order to do a physical implementation of this circuit, we require standard resistor values,

followed by a simulation of the standard circuit. Luckily the resistor values can be used asdetermined in a standard implementation, therefore no modifications are needed.


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6.2 Design Simulations

In this section, the circuit that was designed in section 6.1 is simulated, with resulting voltage graphs, proving

that the designs are within specification.

6.2.1 Simulation and Results - Modified Widlar Current-Source

Figure 6.2 Modified Widlar Current-Source

Figure 6.3 Modified Widlar Current-Source - Results

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