electronics 2012

2012

Submitted To: Sir. Zia

Subject: Digital Electronic

Topic: Counters

Department Of The Space Sciences

University Of The Punjab

Submitted By:

Atiqa Ijaz Khan 03 Farwa Tariq 04

M.Adnan 06 Zertasha Ramzan 10

Anum Mumtaz 29 Zernain Shakoor 32

Department of the Space Sciences [5th Semester, Session 2009-13]

2

1. Abstract 03

2. Section I: Project Work 04

Introduction To Project Theme 04

Circuit Diagram 05

Material List 06

Truth Table 13

Procedural Work 16

Finalization 17

3. Section II: Theoretical Background 18

Introduction To The Flip Flops 18

Introduction To The Counters 24

Types Of Counters 27

4. References 33


3

Abstract

This paper describes one aspect of making of the counters. Our approach is to have a handover over the practicality of the Counters, for which the

opportunity is provided by the Department Of The Space Sciences.

Section I deals with the idea of the Project Work, with the circuit diagram, used materials and the procedure.

While the Section II describes the Theoretical Background behind the entire Practical. It starts from flip flops with counters and its all types.


4

Section I: Project Work

Introduction To The Project Theme:

Our project is based on the making of Counters, counting starts:

1. Directly from 400-500

2. Or from 0-500 and back to the 400-500 onwards.

We have the following options to deal within the types of the counters:

1. Asynchronous Counters.

2. Synchronous Counters.

We prefer on using Asynchronous Counters as:

1. Clock is provided to just 1st flip flop.

2. To know which type gives the more efficient result regarding counters.

3. As per easy to deal with asynchronous counters.

4. Much clean and easy to draw circuit.


5

Circuit Diagram:


6

Material List:

The following is the list of the material used in the making of the project:

Serial No. Components Device Number No. of components used

01 Flip flop 74S112 09

02 AND-Gate 7408(2-inputs) 03

03 OR-Gate 7432(2-inputs) 02

04 NAND-Gate 74S10(3-inputs) 02

05 BCD to 7 Segment 74LS47 03

06 Bread Board 02

07 Wires Bundle of Wires

08 Plastic Bag 01

09 LEDs 09

Where:

Red wire= ; Yellow wire= ; Blue wire= ; Black wire=


7

Review About Flip Flop 74S112:

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs

regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are

transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise

time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These

versatile flip-flops can perform as toggle flip-flops by tying J and K high. The 74S112 is characterized for operation from 0°C to 70°C.


8

Review About OR-Gate 7432:


9

Review About AND-Gate 7408:

Review About NAND-Gate 7400:


10

BCD To 7 Segment Converters:

Asynchronous inputs on a flip-flop have control over the outputs (Q and not-Q) regardless of clock input status.These inputs are called the preset (PRE)

and clear (CLR). The preset input drives the flip-flop to a set state while the clear input drives it to a reset state. It is possible to drive the outputs of a J-K

flip-flop to an invalid condition using the asynchronous inputs, because all feedback within the multivibrator circuit is overridden.

This package accepts a 1-2-4-8 positive-logic Binary Coded Decimal (BCD) input and converts it to the proper pattern necessary to illuminate a 7

segment display. A low output is intended to light the segment. (Common anode).

The outputs can sink 40milliamperes (mA) in the low state and can withstand 30 volts in the high state. The supply voltage must remain at 5+ volts. An

output-high state can be obtained only if a display device or resistor pulls the output to some positive voltage less than 30 volts.

Current-liminting resistors, typically 330 ohms, must be used when driving a light emitting diode display with this package. Incandescent or fluorescent


11

readouts can be driven directly.

The Lam test input should remain high when not in use. To enable the lamp test feature, momentarily

bring the Lamp Test input to ground, this will illuminate all of the segment outputs (for testing). A low

on the blanking input will extinguish character "0". A low on the Blanking output is provided to

extinguish the character "0" of the next stage if leading-edge blanking is desired.

A low on the Blanking output will extinguish the display.

Propagation delay = 45 nanoseconds

Current per Package = 43 milliamperes (mA)

7447 BCD to 7-segment display driver

The appropriate outputs a-g become low to display the BCD (binary coded decimal) number supplied on inputs A-D. The 7447 has open collector outputs

a-g which can sink up to 40mA. The 7-segment display segments must be connected between +Vs and the outputs with a resistor in series (330 with a

5V supply). A common anode display is required.

Display test and blank input are active-low so they should be high for normal operation. When display test is low all the display segments should light

(showing number 8).

http://www.kpsec.freeuk.com/components/ic.htm#sinksource


12

If the blank input is low the display will be blank when the count input is zero (0000). This can be used to blank leading zeros when there are several

display digits driven by a chain of counters. To achieve this blank output should be connected to blank input of the next display down the chain (the next

most significant digit).

The 7447 is intended for BCD (binary coded decimal) which is input values 0 to 9 (0000 to 1001 in binary). Inputs from 10 to 15 (1010 to 1111 in binary)

will light odd display segments but will do no harm.


13

Truth Table:

The truth table is from 400-500 as shown below:

Decimal A B C D E F G H I 400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1


14

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

452

453

454

455

456

457

458

459

460

461

462

463

464

465

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1


15

466

467

468

469

470

471

472

473

474

475

476

477

478

479

480

481

482

483

484

485

486

487

488

489

490

491

492

493

494

495

496

497

498

499

500

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1


16

Procedure:

1. Initially we made the truth table from 400-500 for 9-bit code.

2. The 2nd step was the designing of the circuit or the paper work.

a. The circuit was designed in the procedural way with the help of the truth table.

b. Then by the help of the AND, OR and NAND Gates we arranged the decoder format of counter.

c. LEDs are used to display the outputs for checking.

d. While 7 Segment is used to display the final output by using BCD to 7 Segment decoder.

e. For best working it could be tested on simulation model like:

i. Proteus

ii. Multisim

Its an optional and is used during our project.

3. Transform all this paper work on the bread board (junction to 2 bread boards are used to accumulate the whole circuit).

4. 1st bread board is used for the flip flops while 2nd is for 7 segment along with the decoder display for a better look.

5. VCC and GND are distributed on two sides of the bread board for cleanness in the circuit.

6. All the forms of power supply is given by DC source up to 5volt.

7. While clock must be of 1kHz at minimum rate. Increasing the frequency of the clock makes the counting frequency increased.


17

Finalization:

At last we had done with the circuit.

The speed of the counting can be varied by the varying the frequency of the clock.


18

Section II: Theoretical Background

Introduction To The Flip Flops:

In electronics, a flip-flop is a circuit that has two stable states and can be used to store state information. It is a synchronous version of the latch. The

memory elements in a sequential circuit are called flip-flops. A flip-flop circuit has two outputs, one for the normal value and one for the complement

value of the stored bit. Binary information can enter a flip-flop in a variety of ways and gives rise to different types of flip-flops.

A flip-flop is usually controlled by control signals that can include a clock signal. The outputs usually include the complement as well as the normal

output.

A digital clock signal is basically a square wave voltage similar as the one shown below:

As shown, it has only two levels, one is zero and the other one is high, which the high level can be different according to the requirement of the circuit.

The clock pulse goes through two signal transitions: from 0 to 1 and the return from 1 to 0. As shown in fig. below the positive transition is defined as the

positive edge and the negative transition as the negative edge.

http://www.wikipedia.org/wiki/Electronics

http://www.wikipedia.org/wiki/Electronic_circuit

http://www.wikipedia.org/wiki/Signals

http://www.wikipedia.org/wiki/Clock_signal

http://www.wikipedia.org/wiki/Output

http://www.wikipedia.org/wiki/Logical_complement

http://www.designcabana.com/knowledge/electrical/basics/voltage


19

Clocked SR Flip-Flop

The clocked SR flip-flop shown in Figure 4 consists of a basic NOR flip-flop and two AND gates. The outputs of the two AND gates remain at 0 as long

as the clock pulse (or CP) is 0, regardless of the S and R input values. When the clock pulse goes to 1, information from the S and R inputs passes

through to the basic flip-flop. With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to momentarily go to 0. When the pulse is

removed, the state of the flip-flop is indeterminate, ie., either state may result, depending on whether the set or reset input of the flip-flop remains a 1

longer than the transition to 0 at the end of the pulse.

SR Flip Flop is not available in ICs form.

http://wearcam.org/ece385/lectureflipflops/flipflops/#Figure_4


20

D Flip-Flop

The D flip-flop shown in Figure 5 is a modification of the clocked SR flip-flop. The D input goes directly into the S input and the complement of the D

input goes to the R input. The D input is sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set state (unless it was

already set). If it is 0, the flip-flop switches to the clear state.



21

JK Flip-Flop

A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type. Inputs J and K behave like inputs

S and R to set and clear the flip-flop (note that in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic 1 inputs are applied to both

J and K simultaneously, the flip-flop switches to its complement state, i.e., if Q=1, it switches to Q=0 and vice versa.

A clocked JK flip-flop is shown in Figure 6. Output Q is ANDed with K and CP inputs so that the flip-flop is cleared during a clock pulse only if Q was

previously 1. Similarly, output Q' is ANDed with J and CP inputs so that the flip-flop is set with a clock pulse only if Q' was previously 1.

Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while J=K=1) after the outputs have been complemented

once will cause repeated and continuous transitions of the outputs. To avoid this, the clock pulses must have a time duration less than the propagation

delay through the flip-flop. The restriction on the pulse width can be eliminated with a master-slave or edge-triggered construction. The same reasoning

also applies to the T flip-flop presented next.



22

Asynchronous flip-flop inputs

The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous inputs because they have effect on the outputs (Q and not-Q)

only in step, or in sync, with the clock signal transitions. These extra inputs that I now bring to your attention are called asynchronous because they can

set or reset the flip-flop regardless of the status of the clock signal. Typically, they're called preset and clear:


23

When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of any of the synchronous inputs or the clock. When the clear input

is activated, the flip-flop will be reset (Q=0, not-Q=1), regardless of any of the synchronous inputs or the clock. When both preset and clear inputs are

activated we get an invalid state on the output, where Q and not-Q go to the same state, the S-R latch! Preset and clear inputs find use when multiple flip-

flops are ganged together to perform a function on a multi-bit binary word, and a single line is needed to set or reset them all at once.

Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or active-low. If they're active-low, there will be an inverting

bubble at that input lead on the block symbol, just like the negative edge-trigger clock inputs.

Sometimes the designations "PRE" and "CLR" will be shown with inversion bars above them, to further denote the negative logic of these inputs:


24

Introduction To The Counters:

Counter is basically an apparatus used for counting.

Let us take a look at the definition given by the IBM Dictionary of Computing:

Counter: A functional unit with a finite number of states each of which represents a number that can be, upon receipt of an appropriate signal,

increased by unity or by a given constant. This device is usually capable of bringing the represented number to a specified value; for example zero.

It is another application of the flip flops.

Where;

Jo, Ko, J1, K1=inputs Qo, Q1=Outputs C=Clock FF0, FF1=Flip flops


25

Why do we need counters?

In a digital circuit, counters are used to do 3 main functions: timing, sequencing and counting.

A timing problem might require that a high-frequency pulse train, such as the output of a 10-MHz crystal oscillator, be divided to produce a pulse

train of a much lower frequency, say 1 Hz. This application is required in a precision digital clock, where it is not possible to build a crystal

oscillator whose natural frequency is 1 Hz.

A sequencing problem would arise if, for instance, it became necessary to apply power to various components of a large machine in a specific

order. The starting of a rocket motor is an example where the energizing of fuel pumps, ignition, and possibly explosive bolts for staging must

follow a critical order.

Measuring the flow of auto traffic on roadway is an application in which an event (the passage of a vehicle) must increment a tally. This can be

done automatically with an electronic counter triggered by a photocell or road sensor. In this way, the total number of vehicles passing a certain

point can be counted.

How are counters made?

Counters are generally made up of flip-flops and logic gates. Like flip-flops, counters can retain an output state after the input condition which

brought about that state has been removed. Consequently, digital counters are classified as sequential circuits. While a flip-flop can occupy one of

only two possible sattes, a counter can have many more than two states. In the case of a counter, the value of a state is expressed as a multidigit

binary number, whose `1's and `0's are usually derived from the outputs of internal flip-flops that make up the counter. The number of states a

counter may have is limited only by the amount of electronic hardware that is available. The main types of flip-flops used are J-K flip-flops or T

flip-flops, which are J-K flip-flops with both J and K inputs tied together. Before that, here's a quick reminder of how a J-K flip-flop works:

J input K input Output, Q

0 0 Q

0 1 0

1 0 1

1 1 not Q


26

The flip-flops are used because set/reset ([1,0] [0,1]) functions are seldom used. Only the "do nothing" and toggle ([0,0] [1,1]) functions are used.

Logic gates are used to decide when to toggle which outputs. Below is an example of a synchronous binary counter, implemented using J-K flip-

flops and AND gates.


27

Types Of The Counters:

Counters are generally divided into two following types:

1. Synchronous Counters.

2. Asynchronous Counters.

Synchronous Counters:

According to the Oxford Encyclopedic Dictionary:

Synchronous: Existing or occurring at the same time.

Look at the definition given by the IBM Dictionary of Computing:

Synchronous: Pertaining to two or more processes that depend upon the occurrence of specific events such as common timing signals.

Occurring with a regular or predictable time relationship.

Synchronous – Events that have fixed time relationship with each other and generally, occur at the same time.

So a "synchronous counter" is actually a functional unit with a certain number of states, each representing a number which can be increased or decreased

upon receiving an appropriate signal (e.g. a rising edge pulse), and is usually used to count to, or count down to zero from, a specified number N.


28

And what it "really" means?: Basically, any sequential circuit that goes through a prescribed sequence of states upon the application of input pulses is called a counter. The input

pulses, called count pulses, may be clock pulses or they may originate from an external source and may occur at prescribed intervals of time or at

random. The sequence of states in a counter may follow a binary count or any other sequence.

Synchronous Counters: use edge-triggered flip-flops that change states on either the "positive-edge" (rising edge) or the "negative-edge" (falling

edge) of the clock pulse on the control input resulting in one single count when the clock input changes state. Generally, synchronous counters

count on the rising-edge which is the low to high transition of the clock signal and asynchronous ripple counters count on the falling-edge which is

the high to low transition of the clock signal.


29

It may seem unusual that ripple counters use the falling-edge of the clock cycle to change state, but this makes it easier to link counters together because

the most significant bit (MSB) of one counter can drive the clock input of the next. This works because the next bit must change state when the previous

bit changes from high to low - the point at which a carry must occur to the next bit. Synchronous counters usually have a carry-out and a carry-in pin for

linking counters together without introducing any propagation delays.

2-bit Synchronous Counters Operation:

Digital Circuit’s clock inputs are all wired together. With all clock inputs wired together, propagation delay is assumed to be equal. Propagation Delay

occurs from the triggering edge of the input clock pulse. Each FF’s Q-outputs toggle simultaneously. Response time for a Synchronous counter is faster

than Asynchronous circuit. A 2 Bit Binary Synchronous Counter can be built quite easily.


30

A 3bit synchronous binary counter:

This counter uses a “AND” gate to detect Q and 0 and Q outputs of FF0 and FF1. Q1 outputs of FF0 and FF1 This condition is unique because both

outputs are “Hi” simultaneously. The “AND” is used to assure that FF2 toggles properly.The FFs are positive edge triggered devices.


31

A 4bit synchronous decade counter:

This counter uses a “AND” gates and “OR” gates to detect Q , Q and Q outputs of FF0, FF1 and Q and Q outputs of FF0, FF1 and FF2 as well as

truncating to the appropriate count sequence (MOD 10). This condition is unique because outputs are “Hi” simultaneously. The “AND” is used to assure

that FF2 and FF3 toggles properly and the “OR” gate for partial decoding the correct truncate count sequence (1001). The FFs are positive edge

triggered devices. The “AND” and “OR” gates assist in the Partial Decoding for truncating the sequence for MOD 10 counting. Count value is

incremented on the positive edge of the input clock signal.


32

Advantages of Synchronous Counters:

1. Synchronous counters are easier to design.

2. With all clock inputs wired together there is no inherent propagation delay.

3. Overall faster operation may be achieved compared to Asynchronous counters.


33

Asynchronous Counters:

We know that the output of one counter stage is connected directly to the clock input of the next counter stage and so on along the chain, and as a result

the asynchronous counter suffers from what is known as "Propagation Delay".

The difference between asynchronous and synchronous counters: In an asynchronous counter, an external event is used to directly SET or

CLEAR a flip-flop when it occurs. In a synchronous counter however, the external event is used to produce a pulse that is synchronised with the

internal clock. An example of an asynchronous counter is a ripple counter. Each flip-flop in the ripple counter is clocked by the output from the

previous flip-flop. Only the first flip-flop is clocked by an external clock. Below is an example of a 4-bit ripple counter:


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Asynchronous Decade Counter:

If we take the modulo-16 asynchronous counter and modified it with additional logic gates it can be made to give a decade (divide-by-10) counter output

for use in standard decimal counting and arithmetic circuits.

Such counters are generally referred to as Decade Counters. A decade counter requires resetting to zero when the output count reaches the decimal value

of 10, ie. when DCBA = 1010 and to do this we need to feed this condition back to the reset input. A counter with a count sequence from binary "0000"

(BCD = "0") through to "1001" (BCD = "9") is generally referred to as a BCD binary-coded-decimal counter because its ten state sequence is that of a

BCD code but binary decade counters are more common.

This type of asynchronous counter counts upwards on each leading edge of the input clock signal starting from "0000" until it reaches an output "1010"

(decimal 10). Both outputs QB and QD are now equal to logic "1" and the output from the NAND gate changes state from logic "1" to a logic "0" level

and whose output is also connected to the CLEAR (CLR) inputs of all the J-K Flip-flops. This causes all of the Q outputs to be reset back to binary


35

"0000" on the count of 10. Once QB and QD are both equal to logic "0" the output of the NAND gate returns back to a logic level "1" and the counter

restarts again from "0000". We now have a decade or Modulo-10 counter.

Clock

Count

Output bit Pattern Decimal

Value QD QC QB QA

1 0 0 0 0 0

2 0 0 0 1 1

3 0 0 1 0 2

4 0 0 1 1 3

5 0 1 0 0 4

6 0 1 0 1 5

7 0 1 1 0 6

8 0 1 1 1 7

9 1 0 0 0 8

10 1 0 0 1 9

11 Counter Resets its Outputs back to Zero


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Disadvantages of Asynchronous Counters:

1. An extra "re-synchronizing" output flip-flop may be required.

2. To count a truncated sequence not equal to 2n, extra feedback logic is required.

3. Counting a large number of bits, propagation delay by successive stages may become undesirably large.

4. This delay gives them the nickname of "Propagation Counters".

5. Counting errors at high clocking frequencies.

6. Synchronous Counters are faster using the same clock signal for all flip-flops.


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Websites:

1. www.allaboutcircuits.com/vol_4/chpt_10/7.html.

2. www.alldatasheet.com.

3. www.avagotech.com/docs/AV02-2360EN.

4. www.datasheetcatalog.com/datasheets_pdf/7/4/3/2/7432.shtml.

5. www.digchip.com/datasheets/parts/datasheet/343/7432.php.

6. www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/cwl3/report.html

7. www.eshop.engineering.uiowa.edu/NI/pdfs/00/83/DS008332.pdf

8. www.family-science.net/ITTTech/Downloads/DWCH09Pt2.pdf

9. www.kpsec.freeuk.com/components/74series.htm#7447.

10. www.makeyourownchip.com/7447.html

11. www.manometer-thermometer.de/csdata/.../1/de/7400_eng_683.pdf

12. www.maxwell.ict.griffith.edu.au/yg/teaching/dns/dns_module3_p2.pdf

http://www.allaboutcircuits.com/vol_4/chpt_10/7.html

http://www.alldatasheet.com/

http://www.avagotech.com/docs/AV02-2360EN

http://www.datasheetcatalog.com/datasheets_pdf/7/4/3/2/7432.shtml

http://www.digchip.com/datasheets/parts/datasheet/343/7432.php

http://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/cwl3/report.html

http://www.eshop.engineering.uiowa.edu/NI/pdfs/00/83/DS008332.pdf

http://www.family-science.net/ITTTech/Downloads/DWCH09Pt2.pdf

http://www.kpsec.freeuk.com/components/74series.htm#7447

http://www.makeyourownchip.com/7447.html

http://www.manometer-thermometer.de/csdata/.../1/de/7400_eng_683.pdf

http://www.maxwell.ict.griffith.edu.au/yg/teaching/dns/dns_module3_p2.pdf


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13. www.nxp.com/documents/data_sheet/74F08.pdf

14. www.nalanda.nitc.ac.in/industry/datasheets/atmel/acrobat/doc0466.pdf.

15. www.play-hookey.com/digital/reverse_counter.html

16. www.sccs.swarthmore.edu/users/08/ajb/tmve/wiki100k/docs/Flip- flop_%28electronics%29.html

17. www.wearcam.org/ece385/lectureflipflops/flipflops/

Article:

1. Synchronous Counters - A Brief Introduction by Lee Chin Wei

Book:

1. Digital Fundaments by Thomas L. Floyd

http://www.nxp.com/documents/data_sheet/74F08.pdf

http://www.nalanda.nitc.ac.in/industry/datasheets/atmel/acrobat/doc0466.pdf

http://www.play-hookey.com/digital/reverse_counter.html

http://www.sccs.swarthmore.edu/users/08/ajb/tmve/wiki100k/docs/Flip-%20flop_%28electronics%29.html

http://www.wearcam.org/ece385/lectureflipflops/flipflops/

http://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol1/cwl3/index.html

electronics 2012

Education