electronic circuits laboratory experiments

8/6/2019 Electronic Circuits Laboratory Experiments

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SRI MANAKULA VINAYAGAR ENGINEERING

COLLEGE

MADAGADIPET, PONDICHERRY – 605 107.

Department of Electronics and

Communication Engineering

DEPARTMENT : ECE

SEMESTER/YEAR : V/III

NAME OF THE LAB : ELECTRONIC CIRCUITS II LAB

LIST OF EXPERIMENTS

Cycle-I

1 Negative Feedback Amplifier

2 Rc phase shift oscillators

3 Hartely and colpitts oscillators

4 Clampers and voltage multipliers

5 Astable multivibrator and monostable multivibrator

Cycle II

6 Bistable multivibrator and Schmitt trigger

7 Time base generators

8 UJT saw tooth generators

9 Class A power amplifiers

10 Class B complementary symmetry amplifier



1. VOLTAGE SERIES FEEDBACK AMPLIFIER

AIM:

To design a BJT Voltage series feedback amplifier and determine the

gain, frequency response, input and output impedances with and without

feedback.

DEVICES AND EQUIPMENTS REQUIRED:

THEORY:

An amplifier whose fraction of output is fed back to input is called

feedback amplifier. A feedback amplifier consists of two parts namely

amplifier circuit and feedback circuit. Depending upon whether the feedback

signal increases or decreases the input signal it is classified into two (i)

Positive feedback – If the feedback signal is in phase with the input signal. (ii)

Negative feedback – If the feedback signal is out of phase with the input

signal. The positive feedback increases the gain of the amplifier whereas the

negative feedback decreases the gain. In the current series feedback

connection a fraction of the output current is converted into a proportional

voltage by the feedback network and then applied in series with the input.

Sl.N Particulars Specification Range Quantity

1.

2.

3.

4.

5.

6.

Transistor

Resistors

Capacitor

CRO

Signal

Generator

Power Su l

BC107

(0-20)MHz

(0-1)MHz

(0-30)V

1

1

1



PROCEDURE: -

1. Connect the circuit as per the circuit diagram.

2. Set Vs = 50mV (assume) using the signal generator keeping the input

voltage constant, vary the frequency from 0Hz to 1MHz in regular

steps of 10 and note down corresponding output voltage.

3. Plot the frequency response: Gain (dB) vs Frequency (Hz).

4. Find the input and output impedance.

5. Calculate the bandwidth from the graph.

6. Note down the phase angle, bandwidth, input and output impedance.

Design Formula :

1. VCE =Vcc/2

2. VE = Vcc/10

3. Ib = IC/β

4. IC = IE

5. RE = VE/IE

6. RC = ( VCC – VCE -VE)/IC

7. RB = R1R2/(R1+R2)

8. RB = (S-1)RE

9. R1 = VCCRB/VB



Model Graph (Frequency Response) :-

Frequency in log scale

Circuit Diagram:



General Procedure for Calculation:

1. Input impedance

a) Connect a 10KΩ potentiometer between input voltage source and the

base of the transistor (series connection).

b) Vary the value of potentiometer such that the CRO produces half of the

input signal.

c) Note down the resistance of the potentiometer using multimeter,

which is the input impedance.

2. Output impedance

a) Connect a 10KΩ potentiometer between load and the collector of the

transistor (parallel connection).

b) Vary the value of potentiometer such that the CRO produces half of the

input signal.

c) Note down the resistance of the potentiometer using multimeter,

which is the output impedance.

3. Bandwidth

a) Plot the frequency response for both with and without feedback.



b) Identify the maximum gain region.

c) Drop a horizontal line bi –3dB.

d) The –3dB line intersects the frequency response plot at two points.

e) The lower intersecting point of –3dB line with the frequency response

plot gives the lower cut-off frequency.

f) The upper intersecting point of –3dB line with the frequency response

plot gives the upper cut-off frequency.

g) The difference between upper cut-off frequency and lower cut-off

frequency is called bandwidth. Thus Bandwidth = fh – fl.



RESULT:

Thus the gain, frequency response, input and output impedances with

and without feedback was designed and the readings were verified.



2. VOLTAGE SHUNT FEEDBACK AMPLIFIER

AIM:

To design and Construct a voltage shunt feedback amplifier circuit andalso to determine its frequency response characteristics.


THEORY:


1.

2.3.

4.

5.

6.

Transistor

ResistorsCapacitor

CRO

Signal

Generator

Power Su l

BC107

(0-20)MHz

(0-1)MHz

(0-30)V

1

1

1



An amplifier whose fraction of output is feedback to input is called

feedback amplifier. A feedback amplifier consists of two parts namely

amplifier circuit and feedback circuit. Depending upon whether the feedback

signal increases or decreases the input signal it is classified into two (i)

Positive feedback – If the feedback signal is in phase with the input signal. (ii)

Negative feedback – If the feedback signal is out of phase with the input

signal. The positive feedback increases the gain of the amplifier whereas the

negative feedback decreases the gain. In the voltage shunt feedback

connection a fraction of the output voltage is applied in parallel with the

input voltage through the feedback network. The voltage shunt feedback

connection decreases both the input and output resistance of the feedback

amplifier by a factor equal to (1+βAv).

FORMULA:

1) VCE = VCC/2

2) VE = VCC/10

3) VE = IERE

4) RC = (VCC – VCE – IE ) / IE

5) VB = VBE + VE

6) R1 = (S-1)RE

7) R1 = VCC.RB / VB

8) R2 = R1.RB / ( R1 – RB)

PROCEDURE:

1. Connections are given as the circuit diagram.



2. The DC supply is given and the unable resistor is adjusted to the

decided value

3. The output waveform is obtained and the time period and amplitude is

noted down.

4. The practical frequency is calculated and compared with the

theoretical frequency.

5. The waveform is noted in graph sheet

General Procedure for Calculation:

1. Input impedance

d) Connect a 10KΩ potentiometer between input voltage source and the

base of the transistor (series connection).

e) Vary the value of potentiometer such that the CRO produces half of the

input signal.

f) Note down the resistance of the potentiometer using multimeter,

which is the input impedance.

2. Output impedance

d) Connect a 10KΩ potentiometer between load and the collector of thetransistor (parallel connection).

e) Vary the value of potentiometer such that the CRO produces half of the

input signal.

f) Note down the resistance of the potentiometer using multimeter,

which is the output impedance.

3. Bandwidth

h) Plot the frequency response for both with and without feedback.

i) Identify the maximum gain region.

j) Drop a horizontal line bi –3dB.

k) The –3dB line intersects the frequency response plot at two points.



l) The lower intersecting point of –3dB line with the frequency response

plot gives the lower cut-off frequency.

m)The upper intersecting point of –3dB line with the frequency response

plot gives the upper cut-off frequency.

n) The difference between upper cut-off frequency and lower cut-off

frequency is called bandwidth. Thus Bandwidth = fh – fl.

Model Graph (Frequency Response) :

Frequency in log scale

Design:



RESULT:

Thus voltage shunt feedback amplifier was constructed and the

frequency response graph was plotted.

VIVA QUESTIONS:

1. What are the physical applications of a feedback amplifier?

2. Why is negative feedback used in RC – coupled amplifier?

3. What are the features of negative feedback?

4. Voltage Shunt amplifier is a Trans resistance amplifier: Justify?

5. A common – collector amplifier circuit is an example of which negative

feedback circuit?



3. HARTLEY OSCILLATOR

AIM:

To design and test for the performance of BJT – Hartley Oscillators.


THEORY:

The circuit diagram of Hartley Oscillator using BJT is shown. The

resistances R1 and R2 are the biasing resistances. The RFC is the radio

frequency choke. Its reactance value is very high for high frequencies; hence

it can be treated as open circuit. Hence due to RFC, the isolation between a.c

and d.c operation is achieved. RE is also a biasing circuit resistance and CE is

the emitter capacitor.

Operation:When the circuit is turned on, the capacitor is charged, this capacitor C

is discharged through L1 and L2 thus setting up frequency of oscillation.

f = 1/(2π√(L1+L2)C

or

f= 1/(2π√(L1+L2+2M)C

The output voltage of the amplifier appears across L2 and feedback voltage

across L1. The voltage L1 is 180o

out of phase with the voltage developed


1.

2.

3.

4.5.

6.

Transistor

Resistors

Capacitor

CROSignal

Generator

BC107

(0-20)MHz

(0-1)MHz

(0-30)V

1

1

1



across L1. A phase shift of 180o is produced by the transistor and a further

phase shift of 180o is produced by L1-L2 voltage divider which is necessary to

satisfy oscillation condition. The oscillator frequency can be varied by

varying the capacitor C. Variation over a wide range of frequency can be

easily obtained.



CIRCUIT DESIGN:



MODEL GRAPH:

DESIGN FORMULA:

1. F = 1 ∕ (2π√(Leq.C)

2. VCE = VCC/2

3. VE = VCC / 10

4. RC = ( VCC – VCE – VE) / IC

5. RE = VE / IE

6. VB = VBE + VE

7. R2 = R1.RB / (R1-RB)

8. R1 = VCC.RB / VB

9. RB = (S-1)RE

PROCEDURE: -

1. The Circuit connections are given as per the circuit diagram.



2. The DC supply is given and decade inductor box are adjusted to obtain

the required values.


noted down.



5. The waveform is plotted in graph sheet.

TABULAR COLUMN:

RESULT:

Thus the Hartley Oscillator was designed and constructed and the

output waveform was plotted in the graph sheet.

VIVA QUESTIONS:

1. What type of feedback is preferred in oscillators?

2. How does oscillation start in oscillators?

3. List out the applications of oscillators



4. Which oscillator is very suitable for audio range applications?

5. Which oscillator is suitable for RF range applications?

4. COLPITTS OSCILLATOR

AIM:

To design and test for the performance of BJT Colpitt’s Oscillators.


THEORY:

The Colpitt’s Oscillator is a LC oscillator. Generally, LC oscillators aredesigned to operate in the radio – frequency range above 1MHz however;

they can also be designed to produce oscillations in the low audio –

frequency range. But for low frequency operation, the size of the inductors to

be used become larger and larger as the frequency becomes smaller and

smaller and this puts a limit on the low frequency range of oscillators

employing LC – coupling network The frequency of oscillations is given by


1.

2.

3.

4.

5.

6.

Transistor

Resistors

Capacitor

CRO

Signal

Generator

BC107

(0-20)MHz

(0-1)MHz

(0-30)V

1

1

1



f o = 1 ∕ (2π√LC)

Where CT = C1C2 / C1 + C2, usually since Colpitt’s oscillator is a high

frequency oscillator the capacitors will be in the Pico farads range

PROCEDURE: -

1. Connect the circuit as per the circuit diagram (both oscillators).

2. Switch on the power supply and observe the output on the CRO (sine

wave).3. Note down the practical frequency and compare with its theoretical

frequency.



CIRCUIT DIAGRAM:



MODEL GRAPH :

DESIGN FORMULA:

1. VCE = VCC / 2

2. VE = VCC / 10

3. RE = VE / IE

4. RC = (VCC – VCE – VE) / IC

5. R1 = VCC.RB / VB

6. RB = (S-1) RE

7. R2 = R1RB / (R1 – RB)

8. f= 1/ (2π√(LCeq))

9. Ceq =C1C2 / (C1+C2)



TABULAR COLUMN:

RESULT:

Thus the Colpitts oscillator circuit is constructed and its waveform is

obtained.

VIVA QUESTIONS:

1. Which oscillator is suitable for low frequency applications?

2. Amplifier circuit is necessary in an oscillator, why?

3. Three RC sections are used in RC Phase Shift oscillators why?

4. Generally negative feedback is employed in amplifiers whereas

positive feedback is employed in oscillators, why?

5. For low frequency applications, we apply RC oscillators and not LC

oscillators why



5. RC PHASE SHIFT OSCILLATOR

AIM:

To design and test for the performance of RC Phase Shift Oscillator for

the given operating frequency f O.


THEORY:

Oscillator is a feedback circuit where a fraction of output voltage of an

amplifier is fed back to the input in the same phase. RC phase shift

oscillators are a sine wave oscillator which is used in the audio frequency

range. It has a CE amplifier which provides 1800 phase shift to the input

signal and three frequency selective RC phase shift networks provides a

phase shift of 600 of each, a total of 1800 for a signal with frequency equal

to specific value, which corresponds to the output of the oscillator. Thus the


1.

2.

3.

4.

5.

6.

Transistor

Resistors

Capacitor

CRO

Signal

Generator

BC107

(0-20)MHz

(0-1)MHz

(0-30)V

1

1

1



total phase shift between the input and output is 3600. The frequency of

oscillation is given by

f = 1/(2πRc √(6+4K))

PROCEDURE: -

1. Connect the circuit as per the circuit diagram (both oscillators).

2. Switch on the power supply and observe the output on the CRO (sine

wave).

3. Note down the practical frequency and compare with its theoretical

frequency.

Design:

MODEL GRAPH:



DESIGN FORMULA:

1. VCE = VCC / 2

2. VE = VCC / 10

3. VE = IERE

4. RC = (VCC - VCE – VE)/IE

5. R2 = R1RB/(R1+RB)

6. hie = hfe. 26mV/IE

7. Xci = [hie+(1+hfe)RE] || RE

8. Xci = 1/(2πf ci)

9. Xco = Rc/10

10.Xce = RE/10

11.CE = 1/(2πfXce)

TABULAR COLUMN:



RESULT:

Thus the RC phase shift oscillator was designed and the practical and

theoretical frequency was verified.

VIVA QUESTIONS:

1. What is meant by oscillator?

2. What are the advantages of positive feedback?

3. What are the advantages of negative feedback?

4. State Barkhausen criterion?

5. Compare amplifier and oscillator?

6. Give an example of LC oscillator?

7. Give an example of RC oscillator?



8. What are the disadvantages of negative feedback?

6. WEIN BRIDGE OSCILLATOR:

AIM:

To design, construct and to verify the performance of Wein Bridge

Oscillator.


THEORY:

Because of its simplicity and stability one of the most commonly used

low frequency oscillator is the Wein Bridge frequency oscillator. It is


1.

2.

3.

4.

5.

6.

Transistor

Resistors

Capacitor

CRO

Signal

Generator

Power Su l

BC107

(0-20)MHz

(0-1)MHz

(0-30)V

1

1

1



connected between the amplifier input terminal and output terminal. The

bridge has the series RC network in one arm and a parallel network in

another arm. The remaining two arms contain two resistors R and Rf in each

arm.

The phase angle for certain oscillator is that total phase shift aroundthe circuit must be 0. The condition occurs only when the Wein bridge is

balanced (i.e.) at resonance.

The frequency of the balanced Wein Bridge circuit is given by

f = 1 / (2πRC)

Assume that the resistors are equal in value and capacitors are equal

in the near time by the Wein Bridge. In this frequency, the gain required forsustained oscillations is given by

AV = 1/β

PROCEDURE:

1. Connection is given as the circuit diagram.

2. The DC supply is given and the variable resistor is adjusted to the

decided value.


noted down.



5. The waveform is noted in graph sheet.

6. The connections are then removed.

DESIGN FORMULA:

1. VE = VCC /10

2. VCE = VCC /2



3. VB=VBE + VE

4. RE=VE/IE

5. RC= (VCC-VCE-VE)/IC

6. RB= (S-1) RE

7. R2= (R1.RB)/ (R1-RB)

8. R1= (VCC-RB)/VB

9. R7=R6=R

10.C1=C2=C

11.A=1+ (R7/R8)

12.R = R3 || R4 || hie2

13.AV2= (-hfe2*R02)/hie

14.AV1= (-hfe*R01)/Ri

15.R01=RC1||hie

16.R12=R1||R2|| (hie+(1+hfe)RE)

DESIGN:



MODEL GRAPH:

TABULAR COLUMN:



RESULT:

Thus the Wein bridge oscillator was designed and constructed and the graph

was noted down.

1. Theoretical Frequency:

2. Practical Frequency:

VIVA QUESTIONS:

1. What is the condition for oscillation for Wein Bridge oscillator?

2. Give the low frequency oscillator?

3. Give the radio frequency oscillator?

7. CLIPPING CIRCUITS



AIM:

To design a Clipping circuit for the given specifications and hence to

plot its O/P


THEORY:

Clippers have the ability to clip off a portion of the input signal without

distorting the remaining part of the alternating waveform. The half wave

rectifier is an example of the simplest form of diode clipper – one resistor

and diode. Depending upon the orientation of the diode, the positive or

negative region of the input signal is clipped off.

Clippers are of two :

1. Series

2. Parallel

Series configuration is defined as one where diode is in series with the load,

while in parallel the diode is connected in parallel to the load.

PROCEDURE:

1. Connections are made as shown in the circuit diagram.

2. A sine wave Input Vi whose amplitude is greater than the clipping level is

applied.

3. Output waveform Vo is observed on the CRO.


1.

2.

3.

4.

5.

6.

Diode

Resistors

Capacitor

CRO

SignalGenerator

IN4007

(0-20)MHz

(0-1)MHz

(0-30)V

1

1

1



4. Clipped voltage is measured and verified with the designed values.

DESIGN:

SERIES CLIPPERS:

a) To pass –ve peak above VR level:



b) To pass –ve peak above some level (say -3V):



c) To pass +ve peak above VR Level:



d) To pass +ve peak above some level (say +3v):



CLAMPING CIRCUITS

AIM:

To design a Clamping circuit for the given specifications and hence to

plot its output.



1.

2.

3.

4.

5.

6.

Diode

Resistors

Capacitor

CRO

Signal

Generator

IN4007

(0-20)MHz

(0-1)MHz

(0-30)V

1

1

1



THEORY:

The clamping network is on that will clamp a signal to different dc

level. The circuit has a diode, resistor and a capacitive element, but it can

also employ an independent dc supply to introduce an addition shift. The

magnitude of R and C must be chosen that the time constant ζ = RC is large

enough that the voltage across the capacitor does not discharge significantly

during the interval diode is not conducting.

PROCEDURE:

1. Connections are made as shown in the circuit diagram.

2. A square wave input Vi is applied

3. Output waveform Vo is observed on the CRO. Keeping the AC/DC switch of

the CRO in DC Position.4. Clamped voltage is measured and verified with the designed values


http://slidepdf.com/reader/full/electronic-circuits-laboratory-experiments 45/74RESULT:



Aim:

To design and construct and test the performance characteristics of

UJT relaxation oscillator and to test the output waveform.


Design Formula:

1. Fo=1/(R T*C T*ln(1/(1-ƞ)) Hz2. VP= ƞVBB+VD

3. Rmax=(VBB-VD)/ID4. Rmin=(VBB-VBE(set))/ID5. R2=1000/ ƞVBB

6. R1=R2/2

Theory:

UJT is the Uni Junction Transistor. It is a three terminal device. Theyare: a) emitter b) base1 c) base2. The equivalent circuit is shown with the

circuit diagram. So there are two resistors. One is a variable resistor and

other is a fixed resistor. The ratio of internal resistances is referred as

intrinsic standoff ratio (η).It is defined as the ratio of the variable resistance

to the total resistance.

Due to the existing pn junction, there will be a voltage drop. If we

apply a voltage to the emitter, the device will not turn on until the input

voltage is less than the drop across the diode plus the drop at the variable

resistance R1.When the device is turned on holes moves from emitter to


1.

2.

3.

4.

5.

UJT

Resistors

Capacitor

CRO

Signal

Generator

2N2646 1

1

1



base resulting in a current flow. Due to this sudden increase in charge

concentration in base1 region conductivity increases.

This causes a drop at base1.This region in the graph is known as

negative resistance region. If we further increase the emitter voltage the

device undergoes saturation. So a UJT has 3 operating regions:

1. Cut off region

2. Negative resistance region

3. Saturation region

In a relaxation circuit there is an RC timing circuit. When the supply is

turned on, the capacitor starts charging. When the voltage across the

capacitor reaches the pinch off voltage, the UJT turns on. After discharging of

capacitor ,again it starts charging, and this process continues till powersupply is turned off

UJT Relaxation Oscillator circuit, mainly used for triggering purposes is

shown above. This circuit is ideally suited for triggering an SCR – since UJT is

capable of generating sharp, high powered pulses of short duration whose

peak and average power don’t exceed the power capabilities of the SCR gate

for which they are intended. When power is applied to the given circuit,

capacitor C starts charging exponentially through R to the applied voltage

VCC. The voltage across C is the voltage-Ve applied to the emitter of UJT.

When C is charged to Vp, then UJT turns ON. This greatly reduces theeffective resistance between emitter and base1 of UJT. A sharp pulse of

current flows from base1 to emitter, discharging C through Rb1. When the

capacitor voltage drops below Vp, UJT is brought back to the previous state

and the capacitor again begins to charge towards Vbb. This produces a saw-

tooth wave.

Procedure:

1. Connections are given as per the circuit diagram2. The power supply is switched ON3. The output waveform at the emitter of UJT is observed4. The spikes at Base1 and Base2 are observed5. The observed waveform are plotted in the graph



CIRCUIT DIAGRAM:

MODEL GRAPH:



Result:

Thus the performance of UJT relaxation oscillator is designed and

constructed and the output waveform is obtained.

Time (ms)Capacitor Voltage

At VB1=>

At VB2=>

Amplitude (V) Frequency (Hz)



9. BISTABLE MULTIVIBRATOR

Aim:

To design and construct a bistable multivibrator circuit using

transistors.

Devices and Equipments Required:

Design Formula:

1. VB1=VBB*(R1/(R1+R2))+VCE*(R2/(RI+R2)) <<0.72. I3=(VC2-VBB)/(R1+R2)3. I1=(VC1-VBE)/(RC+R1)4. I2=(VBE-VBB)/R2

5. R1<hfe*RC

6. IC2=IC-I37. IB2=I1-I28. IB2>IB2(min)9. IC=(VCC-VC2)/RC

10.RC=(VCC-VC2)/IC

Theory:

A multivibrator is an electronic circuit used to implement a variety of

simple two-state systems such as oscillators, timers and flip-flops. It is

characterized by two amplifying devices cross-coupled by resistors and

capacitors.

Particulars Range1.

2.

3.

4.

5.

6.

Transistors

PN Diode

Resistors

Capacitors

CRO

Signal Generator

BC 107

iN4007

2

2

1

1

Sl.N

oSpecification Quantity



A Bistable, in which the circuit will remain in either state indefinitely.

The circuit can be flipped from one state to the other by an external event or

trigger. Such a circuit is important as the fundamental building block of a

register or memory device. This circuit is also known as a latch or a flip-flop.

As the name implies, the bistable multivibrator has two stable states. If a trigger of the correct polarity and amplitude is applied to the circuit, it will

change states and remain there until triggered again. The trigger need not

have a fixed prf; in fact, triggers from different sources, occurring at different

times, can be used to switch this circuit.

The bistable multivibrator circuit and the associated waveforms are

shown in figure 3-17, views (A) and (B), respectively. In this circuit, R1 and

R7 are the collector load resistors. Voltage dividers R1, R2, and R5 provideforward bias for Q2; R7, R6, and R3 provide forward bias for Q1. These

resistors also couple the collector signal from one transistor to the base of

the other. Observe that this is direct coupling of feedback. This type of

coupling is required because the circuit depends on input triggers for

operation, not on RC time constants inside the circuit. Both transistors use

common emitter resistor R4 which provides emitter coupling. C1 and C2

couple the input triggers to the transistor bases.

The circuit is symmetrical; that is, each transistor amplifier has the

same component values. When power is first applied, the voltage divider

networks place a negative voltage at the bases of both the transistors. Both

transistors have forward bias and both conduct.

Procedure:

1. Connections are given as per the circuit diagram.

2. The amplitude and the time period are observed from each vibration3. The values are compared with the theoretical values of frequency andtime period.

4. The graph is drawn with output voltage Vo on the Y-axis and the timealong X-axis.



CIRCUIT DIAGRAM:

MODEL GRAPH:



RESULT:

Thus the bistable multivibrator was designed and its performance was

tested.



10. MONOSTABLE AND ASTABLE MULTIVIBRATOR

Aim:

To design and to construct a Monostable and Astable multivibrator andto obtain its output.


Design Formula:

1. RC= (VCC-VCE (sat))/IC

1.

2

3.

4.

5.

6.

Transistors

PN Diode

Resistors

Capacitors

CRO

Signal Generator

BC107

1N4007

2

1

1

1




2. IB2>IB2(min)

3. IB2(min) =IC2/hfe

4. R3=(VCC-VBE(sat))/IB2

5. RC=RC1=RC2

6. VBB*R1=VCE(sat)*R2

7. T=0.69RC

8. RC=(VCC-VCE(sat))/IC

9. R1=R2=hfe* RC

10. T=1.38RC

Theory:

Monostable Multivibrator:

Monostable multivibrators are circuits with one stable state. Theyremain in the stable state until triggered, when they then 'flip' over to the

other state. They remain in the unstable state for a time decided by the

circuit constants and then, of their own accord, 'flop' back to the original

stable state. Flip-flops find many applications in radar. They may be used to

generate rectangular pulses 'locked' to precise time intervals, to reshape

pulse trains which have deterior-ated in shape, to stretch narrow pulses into

wider ones or to generate a time delay.

When triggered by an input pulse, a monostable multivibrator will

switch to its unstable position for a period of time, and then return to its

stable state. The time period monostable multivibrator remains in unstable

state is given by t = ln(2)R2C1. If repeated application of the input pulse

maintains the circuit in the unstable state, it is called a retriggerable

monostable. If further trigger pulses do not affect the period, the circuit is a

non-retriggerable multivibrator

The flip-flop produces a rectangular wave whose leading edge is

coincident in time with the trigger pulse and whose trailing edge may be

varied with time. The output from the flip-flop may be differentiated and then

negatively limited to give a series of pulses which have a controlled variable

time delay in relation to the original trigger pulses.

Astable Multivibrator:



An astable multivibrator is also known as a FREE-RUNNING

MULTIVIBRATOR. It is called free-running because it alternates between two

different output voltage levels during the time it is on. The output remains at

each voltage level for a definite period of time. If you looked at this output

on an oscilloscope, you would see continuous square or rectangular

waveforms. The astable multivibrator has two outputs, but NO inputs.

The astable multivibrator is said to oscillate. To understand why the

astable multivibrator oscillates, assume that transistor Q1 saturates and

transistor Q2 cuts off when the circuit is energized. We assume Q1 saturates

and Q2 is in cutoff because the circuit is symmetrical; that is, R1 = R4, R2 =

R3, C1 = C2, and Q1 = Q2. It is impossible to tell which transistor will

actually conduct when the circuit is energized. For this reason, either of the

transistors may be assumed to conduct for circuit analysis purposes.

Essentially, all the current in the circuit flows through Q1; Q1 offers

almost no resistance to current flow. Notice that capacitor C1 is charging.

Since Q1 offers almost no resistance in its saturated state, the rate of charge

of C1 depends only on the time constant of R2 and C1 Notice that the right-

hand side of capacitor C1 is connected to the base of transistor Q2, which is

now at cutoff.

The right-hand side of capacitor C1 is becoming increasingly negative.

If the base of Q2 becomes sufficiently negative, Q2 will conduct. After a

certain period of time, the base of Q2 will become sufficiently negative to

cause Q2 to change states from cutoff to conduction. The time necessary for

Q2 to become saturated is determined by the time constant R2C1.

The negative voltage accumulated on the right side on capacitor C1

has caused Q2 to conduct. Now the following sequence of events takes place

almost instantaneously. Q2 starts conducting and quickly saturates, and the

voltage at output 2 changes from approximately -VCC to approximately 0

volts. This change in voltage is coupled through C2 to the base of Q1, forcing

Q1 to cutoff. Now Q1 is in cutoff and Q2 is in saturation.

Procedure:

1. Connections are given as per the circuit diagram.



2. The amplitude and time period are observed from each vibrations.

3. The values are compared with the theoretical values of frequency and

the time period.

4. The graph is plotted with the output voltage VO and time along the X

axis.

CIRCUIT DIAGRAM:

MONOSTABLE MULTIVIBRATOR:

ASTABLE MULTIVIBRATOR:



MODEL GRAPH:

TABULAR COLUMN:



RESULT :

Thus the monostable multivibrator and astable multivibrator was

designed and its output waveforms are obtained.

Amplitude (V) Time (ms)

Monostable

VB2

VC2

Astable

VB1

VB2

VC1

VC2



11.BOOTSTRAP SWEEP GENERATION

Aim:

To construct the Bootstrap Sweep Generator circuit and to test its

performance.


Design Formula:

1. IB=IC/β

2. RE=VE/IE3. VE=VCC/104. RC=(VCC-VCE-VERE)/IC5. RB=((1+ β)(1-S)RE)/(1+ β -S)6. VCE=VCC/27. Vth=VBE+IBRB+IERE

8. R1=(VCC/Vth)*RB

9. R2=(R1*Vth)/(VCC-Vth)

Theory:

Let us consider a practical bootstrap sweep circuit using transistor. The voltage V is equal to V!+Vo Where Vo= initial voltage across emitter

resistance RE when S is closed. The major problem with the figure is

grounding (i.e.) the voltage supply ‘V’ is not grounded. This problem has

been overcome in figure. The voltage supply is replaced be a capacitor C1

which is changed through a resistor R1. The value of capacitor C1 is large

enough so that the voltage across it shall not change. Appreciably during the

sweep time if the voltage across C1 is constant and if the emitter follower

had unity voltage amplification then point P2 would exactly follow pint P1

would be invariant and the current i.e. P1 would e invariant and the current

ApparatusSpecificatio

nParticularsSl.N

oRange Quantity

1.

2.

3.

4.

5.

6.

Transistors

PN Diode

Resistors

Capacitors

Signal

Generator

CRO

BC107IN4007

2

1

1

1



i.e. P1 would be through R would be constant. if the input impedance so if

emitter follower is infinity, then the constant current IR passes through the

capacitor C

PROCEDURE:

1. Connections are given as per the circuit diagram.2. Power Supply is switched on.3. Input is applied to the base of the transistors.4. Output is observed at the emitter of transistor Q2.

5. Corresponding Graphs are drawn.

TABULAR COLUMN:

CIRCUIT DIAGRAM:

Frequen

cy

Input Voltage (V) Output Voltage (V)

Amplitude Time (ms) Amplitude Time (ms)



MODEL GRAPH:

RESULT : Thus the bootstrap sweep circuit was designed and its graph was

drawn.



12. SCHMITT TRIGGER

Aim:

To design and construct Schmitt Trigger circuit using transistor and to

test its performance characteristics


Design Formula:

1. VB2=U TP

2. VE=VB2-VBE

3. IE=IC

4. RE=VE/IE

5. IC*RC2=VCC-VE-VCE

6. RC2=(VCC-VE-VCE)/IC

7. I2=IE/10

8. R2=VB2/I2

9. R1=(VCC-VB2)/I2+IB2

10. RC1=RC2

ApparatusSpecificatio

nParticulars

Sl.No Range Quantity

1.

2.

3.

4.

5.

6.

Transistors

PN Diode

Resistors

Capacitors

Signal

Generator

CRO

BC107

IN4007

2

1

1

1



11. VCE=VCC/2

12. R1=((VCC-VB2)/(I2+IB2))-R2

Theory:

Sometimes an input signal to a digital circuit doesn't directly fit thedescription of a digital signal. For various reasons it may have slow rise

and/or fall times, or may have acquired some noise that could be sensed by

further circuitry. It may even be an analog signal whose frequency we want

to measure. All of these conditions, and many others, require a specialized

circuit that will "clean up" a signal and force it to true digital shape.

The required circuit is called a Schmitt Trigger. It has two possible

states just like other multivibrators. However, the trigger for this circuit to

change states is the input voltage level, rather than a digital pulse. That is,

the output state depends on the input level, and will change only as the

input crosses a pre-defined threshold.

Unlike the other multivibrators you have built and demonstrated, the

Schmitt Trigger makes its feedback connection through the emitters of the

transistors as shown in the schematic diagram to the right. This makes for

some useful possibilities, as we will see during our discussion of the

operating theory of this circuit.

To understand how this circuit works, assume that the input starts at

ground, or 0 volts. Transistor Q1 is necessarily turned off, and has no effecton this circuit. Therefore, RC1, R1, and R2 form a voltage divider across the 5

volt power supply to set the base voltage of Q2 to a value of (5 × R2)/(RC1 +

R1 + R2). If we assume that the two transistors are essentially identical, then

as long as the input voltage remains significantly less than the base voltage

of Q2, Q1 will remain off and the circuit operation will not change.

While Q1 is off, Q2 is on. Its emitter and collector current are

essentially the same, and are set by the value of RE and the emitter voltage,

which will be less than the Q2 base voltage by VBE. If Q2 is in saturation

under these circumstances, the output voltage will be within a fraction of thethreshold voltage set by RC1, R1, and R2. It is important to note that the

output voltage of this circuit cannot drop to zero volts, and generally not to a

valid logic 0. We can deal with that, but we must recognize this fact.

Now, suppose that the input voltage rises, and continues to rise until it

approaches the threshold voltage on Q2's base. At this point, Q1 begins to

conduct. Since it now carries some collector current, the current through RC1

increases and the voltage at the collector of Q1 decreases. But this also

affects our voltage divider, reducing the base voltage on Q2. But since Q1 is



now conducting it carries some of the current flowing through RE, and the

voltage across RE doesn't change as rapidly. Therefore, Q2 turns off and the

output voltage rises to +5 volts. The circuit has just changed states.

If the input voltage rises further, it will simply keep Q1 turned on and

Q2 turned off. However, if the input voltage starts to fall back towards zero,

there must clearly be a point at which this circuit will reset itself the falling

Threshold will be the voltage at which Q1's base becomes more negative

than Q2's base, so that Q2 will begin conducting again. However, it isn't the

same as the rising threshold voltage, since Q1 is currently affecting the

behavior of the voltage divider.

As VIN approaches this value, Q2 begin to conduct, taking emitter

current away from Q1. This reduces the current through RC1 which raises

Q2's base voltage further, increasing Q2's forward bias and decreasing Q1's

forward bias. This in turn will turn off Q1, and the circuit will switch back to

its original state.

Three factors must be recognized in the Schmitt Trigger. First, the

circuit will change states as VIN approaches VB2, not when the two voltages

are equal. Therefore VB2 is very close to the threshold voltage, but is not

precisely equal to it. For example, for the component values shown above,

VB2 will be 2.54 volts when Q1 is held off, and 2.06 volts as VIN is falling

towards this value.

Second, since the common emitter connection is part of the feedback

system in this circuit, RE must be large enough to provide the requisite

amount of feedback, without becoming so large as to starve the circuit of needed current. If RE is out of range, the circuit will not operate properly,

and may not operate as anything more than a high-gain amplifier over a

narrow input voltage range, instead of switching states.

The third factor is the fact that the output voltage cannot switch over

logic levels, because the transistor emitters are not grounded. If a logic-level

output is required, which is usually the case, we can use a circuit such as the

one shown here to correct this problem. This circuit is basically two RTL

inverters, except that one uses a PNP transistor. This works because when

Q2 above is turned off, it will hold a PNP inverter off, but when it is on, its

output will turn the PNP transistor on. The NPN transistor here is a second

inverter to re-invert the signal and to restore it to active pull-down in

common with all of our other logic circuits.

Applications

Schmitt triggers are typically used in open loop configurations for noise

immunity and closed loop positive feedback configurations to implement

multivibrators.



Noise immunity

One application of a Schmitt trigger is to increase the noise immunity

in a circuit with only a single input threshold. With only one input threshold,

a noisy input signal near that threshold could cause the output to switch

rapidly back and forth from noise alone. A noisy Schmitt Trigger input signal

near one threshold can cause only one switch in output value, after which it

would have to move beyond the other threshold in order to cause another

switch.

PROCEDURE:

1. The connections are given as per the circuit diagram.

2. The Power supply is switched ON.

3. Sine wave is given as input signal.

4. The square wave is generated as output and the readings are tabulated.

5. The graph is plotted by taking voltage along Y-axis and the time period

along X axis.

CIRCUIT DIAGRAM:



MODEL GRAPH:



RESULT:

Thus, the Schmitt trigger circuit using transistor is designed and

constructed and its performance.



ELECTRONIC CIRCUITS-II LAB

VIVA QUESTIONS

1. What is a transistor?

2. Why transistor is called as current controlled device?3. Define the forward active mode?

4. Explain saturation mode?

5. Explain cutoff mode?

6. Explain the current gain of transistor?

7. Name the three regions in the output characteristics of the

transistor?

8. Give the applications of the transistor?9. What is FET?

10. Why FET is called voltage controlled device?

11. What are the two types of FET?

12. Why FET is called unipolar device?

13. What is pinch off voltage?

14. Explain the drain Characteristics?

15. Explain transfer characteristics?

16. What is the difference between JFET and BJT?

17. What is static resistance?

18. What is dynamic resistance?

19. What is meant by forward bias and reverse bias?

20. Why silicon is preferred compared to germanium?

21. What is meant by semiconductor?

22. What are the two types of semiconductor?

23. What is meant by doping?

24. Is there any phase reversal in CE amplifier?

25. What are the types of coupling?

26. What are the two types of feedback?

27. What is meant by positive feedback?

28. What is meant by negative feedback?

29. What is meant by amplifier?

30. What is meant by oscillator?



31. What are the advantages of positive feedback?

32. What are the advantages of negative feedback?

33. State Barkhausen criterion?

34. Compare amplifier and oscillator?

35. Give an example of LC oscillator?

36. Give an example of RC oscillator?

37. What are the disadvantages of negative feedback?

38. What are the four types of feedback amplifier?

39. Is there any phase reversal in CE amplifier?

40. What are the types of coupling?

41. What type of feedback is employed in amplifiers?

42. Tell an oscillator which uses both positive and negative

feedback?43. What is the phase shift produced by three identical RC networks?

44. What is meant by feedback?

45. Define large signal amplifier?

46. Why the low hfe is used in large signal amplifier?

47. What is the condition for oscillation for Hartley oscillator?

48. What is the condition for oscillation for Colpitts oscillator?

49. What is the condition for oscillation for Weinbridge oscillator?50. Give the low frequency oscillator?

51. Give the radio frequency oscillator?

52. What are the disadvantages of Hartley oscillator?

53. What are the two types of oscillator?

54. What is meant by valley current?

55. What is meant by tripled value?

56. What is meant by peak current?

57. What is meant by cutoff region?

58. What is meant by negative resistance region?

59. What is meant by INTRINSIC STAND OPERATION?

60. What is meant by saturation region?

61. State some applications of UJT?

62. Define Miller effect?

63. Define multivibrator?



64. Compare multivibrator and Schmitt trigger?

65. Write the frequency of oscillation for Hartley oscillator?

66. Write the frequency of oscillation for Colpitts oscillator?

67. Write the frequency of oscillation for RC phase shift oscillator

using BJT and FET?

68. Define astable multivibrator?

69. Define monostable multivibrator?

70. Define bistable multivibrator?

71. What is meant by pulse circuits?

72. Define RC low pass circuits?

73. Define RC high pass circuits?

74. What are the types of wave shaping circuits?

75. Give the examples of linear wave shaping circuits?76. Define tuned amplifier?

77. What is the use of resonance circuit in the tuned amplifier?

78. Define quality factor?

79. Draw the equivalent circuit for transconductance amplifier?

80. How do you generate spike signal?

81. Draw the low frequency model for BJT?

82. Draw the high frequency model for BJT?

83. Define clipper?

84. Define clamper?

85. What is the application of wave shaping circuits?

86. What is the advantage of stagger tuned amplifier?

87. What is the disadvantage of double tuned amplifier?

88. What is meant by wideband amplifier?

89. What is meant by bias?

90. What is maximum phase shift produced by single RC network?

91. Define crystal oscillator?

92. What is the main advantage of crystal oscillator?

93. Give the various feedback amplifiers?

94. What is meant by bias clipper?

95. Define positive clamper?

96. Define time base generator?



97. What is the application of time base generator?

98. What is the disadvantage of Class A amplifier?

99. What is the maximum efficiency of Class C power amplifier?

electronic circuits laboratory experiments

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