elec 2200-002 digital logic circuits fall 2014 sequential ...agrawvd/course/e2200_fall14/... ·...
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ELEC 2200-002Digital Logic Circuits
Fall 2014Sequential Circuits (Chapter 6)
Finite State Machines (Ch. 7-10)Vishwani D. Agrawal
James J. Danaher ProfessorDepartment of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849http://www.eng.auburn.edu/~vagrawal
[email protected] 2014, Nov 10 . . . ELEC2200-002 Lecture 7 1
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Combinational vs. Sequential
Combinational circuit:Output is a function of inputNo memoryExample: parallel adder
Sequential circuit:Output is a function of input and something else stored in the circuitInternal memoryExample: serial adder
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 2
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Parallel and Serial Adders
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 3
Four-bitAdder
0011
0100
0111
One-bitAdder
0 0 1 1
0 1 0 00 1 1 1
One-bitmemory
timetime
S
C
1. Memory initialized to 0 (initial carry = 0)
2. Time synchronization of Inputs, output, and memory (clock)
(LSB)
(LSB)
(LSB)
(LSB
)
(LSB
)
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Another Example of Sequential System
Four-year degree program:Student can be in four states (Fr, So, Jr, Sr)One-bit yearly input, 1 (completed) or 0 (in progress)Output = 1 (degree completed), 0 (in progress)
State diagram:
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 4
Fr So Jr Sr
0/0 0/0 0/0 0/0
1/0 1/0 1/0
1/1Initial state
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State Table or Excitation TableInput Present State Next State Output
0 Fr Fr 0
0 So So 0
0 Jr Jr 0
0 Sr Sr 0
1 Fr So 0
1 So Jr 0
1 Jr Sr 0
1 Sr Sr 1
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 5
Initial State: Fr
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State Table (Alternative Form)
Fr/0 So/0
So/0 Jr/0
Jr/0 Sr/0
Sr/0 Sr/1
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 6
Fr
So
Jr
Sr
Inputs0 1
Pres
ent s
tate
Next state/output
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When Is Circuit Not Combinational?When the present input does not completely control output.For a logic circuit without feedback, input uniquely determines the output.Examples of non-combinational (sequential) circuits:
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 7
Toggling 0-1
Odd inversions Even inversions
0 1or
1 0
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SR Latch: Basic Sequential Circuit
Feedback loop with even number of inversions (no oscillation?).Output(s): two sets of logic values from the loop.Input functions:
To control loop logic valuesTo set the loop in “input control” or “store” state
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 8
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Adding Inputs to Feedback Loop
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 9
Q
Q
S
R
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NOR Set-Reset (SR) Latch
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 10
Q
Q
S
R
Q
Q
S
R
Q
Q
S
R
Also drawn as Symbol used in Logic schematics
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States of LatchState S R Q Q
Set 1 0 1 0
Reset 0 1 0 1
Store 0 0 Prev. Q Prev. Q
Illegal 1 1 0 0
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 11
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The “Set” State
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 12
Q = 1
Q = 0
S = 1
R = 0
Behavior is combinational.
Loop is broken
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The “Reset” State
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 13
Q = 0
Q = 1
S = 0
R = 1
Behavior is combinational.
Loop is broken
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The “Store” State
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 14
Q = 1
Q = 0
S = 0
R = 0
Loop is activated; behavior is sequential.
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The “Illegal” State
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 15
Q = 0
Q = 0
S = 1
R = 1
Loop is broken in two places and inconsistent values inserted.
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“Illegal” State Cannot Be Stored
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 16
Q = 0 → 1 → 0 → 1 → . . .
Q = 0 → 1 → 0 → 1 → . . .
S = 1 → 0
R = 1 → 0
Output oscillates with a period of loop delay. For unequal gatedelays, faster gate will settle to 1 and slower gate to 0. This isknown as RACE CONDITION.
Assume two gates have equal delays.
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Excitation Table of SR LatchExcitation inputs Present
state Next state FunctionalName of
StateS R Q Q*
0 0 0 0Store
0 0 1 1
0 1 0 0Reset
0 1 1 0
1 0 0 1Set
1 0 1 1
1 1 0 Illegal Race condition1 1 1 Illegal
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 17
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Characteristic Equation for SR Latch
Next-state function:Treat illegal states as don’t careMinimize using Karnaugh map
Characteristic equation, Q* = S +RQ
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 18
Φ 1
1 Φ 1Q
S
R
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State Diagram of SR Latch
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 19
Q = 0 Q = 1
SR = 10
SR = 01
SR = 0X SR = X0
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Clocked SR Latch
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 20
S
CK
R
Q
Q
SR-latch
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Clocked Delay Latch or D-Latch
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 21
D
CK
Q
Q
SR-latch
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Setup and Hold Times of LatchSignals are synchronized with respect to clock (CK).Operation is level-sensitive:
CK = 1 allows data (D) to pass throughCK = 0 holds the value of Q, ignores data (D)
Setup time is the interval before the clock transition during which data (D) should be stable (not change). This will avoid any possible race condition.Hold time is the interval after the clock transition during which data should not change. This will avoid data from latching incorrectly.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 22
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Latch Inputs
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 23
1
0 time
D
1
0 time
CK
tr
ts th
tp
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JK-Latch
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 24
J
K
Q
Q
SR-latch
Characteristic Equation, Q = JQ* + K Q*Where Q = present state, Q* = previous state
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T-Latch (Toggle Latch)
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 25
J
K
Q
Q
SR-latch
Characteristic Equation, Q = TQ* + T Q*Where Q = present state, Q* = previous state
T
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Master-Slave D-Flip-Flop
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 26
D
CK
Q
Q
Master latch Slave latch
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Master-Slave D-Flip-Flop
Uses two clocked D-latches.Transfers data (D) with one clock period delay.Operation is edge-triggered:
Negative edge-triggered, CK = 1→0, Q = D (previous slide)Positive edge-triggered, CK = 0→1, Q = D
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 27
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Negative-Edge Triggered D-Flip-Flop
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 28
Clock period, T
Master openSlave closed
Slave openMaster closedCK
D
Data can change Data can changeDatastable
Time
Setup time Hold timeTriggering clock edge
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D-Flip-Flop With CLEAR
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 29
D
CK
Q
Q
Master latch Slave latch
CLR
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D-Flip-Flop With PRESET
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 30
D
CK
Q
Q
Master latch Slave latch
PRESET
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Symbols for Latch and D-Flip-Flops
Fall 2014, Nov 10 . . . 31
CK
D
Q (LATCH)Level sensitive
Q (DFF)Pos. Edge Triggered
Q (DFF)Neg. Edge Triggered
DCK
Q
D
CK
Q
D
CK
Q
ELEC2200-002 Lecture 7
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Register (3-Bit Example)Stores parallel data
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 32
CLRD Q
CK
CLRD Q
CK
CLRD Q
CK
CLR
CK
Q0 Q1 Q2
Parallel output
Parallel inputD0 D1 D2
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Shift Register (3-Bit Example)Stores serial data (parallel output)Delays data (serial output)
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 33
CLRD Q
CK
CLRD Q
CK
CLRD Q
CK
CLR
DSerialinput
CK
Q0 Q1 Q2
Parallel output
Serialoutput
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Two Types of Digital Circuits1. Output depends uniquely on inputs:
Contains only logic gates, AND, OR, . . . No feedback interconnects
2. Output depends on inputs and memory: Contains logic gates, latches and flip-flops May have feedback interconnects Contents of flip-flops define internal state; N flip-
flops provide 2N states; finite memory means finite states, hence the name “finite state machine (FSM)”.
Clocked memory – synchronous FSM No clock – asynchronous FSM
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 34
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Textbook Organization
Chapter 6: Sequential devices – latches, flip-flops.Chapter 7: Modular sequential logic – registers, shift registers, counters.Chapter 8: Specification and analysis of FSM.Chapter 9: Synchronous (clocked) FSM design.Chapter 10: Asynchronous (pulse mode) FSM design.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 35
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Mealy and Moore FSMMealy machine: Output is a function of input and the state.Moore machine: Output is a function of the state alone.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 36
S0 S1
1/1
1/0
0/1 0/0
Mealy machine
S0/1 S1/0
1/0
1/1
0/1 0/0
Moore machine
G. H. Mealy, “A Method for Synthesizing Sequential Circuits,” BellSystems Tech. J., vol. 34, pp. 1045-1079, September 1955.E. F. Moore, “Gedanken-Experiments on Sequential Machines,” Annals ofMathematical Studies, no. 34, pp. 129-153 ,1956, Princeton Univ. Press, NJ.
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Example 8.17: Robot ControlA robot moves in straight line, encounters obstacle and turns right or left until path is clear; on successive obstacles right and left turn strategies are used.Define input: One bit
X = 0, no obstacleX = 1, an obstacle encountered
Define outputs: Two bits to represent three possible actions.Z1, Z2 = 00 no turnZ1, Z2 = 01 turn right by a predetermined angleZ1, Z2 = 10 turn left by a predetermined angleZ1, Z2 = 11 output not used
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 37
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Example 8.17: Robot Control (Continued . . . 2)
Because turning strategy depends on the action for the previous obstacle, the robot must remember the past.Therefore, we define internal memory states:
State A = no obstacle detected, last turn was leftState B = obstacle detected, turning rightState C = no obstacle detected, last turn was rightState D = obstacle detected, turning left
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 38
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Realization of FSMThe general hardware architecture of an FSM, known as Huffman model, consists of:
Flip-flops for storing the state.Combinational logic to generate outputs and next state from inputs and present state.Clock to synchronize state changes.Initialization hardware to set the machine in prespecified state.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 39
Combinational logic
Flip-flops
OutputsInputs
Presentstate
Nextstate
ClockClear
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Example 8.17: Robot Control (Continued . . . 3)
Construct state diagram.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 40
A
D C
B
A: no obstacle, last turn was leftB: obstacle, turn rightC: no obstacle, last turn was rightD: obstacle, turn left
Input: X = 0, no obstacleX = 1, obstacle
Outputs:Z1, Z2 = 00, no turnZ1, Z2 = 01, right turnZ1, Z2 = 10, left turn
0/001/01
0/00 0/00
0/00
1/01
1/101/10
X Z1 Z2
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Example 8.17: Robot Control (Continued . . . 4)
Construct state table.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 41
A
D C
B
0/001/01
0/00 0/00
0/00
1/01
1/101/10
X Z1 Z2
A/00
C/00
C/00
A/00
B/01
B/01
D/10
D/10
XPresent 0 1state
A
B
C
D
Nextstate
OutputsZ1, Z2
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XY1 Y2 0 1
00
01
11
10
Example 8.17: Robot Control (Continued . . . 5)
State assignment: Each state is assigned a unique binary code. Need log24 = 2 binary state variables to represent 4 states.Let memory variables be Y1,Y2:
A: {Y1,Y2} = 00; B: {Y1,Y2} = 01; C: {Y1,Y2} = 11, D: {Y1,Y2} = 10
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 42
A/00
C/00
C/00
A/00
B/01
B/01
D/10
D/10
XPresent 0 1state
A
B
C
D
00/00
11/00
11/00
00/00
01/01
01/01
10/10
10/10
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Realization of FSMPrimary input: XPrimary outputs: Z1, Z2Present state variables: Y1, Y2Next state variables: Y1*, Y2*
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 43
Combinational logic
Flip-flop
Z1
Z2X
Y1
Y2 Y1*
Y2*
Clock
Clear Flip-flop
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XY1 Y2 0 1
00
01
11
10
Example 8.17: Robot Control (Continued . . . 6)
Construct truth tables for outputs, Z1 and Z2, and excitation variables, Y1 and Y2.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 44
00/00
11/00
11/00
00/00
01/01
01/01
10/10
10/10
NextState, Y1*, Y2*
OutputsZ1, Z2
Input Present state Outputs Next state
X Y1 Y2 Z1 Z2 Y1* Y2*0 0 0 0 0 0 00 0 1 0 0 1 10 1 0 0 0 0 00 1 1 0 0 1 11 0 0 0 1 0 11 0 1 0 1 0 11 1 0 1 0 1 01 1 1 1 0 1 0
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Example 8.17: Robot Control (Continued . . . 7)
Synthesize logic functions, Z1, Z2, Y1*, Y2*.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 45
Input Present state Outputs Next state
X Y1 Y2 Z1 Z2 Y1* Y2*0 0 0 0 0 0 00 0 1 0 0 1 10 1 0 0 0 0 00 1 1 0 0 1 11 0 0 0 1 0 11 0 1 0 1 0 11 1 0 1 0 1 01 1 1 1 0 1 0
Z1 = XY1Y2 + XY1 Y2 = XY1
Z2 = XY1Y2 + XY1 Y2 = XY1
Y1* = XY1 Y2 + . . .
Y2* = XY1 Y2 + . . .
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Example 8.17: Robot Control (Continued . . . 8)
Synthesize logic functions, Z1, Z2, Y1*, Y2*.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 46
1
1 1 1Y2
X
Y1
1
1 1 1Y2
Y1
1
1Y2
X
Y1
1
1Y2
X
Y1
X
Z1
Z2
Y1*
Y2*
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Example 8.17: Robot Control (Continued . . . 9)
Synthesize logic and connect memory elements (flip-flops).
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 47
Y2
Y1Y1
Y2
XZ1
Z2Y1*
Y2*
CK
CLEAR
Combinational logic
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Steps in FSM SynthesisExamine specified function to identify inputs, outputs and memory states.Draw a state diagram.Minimize states (see Section 9.1).Assign binary codes to states (Section 9.4).Derive truth tables for state variables and output functions.Minimize multi-output logic circuit.Connect flip-flops for state variables. Don’t forget to connect clock and clear signals.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 48
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Architecture of an FSMThe Huffman model, containing:
Flip-flops for storing the state.Combinational logic to generate outputs and next state from inputs and present state.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 49
Combinational logic
Flip-flops
OutputsInputs
Presentstate
Nextstate
ClockClear
D. A. Huffman, “The Synthesis of Sequential Switching Circuits,J. Franklin Inst., vol. 257, pp. 275-303, March-April 1954.
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State MinimizationAn FSM contains flip-flops and combinational logic:
Number of flip-flops, Nff = log2 Ns , Ns = #statesSize of combinational logic depends on state assignment.
Examples:
1. Ns = 16, Nff = log2 16 = 4
2. Ns = 17, Nff = log2 17 = 4.0875 = 5
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 50
Ceiling operator
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Equivalent StatesTwo states of an FSM are equivalent (or indistinguishable) if for each input they produce the same output and their next states are identical.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 51
Si
Sj
Sm
Sn
1/0
1/0
0/0
0/0
Si,j
Sm
Sn
1/0
0/0
Si and Sj are equivalent andmerged into a single state.
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Minimizing StatesExample: States A . . . I, Inputs I1, I2, Output, Z
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 52
Present state
Next state, output (Z)
InputI1 I2
A D / 0 C / 1B E / 1 A / 1C H / 1 D / 1D D / 0 C / 1E B / 0 G / 1F H / 1 D /1G A / 0 F / 1H C / 0 A / 1I G / 1 H / 1
A and D are equivalent
A and E produce same outputQ: Can they be equivalent?A: Yes, if B and D were equivalent
and C and G were equivalent.
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Implication Table Method
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 53
A B C D E F G H
B
C
D
E
F
G
H
I
√BDCG
ADCF
√
CDAC
EHAD
EHAD
EGAH
Present state
Next state, output (Z)Input
I1 I2A D / 0 C / 1B E / 1 A / 1C H / 1 D / 1D D / 0 C / 1E B / 0 G / 1F H / 1 D / 1G A / 0 F /1H C / 0 A / 1I G / 1 H / 1
ADCFCDAC
BCAG
BDCG
ACAF
GHDH
GHDH
ABFG
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Implication Table Method (Cont.)
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 54
A B C D E F G H
B
C
D
E
F
G
H
I
√BDCG
ADCF
√
CDAC
EHAD
EHAD
EGAH
ADCFCDAC
BCAG
BDCG
ACAF
GHDH
GHDH
Equivalent states:
S1: A, D, G
S2: B, C, F
S3: E, H
S4: IABFG
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Minimized State Table
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 55
Present state
Next state, output (Z)Input
I1 I2A D / 0 C / 1B E / 1 A / 1C H / 1 D / 1D D / 0 C / 1E B / 0 G / 1F H / 1 D / 1G A / 0 F / 1H C / 0 A / 1I G / 1 H / 1
Present stateNext state, output (Z)
InputI1 I2
S1 = (A, D, G) S1 / 0 S2 / 1S2 = (B, C, F) S3 / 1 S1 / 1
S3 = (E, H) S2 / 0 S1 / 1S4 = I S1 / 1 S3 / 1
Original Minimized
Number of flip-flops is reducedfrom 4 to 2.
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State AssignmentState assignment means assigning distinct binary patterns (codes) to states.N flip-flops generate 2N codes.While we are free to assign these codes to represent states in any way, the assignment affects the optimality of the combinational logic.Rules based on heuristics are used to determine state assignment.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 56
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Criteria for State AssignmentOptimize:
Logic gates, orDelay, orPower consumption, orTestability, orAny combination of the above
Up to 4 or 5 flip-flops: can try all assignments and select the best.More flip-flops: Use an existing heuristic (one discussed next) or invent a new heuristic.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 57
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1 1 1
1 1 1
1 1 1
1 1
The Idea of AdjacencyInputs are A and BState variables are Y1 and Y2An output is F(A, B, Y1, Y2)A next state function is G(A, B, Y1, Y2)
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 58
A
B
Y1
Y2
Karnaugh map ofoutput function ornext state function
Larger clustersproduce smaller logic function.
Clustered mintermsdiffer in one variable.
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Size of an ImplementationNumber of product terms determines number of gates.Number of literals in a product term determines number of gate inputs, which is proportional to number of transistors.Hardware α (total number of literals)Examples of four minterm functions:
F1 = ABCD +ABCD +ABCD +ABCD has 16 literalsF2 = ABC +ACD has 6 literals
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 59
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Rule 1States that have the same next state for some fixed input should be assigned logically adjacent codes.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 60
Combinational logic
Flip-flops
OutputsFixedInputs
Presentstate
Nextstate
ClockClear
Si
Sj
Sk
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Rule 2States that are the next states of the same state under logically adjacent inputs, should be assigned logically adjacent codes.
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 61
Combinational logic
Flip-flops
OutputsAdjacentInputs
Fixedpresent
state
Nextstate
ClockClear
SkSm
Si
I1I2
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Example of State Assignment
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 62
Present state
Next state,output (Z)Input, X
0 1A C, 0 D, 0B C, 0 A, 0C B, 0 D, 0D A, 1 B, 1
D B
A
C
0/0
0/0
0/0
1/01/0
1/0
1/1
0/1
A adj B(Rule 1)
A adj C(Rule 1)
B adj D(Rule 2)
Figure 9.19 of textbook C adj D(Rule 2)
A B
C D
0 1
0
1
Verify that BC andAD are not adjacent.
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A = 00, B = 01, C = 10, D = 11
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 63
Present state
Y1, Y2
Next state, outputY1*Y2*, ZInput, X
0 1A = 00 10 / 0 11 / 0B = 01 10 / 0 00 / 0C = 10 01 / 0 11 / 0D = 11 00 / 1 01 / 1
Input Present state Output Next state
X Y1 Y2 Z Y1* Y2*0 0 0 0 1 00 0 1 0 1 00 1 0 0 0 10 1 1 1 0 01 0 0 0 1 11 0 1 0 0 01 1 0 0 1 11 1 1 1 1 0
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Logic Minimization for Optimum State Assignment
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 64
1 1 1
1 1Y2
X
Y1
1 1 1
Y2
Y1
1 1Y2
X
Y1 X
Z Y1*
Y2*
Result: 5 products, 10 literals.
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Circuit for Optimum State Assignment
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 65
Y2
Y1Y1
Y2
X
Z
Y2*
Y1*
CK
CLEAR
Combinational logic
32 transistors
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Using an Arbitrary State Assignment: A = 00, B = 01, C = 11, D = 10
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 66
Present state
Y1, Y2
Next state, outputY1*Y2*, ZInput, X
0 1A = 00 11 / 0 10 / 0B = 01 11 / 0 00 / 0C = 11 01 / 0 10 / 0D = 10 00 / 1 01 / 1
Input Present state Output Next state
X Y1 Y2 Z Y1* Y2*0 0 0 0 1 10 0 1 0 1 10 1 0 1 0 00 1 1 0 0 11 0 0 0 1 01 0 1 0 0 01 1 0 1 0 11 1 1 0 1 0
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Logic Minimization for Arbitrary State Assignment
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 67
Result: 6 products, 14 literals.
1 1
1 1Y2
X
1 1
Y2
XZ Y1*
1 1
1 1Y2
Y1
XY2*Y1 Y1
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Circuit for Arbitrary State Assignment
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 68
Y2
Y1Y1
Y2
X
Z
Y2*
Y1*
CK
CLEAR
Comb.logic
42 transistors
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Find Out More About FSMState minimization through partioning (Section 9.2.2).Incompletely specified sequential circuits (Section 9.3).Further rules for state assignment and use of implication graphs (Section 9.4).Asynchronous or fundamental-mode sequential circuits (Chapter 10).
Fall 2014, Nov 10 . . . ELEC2200-002 Lecture 7 69