1

EECS 427Lecture 20: Design and Synthesis

Readings: 8 1-8 4 Inserts E FReadings: 8.1 8.4, Inserts E, F

EECS 427 F09 Lecture 20 1

Reminders

• One more deadline– Finish your project by Dec. 14y j y– Schematic, layout, simulations, and final assembly (CAD9)– Final report and project presentation (HW5)

• Office hours this week– Mon 3 – 4 pm– Tue 5 – 6 pm– Sun 3 – 6 pm

• Remaining lectures• Remaining lectures– 11/30 Monday: Design and synthesis– 12/2 Wednesday: Design for test– 12/7 Monday: Zhengya’s research– 12/9 Wednesday: Clock and power distribution– 12/14 Monday: Project presentation

EECS 427 F09 Lecture 20 2

2

A Simple Processor

MEMORYMEMORY

CONTROL

INPUT OUTPUT

INP

UT

/OU

TP

UT

DATAPATHINPUT-OUTPUT

EECS 427 F09 Lecture 20 3

A System-on-a-Chip: Example

Courtesy: Philips

EECS 427 F09 Lecture 20 4

3

Impact of Implementation Choices

)100-1000

fic

proc

esso

r

nerg

y E

ffic

ienc

y (i

n M

OP

S/m

W)

1-10

10-100H

ardw

ired

cus

tom

le/P

aram

eter

izab

le Dom

ain-

spec

i f(e

.g. D

SP

)

Em

bedd

ed m

icro

proc

esso

r

En

Flexibility(or application scope)

0.1-1

None Fullyflexible

Somewhatflexible

Con

figu

rab

EECS 427 F09 Lecture 20 5

Implementation Choices

Digital Circuit Implementation Approaches

Custom

Cell-based Array-based

Semicustom

Digital Circuit Implementation Approaches

Standard CellsCompiled Cells Macro Cells Pre-diffused

(Gate Arrays)Pre-wired(FPGA's)

EECS 427 F09 Lecture 20 6

4

Cell-based DesignLogic cellFeedthrough cell

Routing channel requirements areFunctional

Routingchannel

Row

s of

cel

ls

requirements arereduced by presenceof more interconnectlayers

module(RAM,multiplier, …)

EECS 427 F09 Lecture 20 7

Standard Cell — Example

[Brodersen92]

EECS 427 F09 Lecture 20 8

5

Standard Cell

Cell-structurehidden underinterconnect layers

EECS 427 F09 Lecture 20 9

Timing Model

EECS 427 F09 Lecture 20 10

6

Standard Cell - Example

3 input NAND cell3-input NAND cell(from ST Microelectronics):C = Load capacitanceT = input rise/fall time

EECS 427 F09 Lecture 20 11

MacroModules

25632 (or 8192 bit) SRAMGenerated by hard-macro module generator

EECS 427 F09 Lecture 20 12

7

“Soft” MacroModules

Synopsys DesignCompiler

“Intellectual Property”

A Protocol Processor for Wireless

EECS 427 F09 Lecture 20 14

8

Semicustom Design Flow

HDLHDL

BehavioralBehavioralDesign Capture

Logic SynthesisLogic Synthesis

FloorplanningFloorplanning

PlacementPlacement

Pre-Layout SimulationPre-Layout Simulation

Post-Layout Simulation

Post-Layout Simulation

StructuralStructural

PhysicalPhysical

Des

ign

Iter

atio

nD

esig

n It

erat

ion

RoutingRouting

Tape-out

Circuit ExtractionCircuit Extraction

yy

EECS 427 F09 Lecture 20 15

The “Design Closure” Problem

Courtesy Synopsys

Iterative Removal of Timing Violations (white lines)

9

Integrating Synthesis with Physical Design

RTL (Timing) Constraints

Physical SynthesisPhysical Synthesis

Netlist with Place-and-Route Info

MacromodulesFixed netlists

Place-and-RouteOptimization

Place-and-RouteOptimization

ArtworkEECS 427 F09 Lecture 20 17

2-input muxas programmable logic block

Configuration

FA 0

B 1

A B S F=

0 0 0 00 X 1 X0 Y 1 Y0 Y X XYX 0 YY 0 XY 1 X X 1 Y

XYXY

S1 0 X1 0 Y1 1 1 1

XY

EECS 427 F09 Lecture 20 18

10

Logic Cell of Actel Fuse-Based FPGA

AA

B

SA Y

1

C

D 1

1

SBS0S1

EECS 427 F09 Lecture 20 19

Look-up Table Based Logic Cell

Out

Mem

ory In Out

00 00

01 1

10 1

ln1 ln2

11 0

EECS 427 F09 Lecture 20 20

11

LUT-Based Logic Cell

D

C1....C4

xx

4

xxxx xxxx xxxx

BitsD4

D3

D2

D1

F4

F3

F2

Logicfunction

ofxxx

Logicfunction

ofxxx

Logicfunction

of

xxxxxxxx

xxxxxxxx

xxx

Bitscontrol

Bitscontrol

x

xx

xx

xxx xx

xxxx

xxxxxx

xx

x xxx

Courtesy Xilinx

xxxxxx

2

F1

xxx

HP

Multiplexer Controlledby Configuration Program

x x

xx xx

Xilinx 4000 Series

EECS 427 F09 Lecture 20 21

Mesh-based Interconnect Network

Switch Box

Connect Box

InterconnectPointPoint

Courtesy Dehon and WawrzyniekEECS 427 F09 Lecture 20 22

12

Transistor Implementation of Mesh

Courtesy Dehon and WawrzyniekEECS 427 F09 Lecture 20 23

Hierarchical Mesh Network

Use overlayed meshto support longer connections

Reduced fanout and reduced resistance

Courtesy Dehon and WawrzyniekEECS 427 F09 Lecture 20 24

13

Xilinx 4000 Interconnect Architecture

12 Quad12

8

4

3

2CLB

Quad

Single

Double

Long

DirectConnect

2

3

8 4 8 4

DirectConnect

Quad Long GlobalClock

Long Double Single GlobalClock

CarryChain

Long

12 4 4

Courtesy XilinxEECS 427 F09 Lecture 20 25