ee201 final sp2012.fm original design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel...

ee201_final_Sp2012.fm

5/8/12EE201L M

idterm #2 - Spring 2012 8 / 8

CC

opyright 2012 Gandhi Puvvada

7 ( 12 points) 5 m

in. Topic: 4-bit Barrel Shifter design

Given on the bottom

of this page is the original logarithmic right-shifting barrel shifter design discussed

in class. Com

plete it by labelling the 8 missing connections. The second design is a sim

ilar design is shown

with select line S0 controlling the first colum

n of muxes and S1 controlling the second colum

n of muxes.

Com

plete this design also, if it is possible to do so, otherwise state w

hy it can not be completed.

S1 S0

I0

I1

I2

I3

Y0

Y1

Y2

Y3

S1

S0

Original Design

S0 S1

I0

I1

I2

I3

Y0

Y1

Y2

Y3

S0

S1

New Design (See S1 and S0 connections)

INT0

INT1

INT2

INT3

INT_new_0

INT_new_1

INT_new_2

INT_new_3

The TAs, G

raders, and I have enjoyed teaching this course. Hope you also liked the course. H

ope to see you again in EE454L and EE457. -- Gandhi

ee201_final_Sp2012.fm

5/2/12EE201L M

idterm #2 - Spring 2012 8 / 8

CC

opyright 2012 Gandhi Puvvada

7 ( points) m

in. Topic: 4-bit Barrel Shifter design

Given on the left is the original logarithm

ic barrel shifter design discussed in class. Com

plete it by labelling the 8 m

issing connections. In the right, a similar design is show

n with select line S0 controlling

the first column of m

uxes and S1 controlling the second column of m

uxes. Com

plete the right-side design also, if it is possible to do so, otherw

ise state why it can not be com

pleted.

S1 S0

I0

I1

I2

I3

Y0

Y1

Y2

Y3

S1

S0

Original Design

S0 S1

I0

I1

I2

I3

Y0

Y1

Y2

Y3

S0

S1

New Design (See S1 and S0 connections)

INT0

INT1

INT2

INT3

INT_new_0

INT_new_1

INT_new_2

INT_new_3

The TAs, G

raders, and I have enjoyed teaching this course. Hope you also liked the course. H

ope to see you again in EE454L and EE457. -- Gandhi

Page 3: ee201 final Sp2012.fm Original Design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel shifters and a fixed priority resolver. Design a 3-input 3-output barrel shifter (a) by

EE354L_Final_Fall2015.fm

3 ( 36 points) 25 min. Fixed Priority Resolver, Barrel shifter, active levels

3.1 At the end of the chapter on the above topic, we had the "4 low-active inputs 4 low active output Fixed Priority Resolver" shown on the left. In another design, the bottom two requests are high-active and the top two grants are needed to be high-active. Complete the FPR design on the right using the least number of inverters and 3 standard gates (any mix of AND/OR/NAND/NOR). Name all 3 standard gates except inverters as AND/OR/NAND/NOR.

3.2 We designed a 4-input 4-output right-shifting barrel shifter assuming that the S1 S0 represent right-shifting by 0, 1, 2, or 3 depending on S1S0 = 00, 01, 10, and 11. We assumed that everyone uses unsigned binary numbers when it comes to S1S0. Our design is shown on the far left below. Three more copies of the same design are given for you to modify to suit our special customers from the planet MARS who treated the S1S0 as (a) Gray Code (b) Signed numbers represented in 2’s- Complement system (c) Signed numbers represented in Sign-Magnitude system. Negative 1 means rotate left by 1 step which same as rotate right by 3. Negative 2 means rotate left by which is same as rotate right by 2. Modify our original design to the least amount by adding one or two gates as necessary between the external select pins and internal select lines. Relabeling of inputs and/or outputs is allowed if needed. Recall that our right-shifting barrel shifter can be used as a left-shifting barrel shifter by just relabeling!

~R0

~R1

~R2

~R3

~G0

~G1

~G2

~G3

~R0

~R1

R2

R3

G0

G1

~G2

~G3

12 pts

24 pts

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I0

I2 M1Y0

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I1

I3 M2Y1

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I2

I0 M3Y2

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I3

I1 M0Y3

M0

M1

M2

M3

Y0

Y1

Y2

Y3

I0

I1

I2

I3

S0S1

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I0

I2 M1Y0

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I1

I3 M2Y1

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I2

I0 M3Y2

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I3

I1 M0Y3

M0

M1

M2

M3

Y0

Y1

Y2

Y3

I0

I1

I2

I3

S0S1

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I0

I2 M1Y0

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I1

I3 M2Y1

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I2

I0 M3Y2

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I3

I1 M0Y3

M0

M1

M2

M3

Y0

Y1

Y2

Y3

I0

I1

I2

I3

S0S1

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I0

I2 M1Y0

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I1

I3 M2Y1

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I2

I0 M3Y2

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I3

I1 M0Y3

M0

M1

M2

M3

Y0

Y1

Y2

Y3

I0

I1

I2

I3

S0S1

Page 4: ee201 final Sp2012.fm Original Design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel shifters and a fixed priority resolver. Design a 3-input 3-output barrel shifter (a) by

EE354L_Final_Fall2015.fm

3 ( 36 points) 25 min. Fixed Priority Resolver, Barrel shifter, active levels

3.1 At the end of the chapter on the above topic, we had the "4 low-active inputs 4 low active output Fixed Priority Resolver" shown on the left. In another design, the bottom two requests are high-active and the top two grants are needed to be high-active. Complete the FPR design on the right using the least number of inverters and 3 standard gates (any mix of AND/OR/NAND/NOR). Name all 3 standard gates except inverters as AND/OR/NAND/NOR.

3.2 We designed a 4-input 4-output right-shifting barrel shifter assuming that the S1 S0 represent right-shifting by 0, 1, 2, or 3 depending on S1S0 = 00, 01, 10, and 11. We assumed that everyone uses unsigned binary numbers when it comes to S1S0. Our design is shown on the far left below. Three more copies of the same design are given for you to modify to suit our special customers from the planet MARS who treated the S1S0 as (a) Gray Code (b) Signed numbers represented in 2’s- Complement system (c) Signed numbers represented in Sign-Magnitude system. Negative 1 means rotate left by 1 step which same as rotate right by 3. Negative 2 means rotate left by which is same as rotate right by 2. Modify our original design to the least amount by adding one or two gates as necessary between the external select pins and internal select lines. Relabeling of inputs and/or outputs is allowed if needed. Recall that our right-shifting barrel shifter can be used as a left-shifting barrel shifter by just relabeling!

~R0

~R1

~R2

~R3

~G0

~G1

~G2

~G3

~R0

~R1

R2

R3

G0

G1

~G2

~G3

12 pts

24 pts

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I0

I2 M1Y0

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I1

I3 M2Y1

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I2

I0 M3Y2

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I3

I1 M0Y3

M0

M1

M2

M3

Y0

Y1

Y2

Y3

I0

I1

I2

I3

S0S1

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I0

I2 M1Y0

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I1

I3 M2Y1

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I2

I0 M3Y2

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I3

I1 M0Y3

M0

M1

M2

M3

Y0

Y1

Y2

Y3

I0

I1

I2

I3

S0S1

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I0

I2 M1Y0

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I1

I3 M2Y1

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I2

I0 M3Y2

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I3

I1 M0Y3

M0

M1

M2

M3

Y0

Y1

Y2

Y3

I0

I1

I2

I3

S0S1

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I0

I2 M1Y0

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I1

I3 M2Y1

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I2

I0 M3Y2

I0

I1Y

S

I0

I1Y

S

IS1 IS0

I3

I1 M0Y3

M0

M1

M2

M3

Y0

Y1

Y2

Y3

I0

I1

I2

I3

S0S1

Page 5: ee201 final Sp2012.fm Original Design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel shifters and a fixed priority resolver. Design a 3-input 3-output barrel shifter (a) by

ee201_Final_Fall2013.fm

4 ( 27 points) 15 min.

Barrel Shifters and Rotating Prioritizers:

4.1 2-input 2-output rotating prioritizer design: (a) complete the 2-input 2-output barrel shifter (cross switch on the left-end below) by labeling the internal I inputs appropriately. (b) then complete the rotating prioritizer design on the right by placing an inverter or just a wire in the box below. You need to explain adequately (why you chose to put an inverter or a wire) to gain points on this.

4.2 In our class we talked about Barrel shifters of size 2, 4, 8, 16 (all powers of 2) and discussed how we can reduce the cost by using logarithmic barrel shifters. But if we need to implement a rotating prioritizer for 3 requests and 3 grants, we need two 3-input 3-output barrel shifters and a fixed priority resolver.

Design a 3-input 3-output barrel shifter (a) by using three of 3-to-1 muxes (b) by replacing each of the 3-to-1 muxes with two of 2-to-1 muxes.

3+5 pts

I0

I1

Y0

Y1

CROSS

I0

I1Y

S

I0

I1Y

S

C

I

C

I

I0

I1

Y0

Y1

CROSS

I0

I1

Y0

Y1

CROSS

R0 G0

R1 G1

RQ0

RQ1

GT0

GT1

IDMRG

IDMRG = ID of the Most Recent Grantee

Place an inverteror a wire in the box

Explain:

I0

I1Y

S

I0

I1 Y

S1S0I2

S1 S0

I0

I1I2

I0

I1Y

SS1

S0

I

IY

Y

4 pts

6+9 pts

I0

I1 Y

S1S0I2

S1 S0

I

I0

I1 Y

S1S0I2

S1 S0

I

I0

I1 Y

S1S0I2

S1 S0

I

Y0

Y1

Y2

I0

I1

I2

S1 S0

Y0

Y1

Y2

I0

I1

I2

S1 S0

I0

I1Y

S I0

I1Y

SS1

S0

I

I0

I1Y

S I0

I1Y

SS1

S0

I

I0

I1Y

S I0

I1Y

SS1

S0

I

Page 6: ee201 final Sp2012.fm Original Design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel shifters and a fixed priority resolver. Design a 3-input 3-output barrel shifter (a) by

ee201_Final_Fall2013.fm

4 ( 27 points) 15 min.

Barrel Shifters and Rotating Prioritizers:

4.1 2-input 2-output rotating prioritizer design: (a) complete the 2-input 2-output barrel shifter (cross switch on the left-end below) by labeling the internal I inputs appropriately. (b) then complete the rotating prioritizer design on the right by placing an inverter or just a wire in the box below. You need to explain adequately (why you chose to put an inverter or a wire) to gain points on this.

4.2 In our class we talked about Barrel shifters of size 2, 4, 8, 16 (all powers of 2) and discussed how we can reduce the cost by using logarithmic barrel shifters. But if we need to implement a rotating prioritizer for 3 requests and 3 grants, we need two 3-input 3-output barrel shifters and a fixed priority resolver.

Design a 3-input 3-output barrel shifter (a) by using three of 3-to-1 muxes (b) by replacing each of the 3-to-1 muxes with two of 2-to-1 muxes.

3+5 pts

I0

I1

Y0

Y1

CROSS

I0

I1Y

S

I0

I1Y

S

C

I

C

I

I0

I1

Y0

Y1

CROSS

I0

I1

Y0

Y1

CROSS

R0 G0

R1 G1

RQ0

RQ1

GT0

GT1

IDMRG

IDMRG = ID of the Most Recent Grantee

Place an inverteror a wire in the box

Explain:

I0

I1Y

S

I0

I1 Y

S1S0I2

S1 S0

I0

I1I2

I0

I1Y

SS1

S0

I

IY

Y

4 pts

6+9 pts

I0

I1 Y

S1S0I2

S1 S0

I

I0

I1 Y

S1S0I2

S1 S0

I

I0

I1 Y

S1S0I2

S1 S0

I

Y0

Y1

Y2

I0

I1

I2

S1 S0

Y0

Y1

Y2

I0

I1

I2

S1 S0

I0

I1Y

S I0

I1Y

SS1

S0

I

I0

I1Y

S I0

I1Y

SS1

S0

I

I0

I1Y

S I0

I1Y

SS1

S0

I

Page 7: ee201 final Sp2012.fm Original Design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel shifters and a fixed priority resolver. Design a 3-input 3-output barrel shifter (a) by

7 ( 19 + 15 + 10 + 4 = 48 points) 15 min. Miscellaneous

7.1 In a rotating prioritizer of 4 inputs and 4 outputs if the ID of the lowest priority requester is #1 then his request is pushed down to the lowest as shown on the side. Draw a similar line to show that the next requester (#2) is elevated to the top. Muxes are present in ___________ (IR/FPR/OR/multiple of these (list them)) Note: IR = Input Rotator, OR = Output Rotator, FPR = Fixed Priority Resolver. Our design ____________ (assumes/does not assume) that the recipient of the Grant can utilize the grant in one clock. Explain: ______________________________________________________________________________________________________________________________________________________________________________________________________________________Sometimes the ID of the most recent grantee may not change for hours. How can this happen? ______________________________________________________________________________________________________________________________________________________________

7.2 I2C: Suppose three masters establish the START condition simultaneously and call upon their respective salves. Master #1 calls slave with address 30H (011_0000), Master #2 calls slave with address 21H (010_0001), Master #3 calls slave with address 22H (010_0010). Address is sent out with MSB (first) on SDA during the address phase of the transaction. Figure out how arbitration occurs, who back-off and who continues. ___________________________________________________________________________________________________________________________________________________________________________________________________________There ________________ (is a way / isn’t any way) to implement rotating priority in I2C.The following is a brief excerpt of the SCL (serial clock) behavior in an I2C operation.

At Area A, the SCL is low for longer time in the middle of a data transfer. Possible reason is __ ________________________________________________________________________________________________________________________________________________________And at Area B, when the Bus is not Busy, the SCL is high for longer time. Possible reason is __ ________________________________________________________________________________________________________________________________________________________

7.3 Name the two handshake protocols. _____ (2-/4-) way is better (less overhead)On producer side as well as on the consumer side, we need a 3-state state machine in the case of a _____ (2-/4-) way handshake where as we need a 4-state state machine in the other case. FIFO is ____________ (inferior/superior) to both of these.Handshake ______ (is/isn’t) necessary _______ (if/even if) the producer and consumer are working on a common clock.

7.4 An asynchronous reset signal requires synchronization to the system clock ___________ (A/B/C/D). A= while going into RESET, B = while coming out of RESET, C= both ways, D = neither way

0123

IR ORFPR

19 pts

15pts

SCL Area A Area B

takegot

data_1 data_2

P1 P2C1 C2

The _____-way handshake

P1: Take itC1: Got it

P2: Take nextC2: got next

take

got

data data

P1 P2C1 C2

The _______-way handshake

P1: Take itC1: Got it

P2: I see that you got itC2: I see that you saw that I got it

10pts

Page 8: ee201 final Sp2012.fm Original Design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel shifters and a fixed priority resolver. Design a 3-input 3-output barrel shifter (a) by

3 ( 20 + 18 + 21 = 59 points) 45 min. Barrel Shifters, RPR, Verilog

3.1 Reproduced below is a question (Q#6.3 with solution) from Fall 2017 final that you are asked to go through. If we need to change the design from the 4-input 4-output RPR to an 8-input 8-output RPR, find how the design scales up (what are the various changes). Answer the questions in boldface below.

20pts

We built, in class, a 4-input 4-output Rotating Priority Resolver (RPR) shown on next page using (i) an Input Rotator (IR), (ii) a Fixed Priority Resolver (FPR), (iii) an Output Rotator (OR), (iv)a one-hot input to encoded output encoder, and (v) a Most Recent Grantee ID recording register.

Complete the function table for the encoder, draw gate level logic to produce the encoded outputsID1 and ID0 and also draw gate-level logic to produce the UPDATE signal

These 5 items change from 4 signals to ____ signals. This changes from 2 signals to ____signals.

A. These two 2-input OR gates change to ____ of ____-input _______ (OR/AND/NAND/NOR) gates.

A

B

B. This 4-input OR gates changes to ____-input _______ (OR/AND/NAND/NOR) gate.

C D

E

C. These two 2-input Muxes change to ____ of ____-input _______ Muxes. D. These two recirculating FFs change to ____ of _____________ (recirculating/non-recirculating) FFs. E. This 4-input 2-output Table with 5 rows of significant information changes to ____-input _____-output Table with _____ rows of significant information.

Page 9: ee201 final Sp2012.fm Original Design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel shifters and a fixed priority resolver. Design a 3-input 3-output barrel shifter (a) by

3 ( 20 + 18 + 21 = 59 points) 45 min. Barrel Shifters, RPR, Verilog

20pts

A

B

C D

E

Page 10: ee201 final Sp2012.fm Original Design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel shifters and a fixed priority resolver. Design a 3-input 3-output barrel shifter (a) by

Page 8 of 16

Page 11: ee201 final Sp2012.fm Original Design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel shifters and a fixed priority resolver. Design a 3-input 3-output barrel shifter (a) by

Page 12: ee201 final Sp2012.fm Original Design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel shifters and a fixed priority resolver. Design a 3-input 3-output barrel shifter (a) by

3.2 You were provided with a Verilog code for the 4-input 4-output barrel shifter. Please complete below the incomplete statement in the adjacent always block.2’b10: Y = ;

Can we replace the four blocking assignment indicators (=) with non-blocking assignment indicators (<=)? Yes / No Explain ____________________________________________________________________________________________

If we make it a clocked always block [always @(posedge CLK)] and also replace the four assignment indicators with non-blocking assignment indicators (<=), we will be inferring ______ (4/16/other (state)) FFs.

Reproduced below is an extract from the testbench for the above. Is it OK to move the #10; statement from the current position A to the new position B?Both A and B positions are before the I_tb or the S_tb is incremented, so you perform the 64 tests (16 of I_tb values * 4 of S_tb values) = total 64 test combinations, each spaced by 10ns.

_____________________________________________________________________________ _____________________________________________________________________________ _____________________________________________________________________________ _____________________________________________________________________________ Does your testbench run faster if we change the timescale directive from the current`timescale 1ns / 100ps to the new `timescale 100ps / 10ps Yes / NoExplain: ________________________________________________________________Note: With the proposed change, the #10; will be interpreted as "wait for 1 ns (10*100ps = 1000 ps)" instead of the earlier "wait for 10 ns"

always @(*) case(S) 2'b00: Y = I; 2'b01: Y = {I[0], I[3:1]}; 2'b10: Y = ; default: Y = {I[2:0], I[3]}; endcase

18pts

Page 13: ee201 final Sp2012.fm Original Design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel shifters and a fixed priority resolver. Design a 3-input 3-output barrel shifter (a) by

3.2 You were provided with a Verilog code for the 4-input 4-output barrel shifter. Please complete below the incomplete statement in the adjacent always block.2’b10: Y = ;

Can we replace the four blocking assignment indicators (=) with non-blocking assignment indicators (<=)? Yes / No Explain ____________________________________________________________________________________________

If we make it a clocked always block [always @(posedge CLK)] and also replace the four assignment indicators with non-blocking assignment indicators (<=), we will be inferring ______ (4/16/other (state)) FFs.

Reproduced below is an extract from the testbench for the above. Is it OK to move the #10; statement from the current position A to the new position B?Both A and B positions are before the I_tb or the S_tb is incremented, so you perform the 64 tests (16 of I_tb values * 4 of S_tb values) = total 64 test combinations, each spaced by 10ns.

_____________________________________________________________________________ _____________________________________________________________________________ _____________________________________________________________________________ _____________________________________________________________________________ Does your testbench run faster if we change the timescale directive from the current`timescale 1ns / 100ps to the new `timescale 100ps / 10ps Yes / NoExplain: ________________________________________________________________Note: With the proposed change, the #10; will be interpreted as "wait for 1 ns (10*100ps = 1000 ps)" instead of the earlier "wait for 10 ns"

always @(*) case(S) 2'b00: Y = I; 2'b01: Y = {I[0], I[3:1]}; 2'b10: Y = ; default: Y = {I[2:0], I[3]}; endcase

18pts

Page 14: ee201 final Sp2012.fm Original Design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel shifters and a fixed priority resolver. Design a 3-input 3-output barrel shifter (a) by

5 ( 20 + 18 = 38 points) 30 min. Barrel Shifters, RPR, Verilog

20pts

A

B

C D

E

Page 15: ee201 final Sp2012.fm Original Design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel shifters and a fixed priority resolver. Design a 3-input 3-output barrel shifter (a) by

5 ( 20 + 18 = 38 points) 30 min. Barrel Shifters, RPR, Verilog

20pts

A

B

C D

E

ee201 final sp2012.fm original design ( 12 points) 5 min ...€¦ · 3-input 3-output barrel...

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