EE166 Final Presentation

Patsapol KriausakulSung Min ParkDennis WonHoward Yuan

Objectives

To build a 4-bit serial to parallel converter.

Use cadence to design and test our converter circuit.

Use cadence to layout our design.

Design Functionality

Circuit will take serial data streamat 25mhz and convert to a 4-bit parallel bit stream every 4 clock cycles.

Design Specifications Circuit operates on positive edge of clock. All data registers set to logic 0 upon reset going

low. Output buffers can drive 10pf load. Minimized clock skew. Fabrication using AMI16 process. Power consumption of entire design less than

500mw. Equal high and low noise margins of

VswitchingTH=2.5V within 10%. Whole design must fit in a 40mil2 area.

D Flip Flop 4 D flip-flops are implemented into

the converter. Each flip-flop produces a single

output which is read as part of a parallel sequence.

Used master-slave D-latches for positive edge transition.

Schmitt Trigger Input stage to give our converter

noise immunity. VswitchingTH should be equal to 2.5V

with in 10%.

Super Buffer Output stage used to allow our

design to drive a 10pf load with minimal signal propagation delay time.

Converter Design Includes Schmitt trigger, 4 D flip-

flops, and 4 super buffers. Area of design is 1700um X 900um. Clock skew is minimized in layout. Design functionality specifications

satisfied.

Power Circuitry for measuring power. Our power consumption is 248mw

for one period, which satisfies the specification requirement of 500mw for one period.

Conclusion 4-bit serial to parallel converter

achieved. Design flow. Converter test bench. Questions?!!