ee141-fall 2010 digital integrated...
TRANSCRIPT
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EE1411
EECS141 1Lecture #4
EE141EE141--Fall 2010Fall 2010Digital Integrated Digital Integrated CircuitsCircuits
Lecture 4Lecture 4CMOS Switches and GatesCMOS Switches and GatesDesign RulesDesign Rules
EE1412
EECS141 2Lecture #4
Administrative StuffAdministrative StuffFor this week, Hanh-Phuc’s office hours moved to today, 4-5pm (481 Cory)
Labs start this weekSoftware lab #2 starts FridayLab reports due the following week in lab
Homework #2 due this Thurs.Homework #3 out this Thurs.
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EE1413
EECS141 3Lecture #4
Review: Review: VTCsVTCs
EE1414
EECS141 4Lecture #4
Review: DelayReview: DelayIs it possible for a gate to have negative delay?
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EE1415
EECS141 5Lecture #4
Review: EnergyReview: EnergyPulsed inverter
EE1416
EECS141 6Lecture #4
Class MaterialClass MaterialLast lecture
Transistor as a switch, inverterDesign metrics
Today’s lectureDetailed switch modelCMOS gates (intro to Ch. 3, 6)Design rules (Ch. 2.3)
Reading (2.3, 3.3.1-3.3.2, 6.1-6.2.1)
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EE1417
EECS141 7Lecture #4
Switch Model of MOS TransistorSwitch Model of MOS Transistor
|VGS|
S D
G
|VGS| < |VT| |VGS| > |VT|
Ron
S D S D
EE1418
EECS141 8Lecture #4
MOS Switch Model (Capacitance)MOS Switch Model (Capacitance)
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EE1419
EECS141 9Lecture #4
Switch Model (Width)Switch Model (Width)
EE14110
EECS141 10Lecture #4
CMOS Inverter ModelCMOS Inverter Model
Vin Vout
CL
VDD
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EE14111
EECS141 11Lecture #4
CMOS LogicCMOS Logic
EE14112
EECS141 12Lecture #4
The CMOS Inverter: A First GlanceThe CMOS Inverter: A First Glance
Vin Vout
CL
VDD
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EE14113
EECS141 13Lecture #4
Static CMOS GatesStatic CMOS GatesAt every point in time (except during the switchingtransients) each gate output is connected to eitherVDD or VSS via a low resistive path.
The outputs of the gates assume at all times the valueof the Boolean function implemented by the circuit(ignoring, once again, the transient effects during switching periods).
(Will contrast this later to dynamic circuit style.)
EE14114
EECS141 14Lecture #4
Static Complementary CMOSStatic Complementary CMOSVDD
F(In1,In2,…InN)
In1In2InN
In1In2InN
PUN
PDN
PMOS only
NMOS only
PUN and PDN are dual logic networksPUN and PDN functions are complementary
……
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EE14115
EECS141 15Lecture #4
Threshold DropsThreshold DropsVDD
VDD → 0PDN
0 → VDD
CL
CL
PUN
VDD
0 → VDD - VTn
CL
VDD
VDD
VDD → |VTp|
CL
S
D S
D
VGS
S
SD
D
VGS
EE14116
EECS141 16Lecture #4
NMOS Transistors NMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection
Y = X if A AND B
Y = X if A OR B
Transistor ↔ switch controlled by its gate signalNMOS switch on when switch control input is high
NMOS transistors pass a “strong” 0 but a “weak” 1
A B
X Y
X Y
A
B
AND
OR
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EE14117
EECS141 17Lecture #4
PMOS Transistors PMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection
PMOS switch on when switch control is low
PMOS transistors pass a “strong” 1 but a “weak” 0
X Y
A B
A
BX Y
NOR
NAND
Y = X if A AND B = A + B
Y = X if A OR B = AB
EE14118
EECS141 18Lecture #4
Complementary CMOS Logic StyleComplementary CMOS Logic StylePUP is the dual to PDN(can be shown using DeMorgan’s Theorems)
Static CMOS gates are always inverting
A + B = AB
AB = A + B
AND = NAND + INV
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EE14119
EECS141 19Lecture #4
Example Gate: NANDExample Gate: NAND
PDN: G = AB ⇒ Conduction to GNDPUN: F = A + B = AB ⇒ Conduction to VDD
G(In1,In2,In3,…) ≡ F(In1,In2,In3,…)
EE14120
EECS141 20Lecture #4
Example Gate: NORExample Gate: NOR
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EE14121
EECS141 21Lecture #4
Complex CMOS GateComplex CMOS Gate
OUT = D + A • (B + C)
DA
B C
D
AB
C
EE14122
EECS141 22Lecture #4
CMOS PropertiesCMOS PropertiesFull rail-to-rail swingSymmetrical VTCPropagation delay function of load capacitance and resistance of transistorsNo static power dissipation
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EE14123
EECS141 23Lecture #4
Design RulesDesign Rules
EE14124
EECS141 24Lecture #4
Transistor LayoutTransistor Layout
p-well SiO2
poly
SiO2
n+
Cross-Sectional View
Layout View
poly
p-well
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EE14125
EECS141 25Lecture #4
CMOS Process LayersCMOS Process LayersLayer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
RedBlue
MagentaBlack
BlackBlack
Well contact (p+,n+) Green
EE14126
EECS141 26Lecture #4
Layers in 0.25 Layers in 0.25 µµm CMOS processm CMOS process
(well contacts)
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EE14127
EECS141 27Lecture #4
Design RulesDesign Rules
Interface between designer and process engineerGuidelines for constructing process masksUnit dimension: Minimum line width
scalable design rules: lambda parameterabsolute dimensions (micron rules)
EE14128
EECS141 28Lecture #4
Design RulesDesign Rules
Intra-layerWidths, spacing, area
Inter-layerEnclosures, distances, extensions, overlaps
Special rules (sub-0.25µm)Antenna rules, density rules, (area)
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EE14129
EECS141 29Lecture #4
IntraIntra--Layer Design RulesLayer Design Rules
Metal2 4
3
10
90
Well
Active3
3
Polysilicon2
2
Different PotentialSame Potential
Metal1 3
32
Contactor Via
Select2
or6
2Hole
EE14130
EECS141 30Lecture #4
InterInter--Layer: Transistor LayoutLayer: Transistor Layout
1
2
5
3
Tran
sist
or
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EE14131
EECS141 31Lecture #4
InterInter--Layer: Layer: ViasVias and Contactsand Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
EE14132
EECS141 32Lecture #4
InterInter--Layer: Well and SubstrateLayer: Well and Substrate
1
3 3
2
2
2
WellSubstrate
Select3
5
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EE14133
EECS141 33Lecture #4
CMOS Inverter LayoutCMOS Inverter Layout
A A’
np-substrate Field
Oxidep+n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A’
A A’
EE14134
EECS141 34Lecture #4
Layout EditorLayout Editor
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EE14135
EECS141 35Lecture #4
Design Rule CheckerDesign Rule Checker
EE14136
EECS141 36Lecture #4
Layout vs. Schematic (LVS)Layout vs. Schematic (LVS)
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EE14137
EECS141 37Lecture #4
Sticks DiagramSticks Diagram
1
3
In Out
VDD
GND
Stick diagram of inverter
• Dimensionless layout entities• Only topology is important
EE14138
EECS141 38Lecture #4
Circuit Under DesignCircuit Under DesignVDD VDD
Vin Vout
M1
M2
M3
M4
Vout2
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EE14139
EECS141 39Lecture #4
CMOS InverterCMOS Inverter
Polysilicon
In Out
VDD
GND
PMOS 2λ
Metal 1
NMOS
OutIn
VDD
PMOS
NMOS
Contacts
N Well
EE14140
EECS141 40Lecture #4
Two InvertersTwo Inverters
Connect in Metal
Share power and ground
Abut cells
VDD
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EE14141
EECS141 41Lecture #4
Next LectureNext Lecture
Overview of semiconductor memory