12 December 2012Clive “Max” Maxfield

All ProgrammableFPGAs, SoCs, and 3D ICs

Part III. Design Tools and Methodologies

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The Good Old Days

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The Good Old Days (cont.)

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The Good Old Days (cont.)

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Mixed-Level Design

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Simulation and Synthesis

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New Devices – New Challenges

Yesterday: ProgrammableLogic Devices

(PLDs) Today: All Programmable Devices (APDs)

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These Aren’t Your Mother’s FPGAsConsiderations with today’s All Programmable FPGAs, SoCs, and 3D ICs

• Humongous capacity• Large numbers of hard cores (routing issues)• Designs demand high-performance• Designs are IP-Centric• Designers need to manage IP• Designers need to explore design space

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Next-Gen Tools/Methodologies

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Better Quality of Results (QoR)

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IP Packager and IP Integrator

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System Generator for DSP

Vivado HLS Integration

Modeling & Abstraction

Code Generation

QoR/IP Reuse

Debug & Verification

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Vivado High-Level Synthesis (HLS)

Comprehensive Integration with the Xilinx Design Environment

Comprehensive Integration with the Xilinx Design Environment

VHDL or VerilogVHDL or Verilog

System IP IntegrationSystem IP Integration

C, C++ or SystemCC, C++ or SystemC

RTL ImplementationRTL Implementation

Micro Architecture ExplorationMicro Architecture Exploration

Algorithmic SpecificationAlgorithmic Specification

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HLS Exploration and Optimization

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HLS Accelerates ProductivityConventional

HDL-based approach

Functional Verification with C Compiler

Final Validation

Verified RTL

Functional VerificationUsing HDL simulation

VerifiedRTL

Hours-days per iteration

Seconds per iteration

C-based Approach

RTLRTL RTLRTL

C

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Post-Synthesis Power OptimizationBefore

After

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Conventional Methodology

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Modern Methodology

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Modern Methodology (cont.)

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Next Stop – The 20nm Node

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Next Stop – The 20nm Node

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Bugs Are Everywhere!

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Creating Rad-Tolerant Designs

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More Information / Further Readingwww.AllProgrammablePlanet.c

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