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THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

1

ECNG 3016

ADVANCED DIGITAL ELECTRONICShttp://myelearning.sta.uwi.edu/course/view.php?id=686

Semester II 2009

1. GENERAL INFORMATION

Lab #: 3 – Part A

Name of the Lab: Xilinx Tool Flow Lab

Lab Weighting: 0% Estimated totalstudy hours

1:

2

Delivery mode: Lecture

Online

Lab Other

Venue for the Lab: Microprocessor Laboratory

Lab Dependencies2 The theoretical background to this lab is provided in ECNG 3016

Theoretical content link: given at top of page

Pre-Requisites – ECNG 2004

Recommended

prior knowledge

and skills3:

To undertake this lab, students should be able to:

1. Use of Xilinx ISE and Modelsim in the implementation of digital

system2. VHDL programming

Course Staff Position/Role E-mail

Phone

Office Office

Hours

Lucien Ngalamou Lecturer [email protected] room 202

Marcus George Instructor [email protected] room 203

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THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

2

2. LAB LEARNING OUTCOMES

Upon successful completion of the lab assignment, students will be able to: Cognitive

Level

1.

Describe general FPGA architectures and the Xilinx design flow C

2. Use the architecture wizard to generate a DCM C, Ap

3. Use the Xilinx Constraints Editor to enter global timing constraints C, Ap

4. Run behavioral simulation on an FPGA design that contains cores Ap

5. Understand the basics of the PicoBlaze 8-bit controller C

3. PRE-LAB

3.1. Required Reading Resources

3.2. Recommended Reading Resources

3.3. Other Resources

3.4. Pre-Lab Exercise

Due Date:

Submission

Procedure:

Estimated time to

completion:

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Lab 3a: Xilinx Tool Flow Lab

4. IN-LAB

Allotted Completion

Time:

2 hours max

Required lab

Equipment:

1 Computer

1 Spartan 3 Toolkit

4.1. In-Lab Procedure

1 Introduction

This instructor-led demonstration introduces the ISE™ software.

2 Objectives

After participating in this demonstration, you will be able to:

• Step through the FPGA design flow

• Identify the features of the Digilent Spartan-3 board List the features of the PicoBlaze 8-bit controller

3 Procedure

This demonstration comprises four primary steps: you will create a new project, add design

files to the project, simulate the design, and finally implement the design. Below each general

instruction for a given procedure, you will find accompanying step-by-step directions and

illustrated figures that provide more detail for performing the general instruction. If you feel

confident about a specific instruction, feel free to skip the step-by-step directions and move on to

the next general instruction in the procedure.

Note: If you wish to review the demonstration at a later time, you can download the files from

the Xilinx University Program site at http://www.xilinx.com/univ

4 Introduction to the Spartan-3 Board

Throughout the workshop, you will use the Spartan-3 board to test your experiments during

the lab sessions. The requirements to complete the labs include the board, power supply,download cable, and RS232 serial cable. Detailed information can be found in the Spartan-3

starter kit user Guide, which is available with course material distribution , or you maydownload from http://www.digilentinc.com). Figure 1-1, taken from the user guide,

provides an illustration of the board.

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Figure 1-1. Illustration of Digilent Spartan-3 board

Summary of Key Features• 200,000 gate Spartan-3 xc3s00-4ft256 FPGA

- 4,320 logic cells (480 CLBs)

- 30K bits of distributed RAM

- 216K of BlockRAM- 12 dedicated 18x18 multipliers

- 4 Digital Clock Managers (DCM)

- 173 User I/O pins

- 76 maximum differential I/O pairs

• Push button switch to force FPGA configuration•

LED indicates when FPGA is successfully configured

•

Three fourty-pin expansion connectors to extend functionality• JTAG port for low-cost download cable•

Digilent JTAG download/debugging cable connects to PC parallel port

• JTAG download/debug port compatible with the Xilinx Parallel-IV and MultiPRO

desktop tool• Power-on indicator LED• On-board 3.3V, 2.5V, and 1.2V regulators

• 2Mbit Xilinx XCF02S Platform-Flash, in-system programmable configuration PROM• 1M-byte of fast asynchronous SRAM• 3-bit, 8-color VGA display port

• 9-pin RS232 serial port

•

PS/2-style mouse/keyboard port• Four-character, seven-segment LED display

• Eight slide switches

• Eight individual LED outputs•

Four momentary-contact push button switches

• 50 MHz crystal oscillator clock source

• FPGA configuration mode selected via jumper settings

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5 PicoBlaze Overview at a Quick Glance

This section attempts to provide a brief overview of the PicoBlaze microcontroller. Throughout the

lab sessions, you will use PicoBlaze to create designs that illustrate certain features of the ISEFoundation software and Digilent Spartan-3 board. These labs are by no means developed to train

on the PicoBlaze micro-controller. Detailed information can be found in the user guide and

documentation, which you can use as a reference when completing the labs. The information beloware exerts taken from the user guide.

PicoBlaze is a Free Download PicoBlaze is a free downloadable 8-bit microcontroller: refer to the PicoBlaze web site at

http://www.xilinx.com/products/design_resources/proc_central/grouping/picoblaze.htm .The

PicoBlaze files are provided with this distribution for convenience, which can be found in the

KCPSM3 sub-directory and include:

• PicoBlaze Source Code (VHDL and Verilog)

• UART Real-Time Clock reference design (VHDL and Verilog)•

Assembler

•

JTAG loader• Refer to User Guide and manuals for technical details, reference designs, and for answers to

questions such as- Why the PicoBlaze MicroController?- Why use a Microcontroller within an FPGA?

PicoBlaze Features

PicoBlaze is a fully embedded 8-bit microcontroller macro for the Virtex™ and Spartan™ series of

FPGAs and CoolRunner™-II CPLDs. The PicoBlaze reference designs support 57 to 59 different

16- or 18-bit instructions, 8 to 32 general-purpose byte-wide registers, up to 256 directly and

indirectly addressable ports, reset, and a maskable interrupt. The PicoBlaze controller for Spartan-3,

Virtex-4, Virtex-II, and Virtex-II Pro also include 64 bytes of scratchpad RAM.

As shown in figure 1-2 (taken from from user guide), the PicoBlaze microcontroller supports the

following features:• 16-byte wide general-purpose data registers• 1K-instructions of programmable on-chip program store, automatically loaded during FPGA

configuration

• Byte-wide ALU with CARRY and ZERO indicator flags•

64-byte internal scratchpad RAM

• 256 input and 256 output ports for easy expansion and enhancement

•

Automatic 31-location CALL/RETURN stack•

Predictable performance, always 2 clock cycles per instruction, up to 200 MHz or 100 MIPs in a

Virtex-II Pro FPGA

• Fast interrupt response; worst-case 5 clock cycles• Assembler, instruction-set simulator support

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Figure 1-2. PicoBlaze Block Diagram

Figure 1-3 illustrates the top-level interface signals of the PicoBlaze microcontroller along withexample applications.

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Figure 1-3. Interface connections and possible applications

Development Environments

There are three primary development environments for creating PicoBlaze application code, assummarized in Table 10-1 of the user guide. Xilinx offers two PicoBlaze environments. The

PicoBlaze reference design includes the KCPSM3 command-line assembler that executes in a

Windows DOS box or command window. The Xilinx System Generator for DSP development

environment includes both a PicoBlaze assembler and a simulation model for the Math WorksMATLAB/Simulink environment. The Mediatronix pBlazIDE software is a graphical development

environment including an assembler and full-featured instruction-set simulator(ISS).

In this workshop, you will use the KCPSM3 command-line assembler to compile assembly code.

The assembler is provided as a simple DOS executable file together with three template files.Programs are best written with either the standard Notepad or Wordpad tools available on most

Windows computers. However, any PC-format text editor is sufficient. Save the PicoBlaze

assembly program with a PSM file extension that has an eight-character name limit.

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Input and Output Files

The assembler reads in four input files and creates 15 output files as shown in figure 1-4. Theassembler reads the PicoBlaze source program, .psm, and three template files that

instantiate and initialize a block RAM in various design flows.

Figure 1-4. Input and Output Files to the KCPSM3 assembler

If the source program is free of errors, the KCPSM3 assembler generates an object code output,

formatted for a variety of design flows, based on the initial template files. These output filesgenerate the code ROM, instantiated as block RAM, and properly initialized with the PicoBlaze

object code. The assembler also generates equivalent raw decimal and hexadecimal files for otherutilities.

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Let’s Get Started Step 1

Launch the ISE Project Navigator and create a new design project.

Select Start → Programs→ Xilinx ISE 7.1i → Project Navigator

Some popups may appear with messages regarding reading a network directory or

running WebUpdate. These messages appear because we are running the tools on the

Toolwire servers, and they can be ignored. Dismiss the popups to continue.

In the Project Navigator, select File → New Project

The New Project Wizard opens (Figure 1-1)

Figure 1-5. New Project Wizard

For Project Name, type FlowLab

For Project Location, use the “…” button to browse to one of the following directories,and then click

• Verilog users: C:\lab1\labs\verilog\lab1 • VHDL users: C:\lab1\labs\vhdl\lab1

Click Next

The Device and Design Flow dialog will appear (Figure 1-6)

!

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Figure 1-6. Device and Design Flow Dialog

Select the following options and click Next:

1. Device Family: Spartan3

2. Device: xc3s200

3. Package: ft256

4. Speed Grade: –45. Synthesis Tool: XST (VHDL/Verilog)

6. Simulator: ISE Simulator

7.

Generated Simulation Language: VHDL or Verilog

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The Create New Source dialog will appear (Figure 1-7). You can use this dialog to

create a new HDL source file by defining the module name and ports. All of the source

files have been created for you in this project.

Figure 1-7. Create New Source Dialog

Click Next

The Add Existing Sources dialog appears (Figure 1-8).

Figure 1-8. Add Existing Sources Dialog

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Add Design Files for the Project Step 2

Add HDL source files into the project.

Click Add Source and browse to the C:\lab1\KCPSM3\VHDL or Verilog folder

Select the VHDL/Verilog files kcpsm3_int_test and kcpsm3 files and click Open.

A Choose Source Type box opens for each Verilog file (Figure 1-9). Choose VHDL or

Verilog Design File for each of the HDL files and click OK .

Figure 1-9. Choose Source Type

Note: You should see a module called int_test listed in the hierarchy view with a red

question mark. This module is a BlockRAM that will contain the instructions for the

PicoBlaze controller.

Assemble an Application and Finish the Design Step 3

An example PSM file called init_test.psm is included with the PicoBlaze distribution. You

will

assemble this file to generate the instruction ROM that will be integrated with the PicoBlazemicrocontroller.

Open up Windows Explorer and browse to the Assembler provided in the KCPSM3 sub-

directory (C:\lab1\KCPSM3\Assembler)

Note: The KCPSM3.exe assembler and ROM_form* template files along with two

example PSM files (refer to figure 1- ) should reside in this directory. Keep in mind

that the assembled output files will be generated in the directory containing theassembler and template files. It may be beneficial to copy the assembler and

template files to your project directory. For the workshop, we will keep the files in

the current location.

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Figure 1-10. Assembler Directory Content

Open the int_test.psm file using a standard text editor, such as Wordpad, and review the

code, refering to the PicoBlaze 8-bit Embedded Microcontroller User Guide or KCPSM3

manual for technical guidance. These files should reside in the Docs sub-directory.

Open a command window by going to Start Programs Accessories Command

Prompt

Browse to the Assembler directory (figure 1-11) using the cd command> cd C:\lab1\KCPSM3\Assembler

Figure 1-11. Command Window

Enter the following command at the command prompt to assemble the code and generate

the output program ROM files

> kcpsm3 int_test.psm

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Note: You should now see several files in the Assembler sub-directory starting with

init_test*, including VHDL (int_test.vhd) and Verilog (int_test.v) program ROMfiles.

In the ISE Project Navigator, go to Project Add Source and browse to the

int_test.vhd or int_test.v file in the C:\lab1\KCPSM3\Assembler directory path.

Figure 1-12. Add int_test HDL program ROM File to project

Click Open and then OK to add INIT_TEST as a VHDL/Verilog Design File to the project (figure 1- 13).

Figure 1-13. Hierarchical view of PicoBlaze design

Note: The top-level kcpsm3_int_test.vhd/v file contains an instantiation of the

int_test.vhd/v program ROM file. After adding this source code for the int_test.vhd/v tothe design, the red question mark in the module view will disappear as it is no longer

seen as a black box.

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Simulate the Design Step 4

Add the testbench testbench.vhd/.v and review the code. Then run a behavioral simulation

using the Xilinx iSIM simulator and examine the results.

In the Sources in Project window, go to Project Add Source and browse to

C:\lab1\KCPSM3\VHDL

Figure 1-14. Browse to the Test Bench File

Select the test_bench.vhd file and click

In the Choose Source Type dialogue, select Test Bench File and click to add the

test bench to the project.

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Figure 1-15. Hierarchical View Including Test Bench

With the testbench selected, expand the Xilinx ISE Simulator toolbox in the Processes

for Source window, right-click on Simulate Behavioral Model, and select Properties.

Enter the value of 10000 for the Simulation Run Time and click

Figure 1-16. iSIM Behavioral Simulation Properties

Double-click Simulate Behavioral Model

Two windows will appear when the simulation is complete. One window shows the

simulation results as waveforms, and the other shows the testbench in HDL format.

Figure 1-17. iSIM HDL Simulator

Click the waveform tab to view the simulation results. Zoom and pan to confirm that themodule simulated correctly

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Note: the design counts the number of interrupts detected. Refer to the software code

for further detail.

Close the simulator windows. Click Yes to confirm that you want to end the simulation

Implement the Design Step 4

Implement the design. During implementation, some reports will be created. You will lookmore closely at some of these reports in the next module.

In the Sources in Project window, select the top-level design file kcpsm3_int_test.vhd/v

In the Processes for Source window, double-click Implement Design (Figure 1-)

Notice that the tools run all of the processes required to implement the design. In thiscase, the tools run Synthesis before going into Implementation.

Figure 1-17. Processes for Source Window

While the implementation is running, click the + next to Implement Design to expand

the implementation step and view the progress. We refer to this as expanding a process

After each stage is completed, a symbol will appear next to each stage:

8. Green check mark for successful9.

Yellow exclamation point for warnings

10.

Red X for errors

For this particular design, there may be a yellow exclamation point (warnings) for some

steps. The warnings here are okay to ignore.

Read some of the messages in the message window located across the bottom of the

Project Navigator window.

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When implementation is complete, double-click View Design Summary (Figure 1-18)

and review the design utilization and performance summary.

Figure 1-18. Design Summary

Conclusion

In this demonstration, you completed the major stages of the ISE™ design flow: creating a

project, adding source files, simulating the design, and implementing the design.

In the next module, you will examine some of the software reports, determine how the design

was implemented, and determine whether or not your design goals for area and performance were

met.

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Proceed to post-lab exercise.

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5. POST-LAB

A signed plagiarism declaration form must be submitted with your assignment.

5.1. Assignment:

Due Date:

Submission

Procedure:

Deliverables:

End of Lab 3a: Xilinx Tool Flow Lab

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