ece 497 js lecture - 22 timing & signalingjsa.ece.illinois.edu/ece497js/lect_22.pdfece 497-js,...
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1Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
ECE 497 JS Lecture - 22Timing & Signaling
Spring 2004
Jose E. Schutt-AineElectrical & Computer Engineering
University of [email protected]
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2Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
- Signaling Techniques (4/27)
- Signaling - EMI/EMC – Overview (4/29)
- Q & A (5/4)
- Microstrip S-parameter data uploaded
Announcements
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3Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
INI5I4I3I2I1
RP RP RP RP RP RP
RP RP RP RP RPRP
VP
GND
V1 V1 V1 V1 V1 V1
2P w
PP
L rRNW
=2P P
PP
L WANk
=
2/ 2 / 2
21 1 4
PN N
pkIR pk P P
i i P
iJ L rV iJ A R
N k= =
= =∑ ∑
2/ 2
0 8P PL pk wpk w
IRP P
J r LJ r xV dx
k k= =∫
Model for On-Chip Power Distribution
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4Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
Chip 15 × 15 mm in area with 1M Gates. Each has a 200 fF load (40 fF gate, 160 fF wire) and switches on average every 1/3 cycle of a 100 MHz clock. Find total power dissipation of chip. Peak current to average current ratio is 4:1, how many metal layers are needed to distribute power so the overall supply fluctuation of a 2.5V supply in ± 250 mV?
1 1 200 2.5 100 16.673avg
dVI C M fF V MHz Adt
= = × × × × =2 2/(15 ) 0.0740 /avg avgJ I mm A mm= =
24 0.296 /peak avgJ J A mm= =
( )22 0.04 15 0.2961.332
8 8 0.25W peak
P
r L JK
V× × × ×
= = =× ×
( )22 0.04 15 0.2962.664
8 8 0.125W peak
P
r L JK
V× × × ×
= = =× ×
2 2
8 8Ppeak W W peak
IR PP IR
J r L r L JV K
K V× ×
= ⇒ =×
The number of metal layers is
However, if we think that the supply fluctuation is between the Gnd and Vdd, each layer has less than ± 125 mV. Thus for each Gnd and Vdd
From:
Bypass Capacitor Network Design (D&P 5-13)
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5Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
1k3 mm
1.2 µm
0.6 µmCo
Co=300 fF
Co
Cc=90 fF
Ccline a
line b
line c
The resistance of the wires are much smaller than the 1kΩ of the drivers and thus can be ignored
Worst case condition which will cause maximum delay is when the effective capacitance is maximum. If the 2 side aggressor lines transition in the opposite direction of the main driver on the victim line, this will create the most amount of capacitance (Miller effect)
(Dally & Poulton 6-3)
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6Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
– From table 6-3, we get kfx=-0.047, krx=0.058
Example (Dally & Poulton 6-5)
Aggressor
- +
- +
3.3V
0.3V Victim
A B 50
50
Far end crosstalk
C=C+Cm=88+6.4=94.4 pF/mL = 355 nH/m
1 1 81.73 10 m/s94.4 / 355 /
vLC pF m nH m
= = = ××
8
10 0.578 1.73 10x
cmt ns= =×
Full-swing (3.3V) CMOS signal with a fast 500 ps rise time next to a low-swing (300 mV) signal for a 10 cm run of microstrip line. The lines are each 8 mils wide spaced 6 mils above a ground plane and spaced 8 mils from one another (see D&P Table 6-3).Is the noise induced in the low-swing line a concern?
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7Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
aggressorxtalk fx x aggressor rx r
VV k t V k k
t∆
= × × + ∆ × ×∆
3.3 0.047 0.578 3.3 0.058 1 0.37 500
ns Vps
= × × + × × =
Victim line also produces crosstalk on the agressor. However, only second order effect is considered.
0.37 V is bigger than 300 mV/2=150 mV This will cause problem to the system
In worst case, near- and far-end crosstalk will be added add absolute values
Example (Dally & Poulton 6-5)
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8Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
VN- +RoVdd
+
-
50W, 6 ns
3.3 mA
50W, 6 ns +-RT
Transmission Systems
Full-swing CMOS transmission system
Low-swing current-mode transmission system
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9Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
Signaling Voltage mode: 0=GND, Current mode: 0=-3.3 mA1=Vdd 1=+3.3 mA
Reference Power supply: Vr~Vdd/2 Self-centered: Ir=0 mA
Termination Series terminated in output Parallel-terminated at receiverimpedance of driver with RT within 10% of Zo
Signal energy 1.3 nJ 22 pJ
Power dissipation 130 mW 11mW
Noise immunity 1.2:1 actual:required signal 3.6:1swing (with LSC receiver)
Delay 18 ns 6 ns
CMOS LSC
Transmission Systems
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10Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
VOH 0.3 165VOL 0.0 -165VIH 2.2 10VIL 1.1 -10VMH 1.1 155VML 1.1 155
CMOS LSC(V) (mV)
Receiver sensitivity 300 10Receiver offset 250 10Power supply noise 300 3Total noise (swing-independent) 850 23
CMOS LSC(mV) (mV)
Self-induced power supply noise (Kin) 10 0Crosstalk from other signals (Kxt) 250 10Reflections of the same signal large(>5) 5from previous clock cycles (Kr)Transmitter offset (Kto) 10 10Total proportional noise fraction (KN) >35 25
CMOS LSC(%) (%)
Transmission Systems
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11Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
• Basic CMOS system is most commonly used and yet is far from optimal
• Large energy signal is used where it is not needed
• Transmitted signal not isolated from supply noise
• Receiver uses reference that changes significantly with process variations
CMOS vs LSC
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12Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
+-
RT
ZGRZRR
ZORO
VT
ZGT
ZRT
VN
VR
Vr
TGND RGND
Signaling Modes for Transmission Lines
- Signal return impedances ZRT and ZRR- Coupling to local power supply ZGT and ZGR- Introduce noise VN- Sections can be separated if TL is terminated into match impedance
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13Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
• Output impedance, Ro
• Coupling between signal and power supply
• Polarity of signal
• Amplitude of signal
Transmitter Signaling Parameters
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14Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
ZO
VT
ZRT
TGND
ZO
IT
ZGT
ZRT
TGND
Provides isolation of both the signal and current return from the local power supplies
- Large ZGT
Makes a difference in:- Signal return crosstalk- Single power supply noise
Current- & Voltage-Mode Transmission
Current-Mode Transmission Voltage-Mode Transmission
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15Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
• A nonideal return path will appear as an inductive discontinuity
• A nonideal return path will slow the edge rate by filtering out high-frequency components
• If the current divergence path is long enough, a nonideal return path will cause signal integrity problems at the receiver
• Nonideal return paths will increase current loop area and exacerbate EMI
• Nonideal return paths may significantly increase the coupling coefficient between signals
Nonideal Return Paths
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16Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
• Return crosstalk can be reduced with rise-time control
• As rise times get faster, every signal requires its own return might as well use differential signaling
• With voltage-mode signaling, the transmitter signal return crosstalk is a maximum
• High output impedance offers advantage and reduces transmitter return crosstalk
• For current-mode signaling, this form of crosstalk is completely eliminated
Signal Return Crosstalk
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17Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
ZO
ROZRT
ZO
RO
VT1 VT2 VTN
ZO
RO
+
-VL
( )( )1 1
RT O OO OX RT
RT O O
Z R ZR ZZ ZN N Z R Z
++ = = − − + + P
( )1 1 1X RT
X T TO O RT O O
Z ZI I IR Z N Z R Z
= = + − + +
( )1 1RT
X X O TRT O O
ZV I Z VN Z R Z
= = − + +
( )( )
( )1
1 1( 1)1
RT RTXXRT
T RT O O O O
N Z N ZN VKV N Z R Z R Z
− −−= = ≤
− + + +
Transmitter Signal Return Crosstalk
- With voltage-mode signaling, Ro=0, the transmitter signal return crosstalk is a maximum. For curr ent-mode signaling, Ro is infinite and this form of crosstalk is eliminated
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18Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
Voltage-mode signaling with Zo=50 Ω and rise time tr=2 ns and ZRTdominated by 5 nH inductance.
Approximate ZRT=L/tr= 2.5 ΩWant kXRT = 0.1
Solving for N shows that we will need 1 return for every 3 signal traces to meet the spec.
If the rise time is decreased to 1 ns, we will need 1 return for every 2 signal line to keep the same spec
If the rise time is lower than 1 ns, we will need 1 return for every signal might as well use differential signaling
Application: Return Signal Optimization
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19Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
Line impedance: Zo = 50 ΩSource Resistance: Ro= 50 ΩLead Inductance: L = 5 nHPin count: P = 32Data rate: TBR = 8GB/s
S+N=PS*B=TBR
Application: (D&P 7-2)
( )1 RTXRT
O O
N ZK
R Z−
≤+
ZRT is due to the lead inductanceZRT ZRT/N since there are N ground pinsNeed to determine S and N
B: Bit rate per signal pinTBR: Total bit rateS: Number of signal pinsN: Number of return pins
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20Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
P S GP S G P SG G P S G P S GG PP S S P S GG P
SG S S S S S S S P
S S GG S S P S S P S S G
GG S P S S P S G S P S G S P S G
inferior
improved
More improved
Optimal
8-Bit Connector Pin-Out Options
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21Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
• Minimize physical length of connector pins.
• Maximize the ratio of power and ground pins to the signal pins. If possible these ratios should be < 1.
• Place each signal pin as close as possible to a current return pin.
• Place power pins adjacent to ground pins.
Connector Design
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22Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
( )1( 1)( 1) 2 2
RRRRXRR
RR O O
N ZN ZKN Z Z Z
−−= ≤
− +
Receiver Signal Return Crosstalk
- All N terminators return their current through ZRR (shared impedance)
- No crosstalk advantage to current-mode signaling
- TL is like a matched source
ZO
RT
ZRRZO
2Vi1
ZO
+
-VR
2Vi2 2ViN
RT RT
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23Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
Vih
Vil
Threshold
(waveform into reference load)
(waveform at receiver)
Maximum flight time measuredat last crossing of Vih or Vil
Time
Ringback and Rise Time Control
• Violation into threshold region• Detrimental even if threshold is not crossed• Can exacerbate ISI• Can be aggravated by nonlinear (time varying) terminations • Can increase skew between signals
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24Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
VR
+
-
CLVT(t)
RO LP
i
( ) 1 exp cos( )2R
RTV t tL
ω = − −
212R
LC Lω = −
1 LQR Cπ
=
Signaling Over Lumped RLC Interconnect
Q: high
Q: medium
Q: low
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25Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
RT
ZO
RO
VN CN
LR
+-
Example (Dally & Poulton 7-4)
Determine the amount of supply noise VN that appears across RT as a function of frequency. How much signal swing is required to keep the power-supply noise less than 10% of the signal swing across the spectrum from DC to 1GHz
ZO=RT=50ΩRO=1 kΩCN=5 pF
LR=5 nHVN=500 mV
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26Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
( )( )( ) 12 2N O R
RN
O R O R
V Z j LV
Z j L Z j L j Cω
ω ω ω −=+ +
2 2
2 2
4 8 2 2
N O R
O R O R
V Z L CfZ L Cf Z fL
ππ π
=+ +
18 2
18 2 9
2.5 10 98.5 10 100 31.4 10
ff j f
−
− −
− ×=− × + + ×
ZO
RTLR
CN
VN
+-
-
VRN
+
Example (7-4) – Solution
We want 0.1 Vs > VRN VS > 10VRN
![Page 27: ECE 497 JS Lecture - 22 Timing & Signalingjsa.ece.illinois.edu/ece497js/Lect_22.pdfECE 497-JS, Spring 2004 Copyright © by Jose E. Schutt-Aine , All Rights Reserved 4 Chip 15 ×15](https://reader031.vdocuments.site/reader031/viewer/2022022807/5ce2c80a88c99364268c48c4/html5/thumbnails/27.jpg)
27Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
10 2 3 4 5 6 7 8 9 10
X 108 f (Hz)
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0
|VS| (Volts)
Required Voltage Swing
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28Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
• Power supply effects (SSN, ground bounce, rail collapse)• Noise from IC• Receiver transistor mismatches• Return path discontinuities • Coupling to reference voltage circuitry
Voltage Reference Uncertainty
Threshold region
Vref + uncertainty
Vref - uncertainty
Time
Threshold
Vih
Vil
Major Contributors
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29Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
Spreadsheets & metrics
Signal categories
Topology options
Sensitivity analysis
Reference design
Simulation of design
Design check
Tapeout
Buffer guidelinesRouting guidelines
Pass Fail
Fix
Efficient Bus Design Methodology
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30Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004
• I/O capacitance
• Trace length, velocity, and impedance
• Interlayer impedance variations
• Buffer strengths and edge rates
• Termination values
• Receiver setup and hold times
• Interconnect skew specifications
• Package, daughtercard, and parameters
Bus System Variables