ece 477 design review team 2 fall 2011 members: bo yuan, yimin xiao, yang yang, jintao zhang

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ECE 477 DESIGN REVIEW TEAM 2 FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

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Page 1: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

ECE 477 DESIGN REVIEW TEAM 2 FALL 2011

Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Page 2: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Outline

Project overview Project-specific success criteria Block diagram Component selection rationale Packaging design Schematic and theory of operation PCB layout Software design/development status Project completion timeline Questions / discussion

Page 3: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Project Overview

The project we propose is a digital oscilloscope with playback function that provides almost any function of a typical oscilloscope, such as digital sampling, signal processing, scaling, cursor setting, reconstruction and visualization of signals. Additional features such as recording and replicating signals as a function generator, and write data to external storage (SD card).

Page 4: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Project-Specific Success Criteria An ability to sample analog voltage

signal range from -12 V to 12 V via BNC; An ability to reconstruct and display the

sampled signal on VGA display; An ability to create user interface and

realize basic signal measurements, such as frequency and peak-to-peak voltage;

An ability to store/load the sampled signal to/from external memory;

An ability to replay a stored signal.

Page 5: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Block Diagram

Page 6: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Block Diagram, System Level

Page 7: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Component Selection Rationale Power Supply:

Using a standard 20 pin-Computer power supply unit. (Easy to use)

Use linear transistor 7805/7905/78M33 to provide low noise signal. Although 5V and 3.3V are available from the power supply, but along with a ripple voltage at 300mV. No significant current will be drawn from +/-5V line, large ripple voltage will be used in driving the analog MUX (+/-12V) and FPGA module (+5V), which has its own on board linear power supply system.

Using a 3V voltage reference for A/D conversion reference.

Page 8: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Component Selection Rationale Analog circuit:

MAX14752: Analog MUX Advantage:

Large tolerance (VSS-2 to VDD+2) compare to ADG1414 (VSS-0.3 to VDD+0.3).

Easy to control: Serial bus control, no SPI line require. Got free sample from MAXIM, ADG1414 cost 8 dollar a

piece. Disadvantage:

High On-Resistance: 60 Ohm and ADG1414 is only 9.5 Ohm (Typ.).

More Pins to MCU: Each require four lines to controller, but ADG1414 is SPI shift register which can be implemented serially.

Page 9: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Component Selection Rationale

INA118: Instrumentation Amplifier Advantage: low distortion, high tolerance (+/-

40V), voltage shift up by Vref(1.5V).

LF411: Output driver op-amp: Advantage: Low offset, low distortion, high

power (capable to drive coaxial wires)

Page 10: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Component Selection Rationale Digital Circuit:

MCU – STM32F407VG Sampling rate 2.4 MHz maximum. Relatively large RAM size (192 KB).

Crystal Clock: 26MHz Crystal: Allowed maximum external clock. ARM

Cortex-M4 will use an internal PLL to generate higher frequency clock up to 168MHz. Secondary clock (32.768KHz) is also laid out on board in case for need of precise clocking.

FPGA – Spartan 3E VGA support. Older version of the Spartan series, avoid voltage

conversion.

Page 11: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Packaging Design

Page 12: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Schematic/Theory of OperationAnalog Input/ Output

Page 13: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Schematic/Theory of OperationMicroprocessor

Page 14: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Schematic/Theory of OperationDisplay Unit

Page 15: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Schematic/Theory of OperationUser Interface

Page 16: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

PCB Layout: General Layout

Page 17: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

PCB Layout: Through Hole/Via

Page 18: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

PCB Layout: Top Copper

Page 19: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

PCB Layout: Bottom Copper

Page 20: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Software Design/Development Status

Page 21: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Software DesignDevelopment StatusBlock Progress

Timer Config Done

I2C Master Config Done

I2C Slave Config In progress

ADC Config Done with one channel

GPIOs In progress

Subroutines Not started

DAC Not started

USB Done with config

VGA display Not started

Page 22: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

Project Completion Timeline

Page 23: ECE 477 DESIGN REVIEW TEAM 2  FALL 2011 Members: Bo Yuan, Yimin Xiao, Yang Yang, Jintao Zhang

QUESTIONS / DISCUSSION