ece 171 digital circuits chapter 6 logic circuits herbert g. mayer, psu status 1/16/2016 copied with...
DESCRIPTION
Lecture 6 Topics –Combinational Logic Circuits Graphic Symbols (IEEE and IEC) Switching Circuits Analyzing IC Logic Circuits Designing IC Logic Circuits Detailed Schematic Diagrams Using Equivalent Symbols 3TRANSCRIPT
![Page 1: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/1.jpg)
ECE 171Digital Circuits
Chapter 6Logic Circuits
Herbert G. Mayer, PSUStatus 1/16/2016
Copied with Permission from prof. Mark Faust @ PSU ECE
![Page 2: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/2.jpg)
Syllabus
Combinatorial Logic Circuits Truth Tables Logic Functions References
![Page 3: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/3.jpg)
Lecture 6
• Topics– Combinational Logic Circuits
• Graphic Symbols (IEEE and IEC)• Switching Circuits• Analyzing IC Logic Circuits• Designing IC Logic Circuits• Detailed Schematic Diagrams• Using Equivalent Symbols
3
![Page 4: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/4.jpg)
Combinational Logic Circuits
• Combinational Logic– Outputs depend only upon the current inputs (not
previous “state”)• Positive Logic
– High voltage (H) represents logic 1 (“True”)– “Signal BusGrant is asserted High”
• Negative Logic– Low voltage (L) represents logic 1 (“True”)– “Signal BusRequest# is asserted Low”
4
![Page 5: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/5.jpg)
IEEE: Institute of Electricaland Electronics Engineers
IEC: International Electro-technical Commission
5
![Page 6: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/6.jpg)
n.o. = normally openn.c. = normally closed
6
![Page 7: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/7.jpg)
7
![Page 8: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/8.jpg)
8
![Page 9: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/9.jpg)
9
![Page 10: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/10.jpg)
10
![Page 11: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/11.jpg)
11
![Page 12: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/12.jpg)
12
![Page 13: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/13.jpg)
13
![Page 14: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/14.jpg)
All Possible Two Variable FunctionsQuestion: How many unique functions of twovariables are there?
Recall earlier question…
14
![Page 15: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/15.jpg)
Truth Tables
B5 B4 B3 B2 B1 B0 F
0 0 0 0 0 0 0
0 0 0 0 0 1 1
0 0 0 0 1 0 1
0 0 0 0 1 1 0
.
.
.
1 1 1 1 1 1 1
0
1
2
3
.
.
.
63
26 = 64
Question: How many rows are there in a truth tablefor n variables?As many rows as unique combinationsof inputs
Enumerate by counting in binary
2n
15
![Page 16: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/16.jpg)
Two Variable FunctionsQuestion: How many unique combinations of 2n bits?
Enumerate by counting in binary
22n
264
16
B5 B4 B3 B2 B1 B0 F
0 0 0 0 0 0 0
0 0 0 0 0 1 1
0 0 0 0 1 0 1
0 0 0 0 1 1 0
.
.
.
1 1 1 1 1 1 1
0
1
2
3
.
.
.
63
26 = 64
![Page 17: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/17.jpg)
All Possible Two Variable FunctionsQuestion: How many unique functions of twovariables are there? B1 B0 F
0 0 0
0 1 1
1 0 1
1 1 0
22 = 4 rows 4 bits
Number of unique 4 bit words = 24 = 16
17
![Page 18: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/18.jpg)
18
![Page 19: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/19.jpg)
Analyzing Logic Circuits
Reference Designators (“Instances”)
X + Z
XX + Y
(X + Y)×(X + Z)
19
![Page 20: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/20.jpg)
Analyzing Logic Circuits
C
A×B
B×C
A×B + B×C
20
![Page 21: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/21.jpg)
Designing Logic Circuits
F1 = A×B×C + B×C + A×B
SOP form with 3 terms 3 input OR gate
21
![Page 22: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/22.jpg)
Designing Logic Circuits
F1 = A×B×C + B×C + A×B
Complement already available
22
![Page 23: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/23.jpg)
Some Terminology
F1 = A×B×C + B×C + A×BSignal line – any “wire” to a gate input or output
23
![Page 24: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/24.jpg)
Some Terminology
F1 = A×B×C + B×C + A×BNet – collection of signal lines which are connected
24
![Page 25: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/25.jpg)
Some Terminology
F1 = A×B×C + B×C + A×BFan-out – Number of inputs an IC output is driving
Fan-out of 2
25
![Page 26: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/26.jpg)
Some Terminology
F1 = A×B×C + B×C + A×BFan-in – Number of inputs to a gate
Fan-in of 3
26
![Page 27: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/27.jpg)
Vertical Layout Scheme – SOP Form
27
![Page 28: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/28.jpg)
Vertical Layout Scheme – SOP Form
28
![Page 29: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/29.jpg)
>2 Input OR Gates Not Available for all IC Technologies
Solution: “Cascading” gates
29
![Page 30: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/30.jpg)
Vertical Layout Scheme – POS Form
F2 = (X+Y)×(X+Y)×(X+Z)
30
![Page 31: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/31.jpg)
Designing Using DeMorgan Equivalents
• Often prefer NAND/NOR to AND/OR when using real ICs– NAND/NOR typically have more fan-in– NAND/NOR “functionally complete”– NAND/NOR usually faster than AND/OR
31
![Page 32: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/32.jpg)
AND/OR forms of NAND
DeMorgan’s Theorem
32
![Page 33: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/33.jpg)
Summary of AND/OR forms
Change OR to AND“Complement” bubbles
33
![Page 34: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/34.jpg)
Equivalent Signal Lines
34
![Page 35: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/35.jpg)
NAND/NAND Example
35
![Page 36: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/36.jpg)
NOR/NOR Example
36
![Page 37: ECE 171 Digital Circuits Chapter 6 Logic Circuits Herbert G. Mayer, PSU Status 1/16/2016 Copied with Permission from prof. Mark PSU ECE](https://reader031.vdocuments.site/reader031/viewer/2022020921/5a4d1b0a7f8b9ab05998a15f/html5/thumbnails/37.jpg)
37