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LESSON PLANLP – EC2354LP Rev. No: 01Date: 15/12/11Page 01 of 06

Sub Code/Name: EC2354-VLSI DESIGN Unit : I Branch : EC Semester: VI

UNIT I CMOS TECHNOLOGY 9

Syllabus:

A brief History-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non ideal I-V effects, DC transfer characteristics - CMOS technologies, Layout design Rules, CMOS process enhancements, Technology related CAD issues, Manufacturing issues.

Session No. Topics to be covered

Time Page No

Ref Teaching Method

1. Introduction –VLSI Design 50m 1-4 1 BB

2. NMOS, PMOS Enhancement transistor 50m 5-7,40 1 BB

3. MOS transistor-Ideal I-V characteristics 50m 42-45 1 BB4. MOS transistor-C-V characteristics 50m 45-51 1 BB5. Non ideal I-V characteristics- velocity saturation

and mobility degradation, channel length modulation, sub threshold conduction, Body effect

50m 51-55 1 BB

6. Threshold voltage, Junction leakage, Tunneling, temperature dependence, Geometry dependence

50m 55-60 1 BB

7. CMOS inverter DC characteristics, Beta ratio effects

100m 60-65 1 BB

9. CMOS technology : nwell, P well Twin well, triple well,

50m 83,15-21

1,3 BB, OHP

10. Layout design rules-NAND,NOR gate 50m 83-91 1 BB,OHP11. CMOS Process enhancement-SOI Process,

Interconnects, circuit elements: Resistors 50m 91-100 1 BB

12. Circuit element: capacitor, CAD and manufacturing issues

50m 107-109,149

1,2 BB

13. Tutorial 50m - 1,3 BBCAT-I 50m - - -

Objective: To understand the MOS transistor theory, CMOS technologies and the Layout

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LESSON PLANLP – EC2354 LPRev. No: 01Date: 15/12/11Page 02 of 06

Sub Code/Name: EC2354-VLSI DESIGN Unit : II Branch : EC Semester: VI

UNIT II CIRCUIT CHARACTERIZATION AND SIMULATION 9

Syllabus:

Delay estimation, Logical effort and Transistor sizing, Power dissipation, Interconnect, Design margin, Reliability, Scaling- SPICE tutorial, Device models, Device characterization, Circuit characterization, Interconnect simulation.

Objective:

To study the circuit characterization and performance estimation of CMOS technology .

Session No.

Topics to be covered Time Page No

Ref Teaching Method

14. Delay estimation-RC delay model, Linear delay model

50m 111-117,245

1,2 BB

15. Logical effort ,Transistor sizing 50m 118,313 1,2 BB16. Power dissipation-static and dynamic power 50m 129-135 1 BB17. Interconnect –Estimation of resistance

capacitance, delay 50m 142-

148,5251,2 BB

18. cross talk delay effects,Design margin 50m 145-148 1 BB19. Reliability 50m 148-159 1 BB

20. Scaling, SPICE tutorial 50m 159,229 1,2 BB21. SPICE tutorial, Device models 50m 181-193 1 BB22. Device& Circuit characterization

50m 193 -

2131 BB,OHP

23. Interconnect simulation 50m 193 -213

1 BB,OHP

24. Tutorial 50m - 1,3 BB,OHP

CAT-II 50m - - -

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LESSON PLANLP – EC2354LP Rev. No: 01Date: 15/12/11Page 03 of 06

SubCode/Name EC2354 -VLSI DESIGN Unit : III Branch : EC Semester: VI

UNIT III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN 9

9

Syllabus:

Circuit families –Low power logic design – comparison of circuit families – Sequencing static circuits, circuit design of latches and flip flops, Static sequencing element methodology- sequencing dynamic circuits – synchronizers

Objective: To Understand the concepts of designing combinational and sequential circuit

using CMOS logic configuration

Session No.

Topics to be covered Time Page No

Ref Teaching Method

25. Circuit families-static CMOS,ratioed circuit 50m 215-224,342

1,2 BB

26. Cascode voltage swing logic,Dynamic circuits

50m 225,361,353

1,2,3 BB

27. Pass transistor,Differential circuits 50m 233-240 1 BB28. BiCMOS,Low power logic design –

comparison of circuit families50m 241-245 1 BB

29. Sequencing static circuits 50m 252-265 1 BB

30. Circuit design of latches and flip flops 100m 265-274 1 BB,OHP

32. Static sequencing element 50m 275-283 1 BB

33. Sequencing dynamic circuits 50m 284-289 1 BB

34. Synchronizers 50m 289-294 1 BB

CAT-III 50m - - -

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LESSON PLAN LP – EC2354LP Rev. No: 01Date: 15/12/11Page 04 of 06

Sub Code/Name: EC2354 -VLSI DESIGN

Unit : IV Branch : EC Semester: VI

UNIT IV CMOS TESTING 9

Syllabus:

Need for testing- Testers, Text fixtures and test programs- Logic verification- Silicon debug principles- Manufacturing test – Design for testability – Boundary scan.

Objective: To understand the concepts of CMOS testing

Session No.

Topics to be covered Time Page No Ref Teaching Method

35. Need for testing Text fixtures and test programs

50m 531-541 1 BB

36. Logic verification-- Silicondebug principle, Manufacturing test

50m 541-547 1 BB

37. Manufacturing test 50m 547-549,621,239

1,2,4 BB

38. Design for testability-adhoc tesing 50m 548-550 1 BB39. Scan design 100m 550-555 1 BB41. Built in self test, IDDQ testing 50m 555-558 1 BB

42. Boundary scan 100m 559-570 1 BBCAT-IV 75m - - -

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LESSON PLAN LP – EC2354LP Rev. No: 01Date: 15/12/11Page 05 of 06

SubCode/Name: EC2354 - VLSI DESIGN Unit : V Branch : EC Semester: VI

UNIT V SPECIFICATION USING VERILOG HDL 9

Syllabus:Basic concepts- identifiers- gate primitives, gate delays, operators, timing

controls,procedural assignments conditional statements, Data flow and RTL, structural gate

level,switch level modeling, Design hierarchies, Behavioral and RTL modeling, Test

benches,Structural gate level description of decoder, equality detector, comparator,

priorityencoder, half adder, full adder, Ripple carry adder, D latch and D flip flop.

Objective: To understand the concepts of modeling a digital system using Hardware

Description Language.

Session No.

Topics to be covered Time Page No Ref Teaching Method

44. Basic concepts- identifiers- gate primitives,, Design hierarchies

50m 47-48,72,106,388

8,2 BB

45. Gate delays 50m 121 8 BB46. Operators 50m 138 8 BB47.Chip Timing controls 50m 171-178 8 BB

48. Procedural assignments ,conditional statements

50m 166,179 8 BB

49. Data flow and RTL 50m 131 8 BB50. Structural gate level 50m 373 8 BB51. Switch level modeling 50m 383 8 BB52. Behavioral and RTL modeling, Test

benches50m 385 8 BB

53. Gate level verilog code-Decoder, equality detector, comparator, priorityencoder

50m 136 8 BB

54. Half adder, full adder, Ripple carry adder, D latch and D flip flop.

50m 452,414 2,4 BB

CAT-V 50m - - -

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LESSON PLAN LP – EC2354LP Rev. No: 01Date: 15/12/11Page 06 of 06

SubCode/Name: EC2354-VLSI DESIGN Branch : EC Semester: VI

Course Delivery Plan:

Week 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

I II I II I II I II I II I II I II I II I II I II I II I II I II I II I II

Units

1 1 1 1 1 1 12CAT1

2 2 2 2

2

CAT2

3 3 3 3 3

CAT3

4 4 4 4 45CAT4

5 5 5 5 5

CAT5

- - -

TEXT BOOKS:

1. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson Education, 20052. Uyemura J.P: Introduction to VLSI circuits and systems, Wiley 2002.

REFERENCES:

3. D.A Pucknell & K.Eshraghian Basic VLSI Design, Third edition, PHI, 20034. Wayne Wolf, Modern VLSI design, Pearson Education, 20035. M.J.S.Smith: Application specific integrated circuits, Pearson Education, 19976. J.Bhasker: Verilog HDL primer, BS publication,2001

7. Ciletti Advanced Digital Design with the Verilog HDL, Prentice Hall of India, 2003 8.Samir palnitkar, Verilog HDL , Pearson Education,second edition

Prepared by Approved byName M.ANUSHYA Prof.E.G .GovindanDesignation Asst- professor HOD, Department of ECDateSignature