ec2257 ec ii manual 1

EASWARI ENGINEERING COLLEGE, Chennai – 89

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG..

EC 2257 - ELECTRONICS CIRCUITS II AND SIMULATION LAB

(IV SEMESTER ECE A & B)

LAB MANUAL

PREPARED BY APPROVED BY

(HOD/ECE)

1

EC 2257 ELECTRONICS CIRCUITS II AND SIMULATION LAB 0 0 3 2

Design of following circuits

1. Series and Shunt feedback amplifiers:

Frequency response, Input and output impedance calculation

2. RC Phase shift oscillator, Wien Bridge Oscillator

3. Hartley Oscillator, Colpitts Oscillator

4. Tuned Class C Amplifier

5. Integrators, Differentiators, Clippers and Clampers

6. Astable, Monostable and Bistable multivibrators

SIMULATION USING PSPICE:

1. Differential amplifier

2. Active filters : Butterworth 2nd order LPF, HPF (Magnitude & Phase Response)

3. Astable, Monostable and Bistable multivibrator - Transistor bias

4. D/A and A/D converters (Successive approximation)

5. Analog multiplier

6. CMOS Inverter, NAND and NOR

2

EC1256 ELECTRONICS CIRCUITS II AND SIMULATION LAB 0 0 3 100

7. Series and Shunt feedback amplifiers:Frequency response, Input and output impedance calculation

8. Design of RC Phase shift oscillator: Design Wein Bridge Oscillator 9. Design of Hartley and Colpitts Oscilator 10. Tuned Class C11. Integrators, Differentiators, Clippers and Clampers12. Design of Astable and Monostable and Bistable multivibrators

SIMULATION USING PSPICE:

6. Differentiate amplifier7. Active filter : Butterworth IInd order LPF8. Astable, Monostable and Bistable multivibrator - Transistor bias 9. D/A and A/D converter (Successive approximation)10. Analog multiplier11. CMOS Inventor, NAND and NOR

3

EC 2257 - Electronics Circuits II And Simulation Lab

List Of Experiments

Cycle I

1. Feed Back Amplifiers (Series And Shunt)

2. Transistor RC Phase Shift Oscillator

3. Hartley Oscillator

4. Colpitts Oscillator

5. Single Tuned Amplifier

6. Integrators, Differentiators, Clippers And Clampers

7. Astable Multivibrator

Cycle II

8. Monostable Multivibrator

9. Bistable Multivibrator

10. Differential Amplifier

11. Active Filter : Butterworth II Order LPF

12. Astable, Monostable and– Transistor Bias

13. Free running Multivibrator

14. Analog Multiplier

15. CMOS Invertor

4

INDEX

SL NO.

DATE EXPERIMENT NAME

PAGE NO.

MARKS OBTAINED

FACULTY SIGNATURE

5

1. Feed Back Amplifiers

Aim:

To design and simulate(using pspice) the current series and voltage shunt feedback amplifiers and to calculate the following parameters with and without feedback.

1. Mid Band Gain.2. Bandwidth and Cutoff Frequencies.3. Input And Output Impedance

Apparatus Required:

S.No Item Range Q.Ty1 Transistor BC 107 12 Resistor 13 Capacitor

4 CRO (0-30) MHz 15 RPS (0-30) V 16 Function

Generator (0 – 1) MHz 1

7 Ammeters (0-5) mA (ac), (0-200) µA (ac) 1 each

Theory:

An amplifier whose function fraction of output is fed back to the input is called feed back amplifier. Depending upon whether the input is in phase or out of phase with the feed back signal, they are classified in to positive feed back and negative feed back. If the feed back signal is in phase with the input, then the wave will have positive gain. Then the amplifier is said to have a positive feed back. if the feed back signal is out of phase with the input ,then the wave will have a negative gain. The amplifier is said to have a negative feed back. The values of voltage gain and bandwidth without feed back.

Current Series Feedback Design:

Given data: VCC = , β = , f1 = , f2= ,

Ic = , hie=

6

IE = IC

Assume, VCE = VCC / 2 =

VE = VCC / 10 =

VB = VBE + VE =

RC = (VCC - VCE - VE)/ IC =

I2 = IC /10 =

VB = I2 * R2 =

R2 = VB / I2 =

R1 = (VCC - VB) / I2 =

Find

RB = R1R2 =

Input Impedance , Zi = ( RBhie ) =

Coupling and bypass capacitors can be thus found out.

Input coupling capacitor is given by

XCi= Z i / 10 =

7

XCi = 1/ 2fCi =

Ci = 1/ 2f XCi =

output coupling capacitor is given by ,

Xco=(Rc RL) / 10 =

XCo = 1/ 2 f Co =

Co = 1/ 2 f XCo =

By-pass capacitor is given by , XCE = 1/ 2fCE

CE = 1/ 2f XCE =

Design (With feedback):

Remove the emitter capacitance (CE)

β = -1 / RE =

Gm = - hfe/ [(hie + RE ) RB] =

D = 1+ β Gm =

Gmf = Gm / D =

8

Zif = Z iD =

Zof = ZoD =

Current Series Circuit Diagram:

+VCC

R1 RC Co

Cin + - B

- BC107

E RL

Vo

CE

Vin _ R2 RE f = 1 KHz

9

CRO

Observation: Without Feedback

Vi = (volts)

Frequency(Hz)

O/P voltage

Vo (volts)

Gain

Av=20 log (Vo/Vi)

(dB)

100

500

1 K

3 K

5 K

7 K

10 K

30 K

50 K

70 K

100 K

200 K

300 K

500 K

10

Observation: With Feedback

Vi = (volts)

Frequency(Hz)

O/P Voltage

Vo (volts)

Gain

Av=20 log Vo/Vi(dB)

100

500

1 K

3 K

5 K

7 K

10 K

30 K

50 K

70 K

100 K

200 K

300 K

500 K

11

Voltage Shunt Feedback Amplifier Design (With Feedback):

Connect the feedback resistance (Rf) and feedback capacitor (Cf) as shown

in the figure.

Assume, Rf = 68 K

XCf = Rf / 10 =

Cf = Rf / 2πf x 10 =

β = -1 / Rf =

Trans – resistance Rm = - hfe (RB| | Rf ) (RC| | Rf ) / (RB| | Rf ) + hie =

D = 1+ β Rm =

Avf = Rmf / Rs =

Rmf = Rm / D =

Zif = Zi / D =

Zof = Zo / D =

12

Voltage Shunt Feedback Circuit Diagram:

+VCC

R1 Rf Cf Rc Co

Cin B

BC107

E RL

Vo

CE

Vin R2 RE f = 1 KHz

13

CRO

Observation:

Without Feedback

Vin = ------------ Volts

Frequency(Hz)

O/P voltage

Vo (volts)

Gain

Av = 20log(Vo/Vi)(dB)

100

500

1 K

3 K

5 K

7 K

10 K

30 K

50 K

70 K

100 K

200 K

300 K

500 K

14

With Feedback:Vi = (volts)

Frequency(Hz)

O/P voltage(volts)

Av = 20log (Vo/Vi)(dB)

100

500

1 K

3 K

5 K

7 K

10 K

30 K

50 K

70 K

100 K

200 K

300 K

500 K

15

Model Graph (With & Without Feedback)

Without feedback 3 dB

gain (dB) 3dB With feedback

f3 f1 f2 f4 f(Hz)

f2 – f1 = Bandwidth without feedback circuit f4 – f3 = Bandwidth with feedback circuit

Procedure: The connections are made as shown in the circuit. The amplifier is checked for its correct operation .Set the input voltage to a fixed value. Keeping the input voltage Vary the input frequency from 0Hz to 1MHz and note down the corresponding output voltage. plot the graph : gain (dB) Vs frequency .Calculate the bandwidth from the graph. Remove RE and follow the same procedure.

Observation: Theoretical Practical

With F/B Without F/B With F/B Without F/B

Bandwidth(Hz)

Transconductance

(gm)

Result:Thus the feedback amplifier was designed, simulated (using pspice), constructed, tested and frequency response was plotted.

Bandwidth without feedback circuit = Bandwidth with feedback circuit =

16

2. Transistor RC Phase Shift Oscillator

Aim:To design, simulate(using pspice),construct and test the transistor RC Phase shift oscillator and to obtain its output waveform for the given frequency.

Apparatus Required:

S.No Apparatus Name Range Qty1 Transistor BC 107 12 Resistor3 Capacitor4 CRO ( 0 – 30 ) MHz 15 RPS (0-30) V 1

6FunctionGenerator

(0-1 )MHz 1

Design:

Given data : VCC = , β = , f1 = , f2= ,

IC= , hie= , RE=

IE = IC


VE = VCC/10 =

VB = VBE + VE =

RC = (VCC - VCE - VE) / IC =

17

I2 = IC /10 =

VB = I2 * R2 =

R2 = VB / I2 =

R1 = (VCC - VB) / I2 =

RC1 = RC2 =

Find

RB = R1R2 =

Input Impedance, Zi = (RBhie) =


Input coupling capacitor is given by,

XCi = Z i / 10 =

XCi = 1/ 2fCi =

Ci = 1/ 2f XCi =

Output coupling capacitor is given by,

XCo =(RcRL) / 10 =

18

XCo = 1/ 2fCo =

Co = 1/ 2f XCo =

By-pass capacitor is given by,

XCE = 1/ 2f CE =

CE = 1/ 2f XCE =

Oscillator Design

Frequency f = ____________Hz

With feedback:

f = 1/ 2π √6 RC

Assume, C = 0.1μF

R = 1/2π√6 fC

19

Circuit Diagram:

Model Graph:

Theory:

The Transistor Phase Shift Oscillator produces a sine wave of desired designed frequency. The RC combination will give a 60 phase shift totally three combination will give a 180 phase shift. . The BC107 is in the common emitter configuration. Therefore that will give a 180 phase shift totally a 360 phase shift output is produced. The capacitor value is designed in order to get the desired output frequency. Initially the C and R are

20

connected as a feedback with respect to input and output and this will maintain constant sine wave output. CRO is connected at the output.

Procedure:

1. The circuit is constructed as per the given circuit diagram.2. Switch on the power supply and observe the output on the CRO( sine wave)3. Note down the practical frequency and compare it with the theoretical frequency.

Observation:

Amplitude =_____________

Time period t = ____________

Frequency 1/T = ____________

Theoretical frequency fT =

Practical frequency fP =

Result:

Thus the RC Phase shift Oscillator designed, simulated (using pspice), constructed, tested and the output sine waveform is drawn

Theoretical frequency =

Practical frequency =

21

3. Hartley Oscillator

Aim :

To design, simulate(using pspice),construct and test the Hartley oscillator and to obtain its output waveform for the given frequency.

Apparatus Required:

S.No Apparatus Name Range Qty1 Transistor BC 107 12 Resistor 1

3 Capacitor4 CRO (0 – 30)MHZ 15 RPS (0-30) V 1

6 Function Generator

(0- 1 ) MHz 1

7 DLB, DRB 1

Theory:

LC oscillator consisting of a tank circuit for generating sine wave of required frequency. Rectifying Barkhausen criteria A for a circuit containing reactance A must be positive and greater than or equal to unity.

Design:


IC= , hie=

IE=IC

Assume, VCE = VCC/ 2 =

VE = VCC/10 =

22

VB = VBE + VE =


I2 = IC /10 =

VB = I2 * R2 =

R2 = VB / I2 =

R1 = (VCC - VB) / I2 =

R1 = R3 RC1 = RC2

Find

RB = R1 R2 =

Input Impedance, Zi = (RB hie) =



XCi = Z i / 10 =

XCi= 1/ 2fCi

Ci = 1/ 2f XCi =


23

XCO=(RCRL) / 10 =

XCO =1/ 2fCo

Co = 1/ 2f XCO =


XCE = 1/ 2fCE

CE = 1/ 2f XCE =

Hartley Oscillator Design


Assume, L1= L2=

C =

Circuit Diagram :

VCC

24

RB1 RC Co C Cin B BC107

E RL RB2

RE CE

+ L1 - - L2 +

C

Model Graph:

Procedure:

1. The circuit connection is made as per the circuit diagram. 2. Switch on the power supply and observe the output on the CRO (sine wave). 3. Note down the practical frequency and compare it with the theoretical frequency.

25

CRO

Observation:

Amplitude =_____________

Time period t = ____________

Frequency 1/T = ____________



Result:

Thus the Hartley Oscillator designed, simulated (using pspice), constructed, tested and the output sine waveform is drawn



4. Colpitts Oscillator

Aim :

To design, simulate(using pspice),construct and test the transistor colpitts oscillator and to obtain its output waveform for the given frequency.

26

Apparatus Required:


3 Capacitor4 CRO (0 – 30)MHZ 15 RPS (0-30) V 1

6 Function Generator

(0- 1 ) MHz 1

7 DLB, DRB 1

Theory:

LC oscillator consisting of a tank circuit for generating sine wave of required frequency. Rectifying Barkhausen criteria A for a circuit containing reactance A must be positive and greater than or equal to unity.

Design:


IC= , hie=

IE=IC

Assume, VCE = VCC/ 2 =

VE = VCC/10 =

VB = VBE + VE =


I2 = IC /10 =

27

VB = I2 * R2 =

R2 = VB / I2 =

R1 = (VCC - VB) / I2 =

R1 = R3 RC1 = RC2

Find

RB = R1 R2 =

Input Impedance, Zi = (RB hie) =



XCi = Z i / 10 =

XCi= 1/ 2fCi

Ci = 1/ 2f XCi =


XCO=(RCRL) / 10 =

28

XCO =1/ 2fCo

Co = 1/ 2f XCO =


XCE = 1/ 2fCE

CE = 1/ 2f XCE =

Colpitts Oscillator Design:


f = 1/ 2 π √ LC

C1 = C2 =

C = C1+C2

L =

Circuit Diagram:

+VCC

29

RB1 RC

0 .01F Cin C

BBC107

RL

E

RE CE

RB2

C1 C2

L

Model Graph:

Observation:

Amplitude =_____________

Time period t = ____________

Frequency 1/T = ____________

30

CRO



Result:

Thus the Colpitts Oscillator designed, simulated (using pspice), constructed, tested and the output sine waveform is drawn



31

5. Single Tuned Amplifier

Aim:

To design, simulate(using pspice),construct and test the operation of class c tuned amplifier and to obtain its frequency response.

Apparatus Required:


3 Capacitor21

4 CRO - 15 RPS (0-30) V 1

6FunctionGenerator

- 1

Theory:

The amplifier is said to be class c amplifier if the Q Point and the input signal are selected such that the output signal is obtained for less than a half cycle, for a full input cycle Due to such a selection of the Q point, transistor remains active for less than a half cycle .Hence only that much Part is reproduced at the output for remaining cycle of the input cycle the transistor remains cut off and no signal is produced at the output .the totalAngle during which current flows is less than 180 ..This angle is called the conduction angle, Qc.

Design:

Given data : VCC = , β = , f = IC = , hie =

IE = IC


VE = VCC/10 =

32

VB = VBE + VE =

I2 = IC /10 =

VB = I2 * R2 =

R2 = VB / I2 =

R1 = (VCC - VB) / I2 =

f = 1/2π√ LC

C =

L = 1/ (4 π2 f2C)

Input Impedance, Zi = ( RB hie )


Input coupling capacitor is given by ,

XCi = Z i / 10 =

XCi = 1/ 2fCi

Ci = 1/ 2f XCi =


XCO = (RCRL) / 10 =

XCO = 1/ 2fCo

Co = 1/ 2f XCO =

33


XCE = hie / ( 1 + β) =

CE = 1 / 2f XC =

Model Graph:

Circuit Diagram

-

0 . 0 1 u F

2 . 2 K+

B C 1 0 7

-1 0 0 u F

-

0 . 0 7 u f

+

L 1

1 0 u H

1

2

A F O

V C C 2 0 V

1 5 k

C R O

+1 . 3 7 K

-

1 k

0 . 0 1 u F

+

Procedure:1.The connections are given as per the circuit diagram.2.Connect the CRO in the output and trace the waveform.

34

3.Calculate the practical frequency and compare with the theoretical frequency4.Plot the waveform obtained and calculate the bandwidth

Observation:

Vin = ------------ Volts

Frequency(Hz)

O/P Voltage

Vo (volts)

Gain

Av =20 log (Vo/Vi) (dB)

100

500

1 K

3 K

5 K

7 K

10 K

30 K

50 K

70 K

100 K

200 K

300 K

500 K

Bandwidth = f 2

–f 1

35

Result:Thus the class c single tuned amplifier is designed, simulated (using pspice),

constructed, tested and the frequency response is plotted.

Theoretical bandwidth =

Practical bandwidth =

36

6. Integrator, Differentiator, Clippers and Clampers.

Aim:

To simulate(using pspice),construct and verify the operation of Integrator, Differentiator, Clippers and Clampers.

Apparatus Required:

Apparatus Name Range Quantity

Audio OscillatorCROResistorsCapacitorBreadboardRPS

11111

Theory:

Integrator and differentiator:

A simple low pas RC circuit can also work as an integrator when time constant is very large. This requires very large values of R and C.The components R and C cannot be made infinitely large because of practical limitations. However in the op-amp integrator by MILLER’s theorem, the effective input capacitance becomes Cf (1-Av), where Av is the gain of the op-amp. The gain Av is the infinite for an ideal op-amp, so the effective time constant of the opamp integrator becomes very large which results perfect integration.

Clipper and Clamper:

Clipping circuit clips off or removes a portion of input voltage. The circuits will allow voltages which are above or below certain voltage level to pass through them.These are also called as voltage limiters.

Clamping circuits are used to shift the base of the input waveform.1.Series Positive Clipper: During the positive half of the input diode is reverse biased. Hence it clips off the input and during the negative half of the input , it is forward biased and will allow the waveform to appear at the output.2. Series Negative Clipper: This circuit works exactly in the opposite way to the above.3.Negative Clamper (Output Voltage = Vin-Vc) : When the input is positive maximum, capacitor is fully charged and diode is switched on. The circuit is shorted resulting in no

37

output. During the next quarter of the positive half cycle, the diode is switched switch off, as Vin < Vc i.e., Vm. So Vm output is negative. Va = -Vm – Vm = - 2Vm. During the next quarter of negative half cycle, the output reaches –Vm.

Circuit Diagrams

IntegratorR 1K

0.1F5V 1KHz V0

Differentiator 0.1 F

Vo

R 1K

38

5V 1KHz

Clippers

Series Negative Clipper Series Positive Clipper

D

CRO

V 7V in

12

1 k

Clampers

Negative Clamper Positive Clamper.

Procedure:

1.Connections are given as per the circuit diagram. 2.The resistance Rcomp is also connected to the (+) input terminal to minimize the effect of the input bias circuit.3.It is noted that the gain of the integrator decreases with increasing frequency. 4.Thus the integrator circuit does not have any high frequency problem.

VinCRO

D6

12

0.1 µ F

VinCRO

D612

0.1 µ F

39

CRO

D 11 2

V 7V in

1 k

Observation

Result :

Thus the integrator, differentiator, clipper and clamper circuits are constructed, simulated (using pspice) and tested.

40

7.Astable Multivibrator

Aim :To design, simulate(using pspice),construct and test an astable multivibrator for the

given frequency and to obtain its output waveforms.

Apparatus Required :

S.No Item Range Qty1 Transistor BC107 22 Resistor 2

2

3 Capacitor 2

4 RPS (0-30) V 15 CRO - 1

Theory :Astable multivibrator has no stable state, but has two quasi – stable states. The

circuit oscillates between the states (Q1 ON , Q2 OFF) and (Q2 ON , Q! OFF). The output at the collector of each transistor is a square wave. Therefore this circuit is applied as a square wave generator. Refer to the fig each transistor has a bias resistance RB and each base is capacitor coupled to the collector of other transistor. When Q1 is ON and Q2 is OFF, C1 is charged to ( Vcc – VBE1) positive on the right side. For Q2 ON and Q! OFF, C2 is charged to (Vcc – VBE2) positive on the left side.

Design

Given VCC = ; IC = ; h FE = ; f =

R h FE RC

RC = VCC – VC2(sat) / IC

41

R =

T = 1.38 RC =

C =

Circuit Diagram:

+VCC

RC R R RC

C C

C C B B

VC1 BC107 BC107 VC2

E E

Procedure:

1. The connections are given as per the circuit diagram. 2. Switch on the power supply.3. Observe the waveform both at bases and collectors of Q1 and Q2.4. Connect the CRO in the output of Q1 and Q2 and trace the square waveform.

Waveforms :

42

Result: Thus the Astable multivibrator circuit is designed, simulated (using

pspice), constructed, tested and the output waveforms are drawn



43

8. Monostable Multivibrator

Aim:

To design, simulate(using pspice),construct and test an monostable multivibrator for the given frequency and to obtain its output waveforms.

Apparatus Required:

S.No Item Range Qty1 Resistor 1

2Capacitor 1

13 RPS (0-30) V 14 CRO - 1

Theory: A monostable multivibrator has one stable state and a quasistable state. When it is triggered by an external agency it switches from the stable state to quasistable state and returns back to stable state. The time during which it states in quasistable state is determined from the time constant RC. When it is triggered by a continuous pulse it generates a square wave. Monostable multi vibrator can be realized by a pair of regeneratively coupled active devices, resistance devices and op-amps.

Design :

Given VCC = ; VBB = ; Ic = ; VCE(sat) = ; h FE =

f =

RC = VCC – VCE(sat) / IC =

IB2(min) = IC2 / hfe =

Select IB2 > IB1(min) (say 25 A )

44

Then R = VCC – VBE(sat) / I B 2 =

T = 0.69 RC

C =

VB1 = VBB (R1 / R1 + R2) +VCE(sat) (R2 / R1+R2)

Since Q1 is off state, VB1 less than equal to 0.

Then VBB (R1 / R1 + R2 ) = VCE(sat) (R2 / R1+R2)

VBB R1 = VCE(sat) R2

2R1 = 0.2 R2

Assume R1 = 10 K.

Then R2 =

C1 =

Circuit Diagram :

45

+ VCC

RC R RC

R

C C C C B B

VC1 BC107 BC107 VC2

E E -VBB

Procedure:

1. Connect the circuit as per circuit diagram.

2. Switch on the regulated power supply and observe the output waveform at

the collector of Q1 and Q2 and plot it.

3. Trigger the monostable multivibrator with a pulse and observe the change in

waveform.

4. Plot the waveform and observe the changes before and after triggering the input

to the circuit.

46

Observation:

C (f) Theoritical (T=0.69 RC (ms)) Practical T(ms)

Result: Thus the Monostable multivibrator circuit is designed, simulated (using

pspice), constructed, tested and the output waveforms are drawn



47

9.Bistable Multivibrator

Aim: To simulate(using pspice) a bistable multi vibrator and study the performance.

Specifications:

Circuit Diagram :

+V

VCC112V

+

-VBB10

+V

VCC12V

D1IN4001

RC23.9k

RB746.66

RC13.9k

C21uF

R131.6k

R237.3k

C11uF

Q12N2222

Q22N2222

Result: Thus the Bistable multivibrator is simulated(using pspice) and its output waveform is observed.

48

10. Differential Amplifier

Aim:

To Simulate the differential amplifier circuit using PSPICE and study the waveform.

Specifications: The input voltage is 0.1v. The model parameters of the bipolar transistors are Bf = 50,RB = 70, RC = 40.

Circuit Diagram:

0

0

0

Q 1 A

R 1

1 . 5 k

R 2

1 0 K

R 3

1 0 K

R 4

1 5 0 K

R 5

1 5 0 K

R 6

1 . 5 K

R 7

2 0 K

V 1

Q 1 A

Q 1 A

Q 1 A Q 1 A

V 21 2 v

V 31 2 v

49

Program:

Vcc 1 0 12vVEE 0 3 12vVIN1 2 0 DC 0.25vRC1 11 3 10kRC2 11 5 10kRE1 4 12 150RE2 7 12 150RS1 1 2 1.5kRS2 6 0 1.5kRx 11 8 20k

Q1 3 2 4 QNQ2 5 6 7 QNQ3 12 8 9 QNQ4 9 9 10 QNQ5 8 9 10 QN

. TF V (3,5) VINEND

Result:Thus the differential amplifier is simulated(using pspice) and its output waveform is observed.

50

11. Active Butterworth II Order LPF

Aim:

To implement a active low pass Butterworth filter using PSPICE and study the waveform.

Apparatus Required:PC with PSPICE software

Circuit Diagram:

1 V A C 0 V D C V I N

V C C

V E E

0

0

0

0

0

u A 7 4 1

3

27

4

6

1

5+

-V

+V

-

O U T

O S 1

O S 2

R 1

1 k

1 K R 3

0 . 5 8 6 R F

1 K R 2

C 1

1 n

C 2

1 n1 2 V D C

1 2 V D C

Program:LOW PASS FILTERVCC 6 0 DC 12VVEE 0 7 DC 12V VIN 1 0 AC 1VR1 4 0 1KR2 1 2 1KR3 2 3 1KRF 4 5 0.586KC2 2 5 0.079 UFC3 3 0 0.079UFX1 4 3 6 7 5 UA 741.LIB NOB .LIB.AC DEC 10HZ 100HZ 1MEGHZ.PROBE.END

51

Result:

Thus the Active Butterworth filter (using pspice) and its output waveform isobserved.

52

12. Free Running Multivibrator

Aim:

To implement a Free running multivibrator using PSPICE and study the waveform.


Circuit Diagram:

+VCC

RC R R RC

C C

C C B B

VC1 BC107 BC107 VC2

E E

Program:

VCC 6 0 DC 12VVEE 0 7 DC 12VR1 1 0 100KR2 2 3 100K

53

R3 2 3 10KC1 3 0 0.1 UF IC = -5VXA1 1 3 6 7 2 UA741.LIB EVAL .LIB.TRANS 10US 4MS UIC .PROBE.END

Result:Thus the Free running multivibrator is simulated(using pspice) and its output waveform is observed.

54

13. Analog Multiplier

Aim:

To implement an Analog multiplier using PSPICE and to obtain its output.


Circuit Diagram:

0

0

0

0

0 0

0

U 2

A D 7 4 1

3

2

74

6

1

5+

-

V+

V-

O U T

O S 1

O S 2

R 1 7

1 k R 2 6

1 k

V 80 V

U 2

A D 7 4 1

3

2

74

6

1

5+

-

V+

V-

O U T

O S 1

O S 2

R 1 7

1 kV 8

0 V

U 2

A D 7 4 1

3

2

74

6

1

5+

-

V+

V-

O U T

O S 1

O S 2 D 1

1 N 4 3 7 6

1 2

R 2 6

1 k

U 2

A D 7 4 1

3

27

4

6

1

5+

-V

+V

-

O U T

O S 1

O S 2

R 2 7

1 k

Program:

V1 1 0 1VV2 4 0 1VR1 1 2 1KR2 4 5 1KR3 3 7 1KR4 6 7 1KR5 7 8 1K R6 10 0 1KD1 2 3 DAD2 5 6 DA

55

D3 8 9 DA.MODEL DA DX1 2 0 3 IOPX2 5 0 6 IOP X3 7 0 8 IOP X4 9 0 10 IOP.SUBCKT IOP M P V0RI M P 1GE V0 0 P M 2E5.ENDS.DC V1 -1 1 0.1.PROBE.END

Result:

Thus the analog multiplier is simulated(using pspice) and its output is observed.

56

14. A CMOS Inverter

Aim:

To implement a CMOS inverter using PSPICE


Circuit Diagram:

Program: VDD 2 0 5VVIN 1 0 DC 5V PULSE (0 5V 0 1NS 1NS 20US 40US)RL 3 0 100kM1 3 1 2 2 PMOD L=1U W= 20UM2 3 1 0 0 NMOD L=1U W= 5U

57

.TRAN 1US 80US

.TF V(3) VIN

.OP

.PLOT TRAN V(3) V(1)

.PROBE

Result:

Thus the CMOS inverter is simulated (using pspice) and its output is observed.

58

ec2257 ec ii manual 1

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