ec-ii manual original

8/13/2019 Ec-II Manual Original

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CURRENT SERIES FEEDBACK AMPLIFIER

AIM:

To design, construct and obtain the frequency response characteristics of current

series feedback amplifier.

APPARATUS REQUIRED:

1. Transistor BC107

2. esistors 1k!,".#k!,2.2k!,10k!

". Capacitors 10$f,10$f

%. &' (0)"0*+

. Cathode ray oscilloscope

-. unction generator

7. Bread board

/. Connecting ires

THEORY:

portion of the output signal is taken from the output of the amplifier and is combined

ith the normal input signal and thereby the feedback is accomplished. n current series

feedback, a 3oltage is de3eloped hich is proportional to the output current. This is called

current feedback e3enthough it is a 3oltage that subtracts from the input 3oltage. Because of the

series connection at the input and output, the input and output resistances get increased. This

type of amplifier is called transconductance amplifier. 4ne of the most common method of

applying the current series feedback is to place a resistor a beteen load of common emitter

amplifier and ground. s the common emitter amplifier has a high gain, this is most often used

ith series negati3e feedback so that it can afford to lose some gain.5hen a is properly bypassed ith a large capacitor Ce, the output 3oltage is +o and the

3oltage gain ithout feedback is . esistor a pro3ides d.c. bias stabili6ation, but no a.c.

feedback. 5hen the capacitor Ce is remo3ed, and a.c. 3oltage ill be de3eloped across a due to

emitter current floing through a and this current is approimately equal to the output collector

current., This 3oltage drop across a ill ser3e to decrease the input 3oltage beteen base and

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emitter. 'o that the output 3oltage ill decrease to +o. The gain of the amplifier ith negati3e

feedback is no f. t can be shon that the current series feedback increases the input

resistance but decreases the output resistance of a feedback amplifier by a factor equal to 1:;.

n large signal amplifier and electronic measuring instruments, the ma


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CIRCUIT DIAGRAM:

B C 1 0 7

1 0 K O h m s 3 . 9 K O h m s

1 K O h m s2 . 2 K O h m s

1 0 u F

1 0 u F

0 . 0 1 u F

0

+cc > 10+

.unction generator

(0 ) 2?*=6

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DESIGN PROCEDURE:

@i3en dataA

+CC> 103, +8>1910th 4 +CC> 1+

8> +89 8

et 8 > 1m

8> 1!

ocate the D point at approimately the middle of the dc load line. t

means that 0. +CCappears across the collector emitter terminal remaining

0.% +CCappears across the C.

C > % 8> %! > ".# !

; > 2#0, thE 0.01 ;F 8

E 0.01F 2#0 F ".#F10G"

thE 2.#!

et th> 1F2 9 (1:2*

et th> 1./ ! and 1 > 10 !

2 > 2.# !

Choose input coupling capacitor > 10$

4utput coupling capacitor > 100$

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TABULATION:

WITHOUT FEEDBACK:

Vin =

'.H4 requency in =I mplitude in +olts +oltage gain +oltage gain in dB

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WITH FEEDBACK:

Vin =


MODELGRAPH:

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RESULT:

Thus the frequency response characteristics of current series feedback amplifier ere

obtained.

Bandidth ith feedback >

Bandidth ithout feedback >

VOLTAGE SHUNT FEEDBACK AMPLIFIER

AIM:

To design, construct, obtain the frequency response characteristics of 3oltage shunt

feedback amplifier.

APPARATUS REQUIRED:

1. Transistor BC107

2. esistors %/./kJ,%kJ,-00kJ,1kJ,10kJ,%.7kJ,-/kJ

". Capacitors 0.%K,10 K,%7 K,0.%7 K

%. Cathode ay 4scilloscope

. unction generator

-. &' (0)"0*+

7. Bread board

/. Connecting ires

THEORY:

n large signal amplifiers and electronic measuring instruments, the ma


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3oltage 3ariations. To obtain the input circuit of the amplifier ithout feedback, e short the

output node i.e. make +o> 0. This places ffrom base to emitter of the transistor. To obtain the

output circuit, e short the input node i.e. make +i>0, thereby connecting f from collector to

emitter.

PROCEDURE:

1. The connections are made as per the circuit diagram.

2. By 3arying the frequency, the input and output 3oltages are noted ith supply

3oltage i.e. +cc>10+.

". This procedure is repeated for 3arious frequencies (ith feedback*. The graph is

plotted beteen the frequency in =6 and gain in db.

%. Then the feedback element i.e. feedback resistor and capacitor is remo3ed for

ithout feedback.

. The same procedure is repeated for ithout feedback, the graph is plotted beteen

the frequency and the gain in db.

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CIRCUIT DIAGRAM:

B C 1 0 7

1 0 K O h m s

4 K O h m s4 8 . 8 K O h m s

6 8 K O h m s

6 0 0 O h m s

1 K O h m s

0 . 0 1 u F

1 0 u F

0 . 4 u F

0 . 4 7 u F

4 . 7 K O h m s

0

.unction generator

+cc > 10+

(0 ) 2?*=6

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DESIGN PROCEDURE:

@i3en dataA +CC> 10+, C> 1m, '> -00!

> %.7 !, f > 0=6

8> C> 1m

+C8> +CC9 2 > 10 9 2 > +

+8 > 10M of +CC> 1+

+B> +8: +B8 > 1:0.7 > 1.7+

8 > +89 8> 1!

+oltage across 2 is +B.

+B> +CC. 2 9 (1:2*

ssume 2 > 10 !

1> %/./ !

C> (+CCN +C8N 8. 8* 9 C> % !

OC8 > 0.18

19 (PC8* > 0.18

C8> 19 (2QF0F0.1F10G"*

C8> "1./$ > %7 $

Choose nput coupling capacitor > 0.% $

4utput coupling capacitor > 10 $

Design !" ee#$%&':

f> 19 (2RC*

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C> 19 (F2FRF*

OC> 9 10 > -/F10G" 9 10 > -./ !

C> 19 (2 RF0F-./F10G"*

C> 0.%7 $

TABULATION:

WITHOUT FEEDBACK:

+in >


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WITH FEEDBACK:

Vin =


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MODELGRAPH:

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RESULT:

Thus the frequency response characteristics of 3oltage shunt feedback amplifier ere

obtained.

Bandidth ith feedback >

Bandidth ithout feedback >

RC PHASE SHIFT OSCILLATOR

AIM:

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To design, construct and test the performance of C phase shift oscillator.

APPARATUS REQUIRED:

1. Transistor BC107

2. Capacitor 0.01$f, 10$f, %7$f

". esistors 10, -.!, -0!, 0!, 2.%!

%. Cathode ay 4scilloscope

. egulated &oer 'upply ( 0 N "0 *+

-. Bread board

7. Connecting ires

THEORY:

ny circuit hich is used to generate a.c 3oltage ithout a.c input signal is called an

oscillator. ll the oscillators using tuned C circuits operate ell at high frequencies. t lo

frequencies as the inductors and capacitors required for the time circuit ould be 3ery bulky,

C oscillators are found to be more suitable. n this oscillator the required phase shift is 1/0S

in the feedback lop from output to input is obtained by using and C Components instead of

tank circuit.

=ere a common emitter amplifier is folloed by three sections of C phase shift

netork, the output of the last section being returned to the input. n practice the 3alue of is

ad


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PROCEDURE:


2. 'et the supply 3oltage +cc>:12+

". By ad


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B C 1 0 7

2 . 4 K O h m s

5 6 0 O h m s

6 . 5 K O h m s6 . 5 K O h m s 6 . 5 K O h m s 1 0 K O h m s

5 0 K O h m s

1 0 u F0 . 0 1 u F0 . 0 1 u F0 . 0 1 u F

1 0 u F

4 7 u F

0

+12V

DESIGN PROCEDURE:

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+CC> 12+, c > 2m , ; > 100

B> C9 ;

B> 2.02m

+C8> +CC9 2

+C8> -+

+B8> 10M of +CC> 1.2+

+B> +8 : +B8> 1.2 : 0.7 > 1.#+

8 > +89 8> 1.2 9 (2.02F10G)"* > #%! > -% !

2 > +B9 (10F B* > #. ! > 10 !

1 > +CC9 (10F B*U N 2> 0. ! > 1 !

C > (+CCN +C8N 88* 9 C> 2.% !

OC8must be equal to one tenth of 3alue of 8at the loest operating frequency.

OC8> 8 9 10 > #.%

19(P C8* > #.%

19(2Qf C8* > #.%

19 (2QF0F C8* > #.%

C8> -$ > %7$

Choose coupling capacitor > 10$

Design !" ee#$%&':

requency f > 19(2QCV-*

et f > 1=I and C > 0.01$

>W > -. !

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RESULT:

Thus the C phase shift oscillator as constructed and designed and the

performance as 3erified.

Lesigned frequency > 1 =6 4btained frequency > 1 =6

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WEIN BRIDGE OSCILLATOR

AIM:

To design and measure the frequency of oscillation of the 5ein bridge oscillatorusing 4p)amp.

APPARATUS REQUIRED:

1. 4p)amp C 7%1

2. esistors 2.2!, 10!,22!

". Capacitors 0.1$f,0.01$f

%. &' ( 0 )"0*+

. C4 "?=6

-. Bread board

7. Connecting ires

THEORY:

5ein bridge oscillator is an audio frequency C oscillator. The feedback signal isconnected to positi3e terminal so that the op)amp is orking as a non)in3erting amplifier.

Therefore the feedback netork need not pro3ide any phase shift.

1The frequency of oscillation f >

2XC

PROCEDURE:


2. The poer is sathe 4H and sinusoidal a3eform is obtained for the first set

of C and 3alues.

". 5ith the help of C4, the oscillator frequency is determined.

%. The calculated 3alue of the frequency of oscillation is compared ith the

actual 3alue as determined from an obser3ation of the oscillation period.

. 'imilarly the steps are repeated for the other set of C and 3alues and are

3erified.

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CIRCUIT DIAGRAM:

TABULATION:

esistorJ

Capacitor$

Time periodin msec

mplitude in+olts

4bser3edfrequency =6

Calculatedfrequency =6

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+3

-2

V +7

V -4

O U T6

O S 1 1

O S 25

U 1

u A 7 4 1

2 . 2 K

0 . 1 u F

1 0 K

2 . 2 K

2 2 K

0 . 0 1 u F

1 2 V

1 2 V

00

0

0

Vo


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MODEL GRAPH:

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RESULT:

Thus the 5ein bridge oscillator has been designed and its output frequency has

been 3erified ith theoretical frequency.

Lesigned frequency > 1 =6

4bser3ed frequency >

HARTELEY OSCILLATOR

AIM:

To design, construct and test the performance of =artley oscillator.

APPARATUS REQUIRED:

1. Transistor BC10/

2. esistors 270kJ,"%0 kJ

". Capacitor 0.01$f,0.02$f

%. nductor bo "0m=, 0.7m=

. Cathode ay 4scilloscope

-. &oer supply (0)"0*+

7. Bread board

/. Connecting ires

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THEORY:

esistors 1, 2, e pro3ide the necessary L.C. bias to the transistor. Ce

is a bypass capacitor. Cc1, Cc2 are coupling capacitors. The feedback netork consisting

of inductors 1 and 2 and capacitor C1 determines the frequency of the oscillator. 5hen

the supply 3oltage :+cc is sitched on, a transient current is produced in the tank circuit

and consequently damped harmonic oscillations are set up in the circuit. The oscillatory

current in the tank circuit produces ac 3oltages across 1 and 2. s terminal " is earthed

it ill be at 6ero potential. f terminal 1 is at positi3e potential ith respect to " at any

instant, terminal 2 ill be a negati3e potential ith respect to " at the same instant. Thus

the phase difference beteen the terminals 1 and 2 is alays 1/0. n the Ce mode, the

transistor pro3ides the phase difference of 1/0 beteen the input and output. Therefore

the total phase shift is "-0. Thus at the frequency determinant for the tank circuit, the

necessary condition for sustained oscillations is satisfied. f the feedback is ad 1 the circuit acts as an oscillator.

CIRCUIT DIAGRAM:

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PROCEDURE:


2. 'et the supply 3oltage +cc > :12+

". By ad


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TABULATION:

'.Ho mplitude in +olts Time period in msec

MODEL GRAPH:

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RESULT:

Thus the performance of =artley oscillator as designed and tested.

Lesigned frequency >

4btained frequency >

COLPITTS OSCILLATOR

AIM:

To design and construct the colpittYs oscillator circuit and dra the a3eform.

APPARATUS REQUIRED:

1. &' 10+

2. Transistor BC107

". esistor 270,"%0

%. Capacitor 0.01K

. nductor m=,"0m=

-. C4 0)"0?=6

7. Bread board

THEORY:

esistors 1, 2, e pro3ide the necessary L.C. bias to the transistor. Ce is a

bypass capacitor. Cc1, Cc2 are coupling capacitors. The feedback netork consisting of

inductors 1 and 2 and capacitor C1 determines the frequency of the oscillator. 5hen

the supply 3oltage :+cc is sitched on, a transient current is produced in the tank circuitand consequently damped harmonic oscillations are set up in the circuit. The oscillatory

current in the tank circuit produces ac 3oltages across C1 and C2. s terminal " is earthed

it ill be at 6ero potential. f terminal 1 is at positi3e potential ith respect to " at any

instant, terminal 2 ill be a negati3e potential ith respect to " at the same instant. Thus

the phase difference beteen the terminals 1 and 2 is alays 1/0. n the Ce mode, the

transistor pro3ides the phase difference of 1/0 beteen the input and output. Therefore

the total phase shift is "-0. Thus at the frequency determinant for the tank circuit, the

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necessary condition for sustained oscillations is satisfied. f the feedback is ad 1 the circuit acts as an oscillator.

PROCEDURE:

1. The circuit connections are gi3en as per the circuit diagram.

2. 'et the input supply 3oltage.

". By ad


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CIRCUIT DIAGRAM:

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Q 1

B C 1 0 7

R 1

3 4 0

R 2

2 7 0 K

1

2

1

3 0 m H

1 2

2

5 m H

C 1

0 . 0 1 u F

C 2

0 . 0 1 u F

C 3

0 . 0 1 u F

C 4

0 . 0 1 u F

C 5

0 . 0 1 u F

0

0

V 1

1 0 V

0

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DESIGN PROCEDURE:

requency of oscillation f > 1 9 (2QVC*

ssume f > "0 =6 and > m=

C>.-n

nd C > C1C29 (C1: C2*

et C1 >0.01$

C2 > 0.01$

TABULATION:

mplitude

in +olts

Time period

in msec

&ractical frequency

in =6

Theoretical frequency

in =6

MODEL GRAPH:

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RESULT:

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Thus the sine a3eform is generated by constructing colpittYs oscillator.

Theoretical frequency >

&ractical frequency >

TUNED CLASS C AMPLIFIER

AIM:

To design and construct the tuned class C amplifier and dra the frequency

response.

APPARATUS REQUIRED:

1. &' +

2. Transistor '100

". esistor %70,10,-/0

%. Capacitor 0.01Kf, 0.1Kf, 0.""Kf

. 'ignal generator 2?=6

-. C4 0)"0?=6

7. Bread board

THEORY:

Class C operation means the collector current flos for less than 1/0S of the a.c.

input

cycle. t implies that the collector current of a class C amplifier is highly non sinusoidal.

Because of current flos in pulses thus a tank circuit is used as a load in an amplifier

results in a sinusoidal output 3oltage, thus this amplifier is knon as class C tuned

amplifier. 5hen no bias is applied then +B8 > 0. The input


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component of the class C a3eform, hich has the same frequency as input. 5hen the

resultant frequency of the tank circuit is made equal to the input frequency, the

impedance of the tank circuit is maimum, result in hich the gain is maimum for all

other frequency impedance as ell as gain are much smaller. The amplitude of the

fundamental component of class c a3eform depends on the conduction angle. The

greater the conduction angle results in greater the ratio of the amplitude of the

fundamental component to the amplitude of the total a3eform.

PROCEDURE:

1. The circuit connections are gi3en as per the circuit diagram.

2. 'et the input supply 3oltage.

". By ad


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CIRCUIT DIAGRAM:

S 1 0 0

6 8 0 O h m s

1 0 K O h m s

4 7 0 O h m s

0 . 0 1 u F

0 . 3 3 u F

1 0 0 u FV ! ! " # 0 - 5 $ V

1

2

1 m H

0 . 1 u F

0

+cc > 1,+

.unction generator

( 0 ) 2? * =6

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DESIGN PROCEDURE:

+BB> + +CC> 1+

> %70! C> 10m

fl> 0=6 C > 0.01$

et f4> 0 =6

f4> 1 9 (2QVC*

> 1m=

Choose input coupling capacitor > 0.1$

4utput coupling capacitor > 0.""$

MODEL GRAPH:

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TABULATION:

Vin = V

'.H4 requency in =6 4utput 3oltage in

+olts

@ain in dB

20log(+o9 +in*

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Clipper is a circuit hich is used to clip off unanted portion of the a3eform,

ithout distorting the remaining part of the a3eform. Clippers can be constructed using

diodes. 5hen the diode is connected in series ith the load, such a circuit is called a

series clipper. The clipper le3el is determined by the reference 3oltage + refand could be

obtained by the supply 3oltage. 5hen the supply 3oltage is positi3e, the circuit is said to

be positi3e reference clipper. 5hen the input 3oltage +i is greater than +r, the diode

becomes forard biased and the output 3oltage is obtained hich is equal to +i, hen +i

[ +r, The diode is re3erse biased and the circuit becomes open. The portion of +i [ +r

are clipped off. 5hen a negati3e 3oltage +r is gi3en, the output is obtained only hen +i

W +r. The portion of +iWr are clipped off.

CLAMPER:

The clamper hich is used to add a dc le3el as per the requirements to the ac

output signal is called clampers. The capacitor, diode and resistors are the " basic

elements of a clamper circuit. They are also called as dc inserter circuits or dc resonators.

They are positi3e and negati3e clampers depending on hether positi3e dc or negati3e dc

shift is introduced. positi3e clamper adds a positi3e le3el to the ac output. Luring the

positi3e half cycle of +i, the diode is re3erse biased and the capacitor starts discharge.

Luring the negati3e half cycle, the diode gets forard biased and the capacitor charges to

maimum le3el +m. negati3e clamper adds a negati3e le3el to the ac output. Luring

positi3e half cycle, the diode is forard biased and during negati3e half cycle it is

re3erse biased.

INTEGRATOR:

or a lo pass C circuit, if the time constant is 3ery large as compared to the

time required by the input signal to make an appreciable change, the circuit acts as an

integrator. Znder this case, the drop across C is negligible compared to drop across .

Thus the entire input +i (t* can be assumed to be appearing across . Then the current i is

gi3en by, +r> +i > i

i > +i 9

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DIFFERENTIATOR:

or a high pass C circuit, if time constant is 3ery small as compared to the time

required by the input signal to make an appreciable change the circuit acts as a

differentiator.

i > C (d+c 9 dt*

i > C (d+i 9 dt*

+o > i

+o > C (d+i 9 dt*

PROCEDURE:

1. The circuit connections are made as per the circuit diagram.

2. By ad


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SERIES CLIPPERS:

Neg%)i*e &+i,,e" -i). ,!si)i*e "ee"en&e:

1 % 4 0 0 7

1 &

2 V ' (

F R ) Q " 1 K H *

V A , " 5 V

0

Neg%)i*e &+i,,e" -i). neg%)i*e "ee"en&e:

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1 % 4 0 0 7

1 &

2 V ' (

F R ) Q " 1 K H *

V A , " 5 V

0

P!si)i*e &+i,,e" -i). ,!si)i*e "ee"en&e:

1 % 4 0 0 7

1 &

2 V ' (

F R ) Q " 1 K H *

V A , " 5 V

0

P!si)i*e &+i,,e" -i). neg%)i*e "ee"en&e:

1 % 4 0 0 7

1 &

2 V ' (

F R ) Q " 1 K H *

V A , " 5 V

0

PARALLEL CLIPPERS:

P!si)i*e &+i,,e" -i). ,!si)i*e "ee"en&e:

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2 V ' (

F R ) Q " 1 K H *

V A , " 5 V

0

1 % 4 0 0 7

1 &

P!si)i*e &+i,,e" -i). neg%)i*e "ee"en&e:

2 V ' (

F R ) Q " 1 K H *

V A , " 5 V

0

1 % 4 0 0 7

1 &

Neg%)i*e &+i,,e" -i). ,!si)i*e "ee"en&e:

2 V ' (

F R ) Q " 1 K H *

V A , " 5 V

0

1 % 4 0 0 7

1 &

Neg%)i*e &+i,,e" -i). neg%)i*e "ee"en&e:

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2 V ' (

F R ) Q " 1 K H *

V A , " 5 V

0

1 % 4 0 0 7

1 &

INTEGRATOR:

F R ) Q " 1 K H *

V A , " 5 V

0

0 . 1 u F

1 &

DIFFRENTIATOR:

F R ) Q " 1 K H *

V A , " 5 V

0

0 . 1 u F

1 &

CLAMPER:

P!si)i*e &+%/,e":

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F R ) Q " 1 K H *

V A , " 5 V

0

0 . 1 u F

1 &

1 % 4 0 0 7

2 V ' (

Neg%)i*e C+%/,e":

F R ) Q " 1 K H *

V A , " 5 V

0

0 . 1 u F

1 &

1 % 4 0 0 7

2 V ' (

TABULATION:

CLIPPER:

'.Ho Type of the clipper mplitude in + Time period in msec

CLAMPER:

'.Ho Type of the clamper mplitude in + Time period in msec

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INTEGRATOR:

'.Ho Type of the input mplitude in + Time period in msec

DIFFERENTIATOR:

'.Ho Type of the input mplitude in + Time period in msec

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RESULT:

Thus Clipper, clamper, differentiator and integrator circuits ere constructed and

their output as obtained.

ASTABLE MULTIVIBRATOR

AIM:

To design, construct and study the characteristics of the astable multi3ibrator.

APPARATUS REQUIRED:

1. Transistor BC1%/

2. esistors 2kJ,.- kJ

". Capacitor 0.1Kf

%. &'4 (0)"0*+

. Cathode ay 4scilloscope-. Bread board

7. Connecting ires

THEORY:

?ulti3ibrator are to stage sitching circuits in hich the output of the first stage is fed

to the input of the second stage and 3ice 3ersa. The outputs of the to stages are complementary.

The astable or free running multi3ibrator generates square a3e ithout any eternaltriggering pulse. t has no stable states i.e. it has to quasi stable states. t sitches back and

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forth from one state to another, remaining in each state for a time depending upon the

discharging of a capaciti3e circuit. Transistor astable multi3ibrator in hich components in one

half of a cycle of the circuit are identical to their counter part in the other half. The square a3e

output can be taken from collector point of D1 and D2. 5hen the supply 3oltage +cc is applied

due to some circuit imbalance. nitially let assume that D1 is conducting and D2 if cut off. The

+c1 the output of D1 is equal to +ce (sat* i.e. approimately 6ero 3olt and +c2>:+cc. t this

instant C1 charges eponentially ith a time constant 1C1 toards the supply 3oltage through

1 and correspondingly +b2 also increases eponentially toards +cc.

5hen +b2 crosses the cut)in 3oltage, D2 starts conducting and +c2 falls to +ce(sat*.

lso +b1 falls due to capaciti3e coupling beteen collector of D2 and base of D1, thereby

dri3ing D1 into off state. Ho the rise in 3oltage +c1 is coupled through C1 to the base of D2,

causing a small o3ershoot in 3oltage +b2. Thus D1 is off and D2 is on. t this instant, the

3oltage le3els are +b1 is negati3e,+c1> +cc,+be(sat*, +c2>+ce(sat*.

5hen D1 is off and D2 is on, the 3oltage +b1 increases eponentially ith a time

constant 2C2 toards +cc. Therefore D1 is dri3en into saturation and D2 is cut off. Ho the

3oltage le3els are +b1>+be (sat*, +c1>+ce (sat*, +b" is negati3e and +c2>+cc. t is clear that

hen D2 is on, the falling 3oltage +c2 permits the discharging of the capacitor C2, hich dri3es

D1 into cutoff. The rising 3oltage of +c1 feeds back to the base of D2 tending to turn it on. This

process is said to be regenerati3e. t is used as square a3e generator, 3oltage to frequency

con3erter and in pulse synchroni6ation, in the construction of digital 3oltmeter and '?&'.

PROCEDURE:


2. irst the C4 connections are made at the collector of D1 and D2 ith constant

supply 3oltage i.e. +cc>10+. Then the amplitude and time period of the sine a3e

is noted.". The input and output signals are grounded, from hich the saturation is noted.

%. Then the C4 connections are made at the base of D1 and D2, the same

procedure is repeated for this connection.

. The graph is plotted beteen the time in ms and the amplitude in 3olts.

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CIRCUIT DIAGRAM:

B C 5 4 8 B C 5 4 8

5 . 6 K O h m s5 . 6 K O h m s 2 K O h m s2 K O h m s

0 . 1 u F0 . 1 u F

00 000 0

+c1

+cc > 10+

+B2+B1 +c2

DESIGN PROCEDURE:

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+CC> 10+ and C> m

C> +CC9 C> 2!

C1> C2> C> 2 !

requency of oscillation > 1." =6

et 1 > 2 > and C1>C2>C

Time period T > 1."/C

requency f > 1 9 T > 19 1."/C

1."F10G" > 19 1."/C

ssume C > 0.1$

>W > .7 ! > .- !

TABULATION:

'.Ho 4utput mplitude in +olts Time period in msec

1 +C81

2 +B81

" +C82

% +B82

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MODEL GRAPH:

8'8C98C8


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RESULT:

Thus the astable multi3ibrator as designed and its characteristics ere studied.

MONOSTABLE MULTIVIBRATOR

AIM:

To design, construct and test the performance of the monostable multi3ibrator.

APPARATUS REQUIRED:

1. transistor BC107

2. Liode 1H%007

". esistor .#!, %2 !, 10 !, 100 !

%. capacitor ".2n, 2"p

. poer supply (0)"0*+

-. function generator (0)2?*=6

7. cathode ray oscilloscope (0)"0?*=6/. Bread board

#. Connecting ires

THEORY:

?onostable multi3ibrator has one stable state and one quasi stable state. t is also

knon as one)shot multi3ibrator or Zni3ibrator. t remains in its stable state until an input

pulse triggers it into its quasi stable state for a time duration determined by discharging anC circuit and the circuit returns to its original stable state automatically. t remains there

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until the net trigger pulse is applied. Thus a monostable multi3ibrator cannot generate

square a3es of its on like an astable multi3ibrator. 4nly eternal trigger pulses ill

cause it to generate the rectangular a3eform.

t consists of to identical transistors D1, D2 ith equal collector resistances of

C1 and C2. The output of D2 through a resisti3e attenuator in hich C1 is a small

speed up capacitor to speed up the transition. The 3alues of 2 and N+BB are chosen so

as to re3erse bias D1 and keep it in the 4 state. The collector supply :+CC and ill

forard bias D2 and keep it in 4H state. ctually this is the stable state for the circuit.

5hen a positi3e trigger pulse of short duration and sufficient magnitude is applied

to the base of D1 through C2, Transistor D1 starts conducting and thereby decreasing the

3oltage at its collector +C\ 5hich is coupled to the base of D2 through the capacitor C.

This decreases the forard bias on D2 and its collector current decreases. The increasing

positi3e potential on the collector of D2 is applied to the base of D1 through 1. this

further increases the base potential of D1 and D1 is quickly dri3en to saturation and D2 to

cut)off.

The capacitor C is charged to approimately :+CC through the path +CC, and

D1. as the capacitor C discharges, the base of D2 is forard biased and collector current

starts to flo into D2. Thus D2 is quickly dri3en to saturation and D1 is cut)off. This is

the stable state for the circuit and remains in this condition until another trigger pulse

causes the circuit to sitch o3er the states. The duration of the output pulse of the

monostable multi3ibrator is gi3en by T > 0.-#C.

The monostable multi3ibrator is used to function as an ad


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CIRCUIT DIAGRAM:

C 1

0 . 1 u

C 2

0 . 1 U

R 1

1 K

R 2

1 KR 3

1 0 K

R 4

1 0 K

R 5

2 0 KC 3

1 U

Q 1

B C 5 4 7

Q 2

B C 5 4 7

V 1

6 V

V 2

- 1 . 5 V

0000

0

V 3

T " 0

T F " 1 s

, / " 2 0 u s

, ) R " 4 0 u s

V 1 " 5

T R " 1 s

V 2 " 0

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MODEL GRAPH:

8'8C98C8


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PROCEDURE:


2. Hegati3e trigger pulse is applied to the collector of the transistor D1 through the

diode.

". The C4 output connections are made at the collector of both the transistor.

%. The amplitude and time period are noted ith constant supply 3oltages.

. The graph is plotted beteen the time in msec and the amplitude in +olts.

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8'8C98C8


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RESULT:

Thus the performance of monostable multi3ibrator as tested.

DIFFERENTIAL AMPLIFIER

AIM:

To stimulate a differential amplifier circuit using 4CL &'&C8.

PROCEDURE:

1. 4CL ) capture

2. ?aimi6e the session log.

". n file, open a ne pro


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CIRCUIT DIAGRAM:

8'8C98C8


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Q 1

Q 2 % 2 2 2 2

Q 2

Q 2 % 2 2 2 2

R 1

3 . 9 K

R 2

3 . 9 K

R 3

3 . 6 K

V 1

F R ) Q " 5 0 H *

V A , " 1 V

V O F F " 0 VV 2

F R ) Q " 5 0 H *

V A , " 0 . 9 9 V

V O F F " 0 V

V 31 2 V

V 4

1 2 V

0 00

0

V-V+

8'8C98C8


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8'8C98C8


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RESULT:

Thus the differential amplifier circuit using 4CL &'&C8 has been stimulated.

ACTIVE FILTER 0 BUTTERWORTH SECOND ORDER LOW PASS FILTER

AIM:

To stimulate an acti3e butterorth second order lo pass filter circuit using

4CL &'&C8.

PROCEDURE:

1. 4CL ) capture




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CIRCUIT DIAGRAM:

C 1

0 . 1 U

C 2

0 . 1 U

V 1

1 5 V

V 2

1 5 V

0

0

0

0

0

R 1

1 &

R 2 1 . 5 9 K

R 3

1 . 5 9 K

R 4 1 . 5 9 K

V 3

2 V (

0 V ' (

+3

-2

V +7

V -4

O U T6

O S 11

O S 25

U 2

u A 7 4 1

V

8'8C98C8


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8'8C98C8


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RESULT:

Thus an acti3e butterorth second order lo pass filter circuit using 4CL

&'&C8 has been stimulated.

ACTIVE FILTER 0 BUTTERWORTH SECOND ORDER HIGH PASS FILTER

AIM:

To stimulate an acti3e butterorth second order high pass filter circuit using

4CL &'&C8.

PROCEDURE:

1. 4CL ) capture




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CIRCUIT DIAGRAM:

+3

-2

V

+

7

V -4

O U T6

O S 11

O S 25

U 1

u A 7 4 1

V 1

1 5

V 2

1 5

R 1

5 . 8 6 &

R 2

1 0 &

R 3

1 . 6 &

R 4

1 . 6 &

C 1

0 . 1 u

C 2

0 . 1 u

0

0

0

0

V 3

F R ) Q " 5 0 h *

V A , " 1

V O F F " 0

0

V

8'8C98C8


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8'8C98C8


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RESULT:

Thus an acti3e butterorth second order high pass filter circuit using 4CL


ASTABLE( MONOSTABLE AND BISTABLE MULTIVIBRATOR

AIM:To stimulate stable, ?onostable nd Bistable ?ulti3ibrator circuit using

4CL &'&C8.

PROCEDURE:

1. 4CL ) capture




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8'8C98C8


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MONOSTABLE MULTIVIBRATOR:

8'8C98C8


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8'8C98C8


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ASTABLE MULTIVIBRATOR:

8'8C98C8


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RESULT:

Thus stable, ?onostable nd Bistable ?ulti3ibrator circuit using 4CL


DIGITAL TO ANALOG CONVERTOR

AIM:

8'8C98C8


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To stimulate Ligital to nalog Con3ertor circuit using 4CL &'&C8.

PROCEDURE:

1. 4CL ) capture




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+3

-2

V

+

7

V

-

4

O U T 6

O S 1 1

O S 2 5

U 1

u A 7 4 1R 1

1 0 K

R 2

1 0 K

R 3

1 0 K

R 4

1 0 K

R 5

2 0 K

R 6

2 0 K

R 7

2 0 K

R 8

2 0 K

R 9

2 0 K

R 1 0

2 0 KR 1 1

1 0 K V 1

1 5 V ' (V 2

1 6 V ' (

V 3

1 5 V ' (

0000 0

0

00

V 4

1 6 V ' (

V 5

1 6 V ' (

V 6

1 6 V ' (

V

8'8C98C8


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TABULATION:

'.Ho L" L2 L1 L0 4utput

3oltage (+*1 0 0 0 0 0

2 0 0 0 1 1" 0 0 1 0 2% 0 0 1 1 " 0 1 0 0 %- 0 1 0 1 7 0 1 1 0 -/ 0 1 1 1 7# 1 0 0 0 /

10 1 0 0 1 #11 1 0 1 0 1012 1 0 1 1 111" 1 1 0 0 121% 1 1 0 1 1"1 1 1 1 0 1%1- 1 1 1 1 1

8'8C98C8


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RESULT:

Thus Ligital to nalog Con3ertor circuit using 4CL &'&C8 has been

stimulated.

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CIRCUIT DIAGRAM:

/ 7 11

22

13

24

6

+ V C C8

- V C C5

U 1

A 6 3 3

V 1

F R ) Q " 5 0 H *

V A , " 1 0

V O F F " 0

V 2

F R ) Q " 5 0 H *

V A , " 0 V

V O F F " 0 V

V 3

F R ) Q " 5 0 H *

V A , " 4 V

V O F F " 0 V

V 4

F R ) Q " 5 0 H *

V A , " 0 V

V O F F " 0 V

V 5

F R ) Q " 5 0 H *

V A , " 1 V

V O F F " 0 V

V 6

1 5 V ' (

V 7

1 5 V ' (

C 2

0 . 1 u

0

C 1

0 . 1 u

00 00

V

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8'8C98C8


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RESULT:

Thus nalog ?ultiplier circuit using 4CL &'&C8 has been stimulated.

CMOS INVERTER( NAND 1 NOR GATES

AIM:

To stimulate C?4' n3erter, HHL ] H4 @ates circuit using 4CL

&'&C8.

PROCEDURE:

1. 4CL ) capture




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CIRCUIT DIAGRAM:

CMOS NOT GATE:

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93/99

1

R F 9 1 4 0

2

R F 9 1 4 0

0 0

0

V 1

1 2 V

R 1

1 0 0 K

V 2

T " 0

T F " 1 s

, / " 2 0 u s

, ) R " 4 0 u s

V 1 " 0 V

T R " 1 s

V 2 " 5 V

V V

8'8C98C8


94/99

CMOS NOR GATE:

1

R F 9 1 4 0

2

R F 9 1 4 0

3

R F 1 5 0

4

R F 1 5 0

V 1T " 0

T F " 1 s

, / " 1 0 u s

, ) R " 4 0 u s

V 1 " 0 V

T R " 1 s

V 2 " 5 V

V 2

T " 0

T F " 1 s

, / " 2 0 u s

, ) R " 4 0 u s

V 1 " 5 V

T R " 1 s

V 2 " 0 V

V 3

5 V

0

0

0

0

V

V

V

8'8C98C8


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CMOS NAND GATE:

8'8C98C8


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2

R F 9 1 4 0

3

R F 1 5 0

4

R F 1 5 0

V 1

5 V

0

0

0

0

V 2

T " 0

T F " 1 s

, / " 3 0 u s

, ) R " 4 0 u s

V 1 " 0 V

T R " 1 s

V 2 " 5 V

V 3

T " 0

T F " 1 s

, / " 2 0 u s

, ) R " 4 0 u s

V 1 " 5 V

T R " 1 s

V 2 " 0 V

5

R F 9 1 4 0

V

V

V

TRUTH TABLE:

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CMOS INVERTER:

CMOS NOR:

CMOS NAND:

8'8C98C8

INPUT OUTPUT

0 11 0

INPUT 2 INPUT3 OUTPUT

0 0 10 1 01 0 01 1 0

INPUT 2 INPUT3 OUTPUT

0 0 10 1 11 0 1

1 1 0


98/99

8'8C98C8


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RESULT:

Thus C?4' n3erter, HHL ] H4 @ates circuit using 4CL &'&C8 has

been stimulated.

ec-ii manual original

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