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CHAPTER 5. Memory Element

Electrical Engineering DepartmentPTSB

EC303COMPUTER ARCHITECTURE & ORGANIZATION

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Learning Outcomes

After learning of this chapter, student should beable:-

To know the computer memory organization

To understand Virtual Memory Organization

To understand cache memory

To understand decoder

To realize connecting memory chips to computerbus

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Brainstorming

3

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4

Computer Memory Organization

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Memory

5

Main memory consists of a number

of storage locations, each of which isidentified by a unique address

The ability of the CPU to identify

each location is known as its

addressability

Each location stores a wordi.e. the

number of bits that can be processed

by the CPU in a single operation.

Word lengthmay be typically 16, 24,

32 or as many as 64 bits.

A large word length improves system

performance, though may be less

efficient on occasions when the full word

length is not used

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Block Diagram of Memory

An M-bit data value can be read or written at each unique N-bit address

Read operation- take data out of the specified address in the memory Write operationput data into a specified address in memory

6

Memory

2Nwords

(M-bit per word)Read/Write

Chip Select

(Chip Enable)

M-bit Data Output

(for Read/Write)

M

Example: Byte-addressable2MB memory

M = 8 (because of byte-addressability)

N = 21 (1 word = 8-bit)

N-bit

address lines

N

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10

D7

D2

D1

D0

A10

A8

A7

A0

2K x 8

R/WCS

RAM CHIP

Design a 2K x 8 memory chips

0 = Write

1 = Read

CS = CHIP SELECT

CS = 0 enables theoutput buffers

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Describe the buses line to interfacememory

In computer architecture, a busis a subsystem that transfers data between

components inside a computer, or between computers.

How the RAM chip works?

a) Data bus-Carry information

b) Address bus- Determine where itshould be sent

c) Control bus - Determine its operation

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OPERATION OF PSYSTEM (Fetch &Execute Cycles cont)

Read Cycle :- CPU sends a signal via control bus. If the bus

is busy, CPU is put on Wait state.

- If the bus is free, CPU will place instruction

address on the address bus.

- This address will be decoded or translated bythe circuitry in the memory or I/O interface.

- Finally the data at the specific address isobtained and is placed on the data bus.

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OPERATION OF COMPUTER SYSTEMFetch & Execute Cycles Cont..

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Write cycles :- Write cycle enables CPU sends data to the

memory or I/O devices.

- CPU will send a signal (request to write) to the

control bus.

- If the data bus is free, the data is placed on thedata bus, whereas the location address will be

placed on the address bus.- CPU will then send the data to the destination

with respect to the address.

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OUTCOME :

a. Design an interface chip circuit for an 8-word 3-bit RAM chip.

b. Manipulate the circuit (from a) to design layoutcircuit for adding memory to a bus using

decoderc. Define function of decoder.

d. Illustrate the circuit of a four-output decoder

and parallel decoder.

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RAM CHIP

Design a 8-word 3 bit RAM chip ?

D2D1

D08 X 3

R/WCS

A0

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Q & A

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How to design a 1Mx8 computer system

using 1Mx4 memory chips

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Building Memory in Hierarchy

Design a 1Mx8 using 1Mx4 memory chips

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D3

D2

D1

D0

A19A18

A17

A0

1Mx4

R/WCS

D7

D6

D5

D4

A19A18

1Mx4

R/WCS

A17

A0CS

Prof. Sean Lees Slide, Georgia Tech

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Q & A

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How to design a

2Mx4 using 1Mx4 memory chips

1) How many chip ?Chip needed = system needed

chip used2) Calculate the address line for chip used3) Calculate the address line for system

4) Decide the decoder needed

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A19

A18

A17

A0

1Mx4

R/WCS

A19

A18

A17

A0

1Mx4

R/WCS

A20 1-to-2

Decoder

CS

1

0

D3

D2

D1

D0


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Q & A

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How to design a

64Kx8 computer system

using 16Kx4 memory chips

1) How many chip ?Chip needed = system needed

chip used2) Calculate the address line for chip used

3) Calculate the address line for system4) Decide the decoder needed5) Calculate the data lines for chip and system

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Design a 64Kx8 using 16Kx4 memory chips

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A13A12A11

A0

16Kx4

CS R/W

A13A12

A11

A0

16Kx4

CS R/W

A13A12A11

A0

16Kx4

CS R/W

A13A12A11

A0

16Kx4

CS R/W

D7

D6

D5

D4

D3

D2D1

D0

A13A12A11

A0

A14

2-to-4

Decoder

CS

1

0


A15

2

3

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Memory Organization Example

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1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit




0

1

2

3

D7 D6 D5 D4 D3 D2 D1 D0

4 words x 8 bits2-to-4

Decoder

A0

A1

CS

Chip Select

Wordline (WL)

BitLine

Modified from Prof Sean Lees Slide, Georgia Tech

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How to Address Memory

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0

1

2

3

D7 D6 D5 D4 D3 D2 D1 D0

2-to-4

DecoderA0=1

A1=0

Access address = 0x1

CS

Chip Select=1

4 words x 8 bits


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Decoder

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Decoder A decoderis a device which does the reverse of an encoder, undoing the

encoding so that the original information can be retrieved.

Four-output decoder and a parallel decoder

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Determine the digital circuit in a tree-typedecoding network with 16 output lines

The first stage is a 2-to-4-line decoder.A new variable is introduced in each successive stage; it orits inverse becomes one input to each of the two-input AND gates in this stage. The second input toeach AND gate comes from the preceding stage. For example, one of the outputs of the secondstage will beAB'C. This will result in two outputs from the next stage,AB'CD and AB'CD'. This designdoes avoid the fan-out problem in the early stages but not in the later stages. Nevertheless, theproblem exists only for the variables introduced in those stages.

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A balanced multiplicative decodernetwork

Requires the minimum number of diodes

This decoder circuit is the fastest and mostregular.

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Computer Memory Hierarchy

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Storage Hierarchies :Computer data storage often called storageor memory, refers to computer

components and recording media that retain digital data. Data storage is one of

the core functions and fundamental components of computers.

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PRIMARY STORAGE

Primary storage(or main memoryor internal memory), often referred to simply as memory, isthe only one directly accessible to the CPU. The CPU continuously reads instructions stored there and

executes them as required. Any data actively operated on is also stored there in uniform manner.

RAM: Processor registers are located inside the processor. Each register typically holds a word of data

(often 32 or 64 bits). CPU instructions instruct the arithmetic and logic unit to perform variouscalculations or other operations on this data (or with the help of it). Registers are the fastest of all

forms of computer data storage.

Processor cache is an intermediate stage between ultra-fast registers and much slower mainmemory. It's introduced solely to increase performance of the computer. Most actively usedinformation in the main memory is just duplicated in the cache memory, which is faster, but of muchlesser capacity.

Main memory is directly or indirectly connected to the central processing unit via a memory bus. It isactually two buses ): an address bus and a data bus. The CPU firstly sends a number through anaddress bus, a number called memory address, that indicates the desired location of data. Then itreads or writes the data itself using the data bus.

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SECONDARY STORAGE

Secondary storage(also known as external memory or auxiliary storage), differs from primarystorage in that it is not directly accessible by the CPU. The computer usually uses its input/outputchannels to access secondary storage and transfers the desired data using intermediate area in

primary storage. Secondary storage does not lose the data when the device is powered downit isnon-volatile.

Example: Flash drive, CD and DVD drives, floppy disks, punch cards.

TERTIARY STORAGE Tertiary storageor tertiary memory, provides a third level of storage. Typically it involves a

robotic mechanism which will mount(insert) and dismountremovable mass storage media into astorage device according to the system's demands; this data is often copied to secondary storagebefore use.

Example: useful for extraordinarily large data stores, accessed without human operators(roboticarms). Typical examples include tape libraries and optical jukeboxes.

Off-line storage Off-line storageis a computer data storage on a medium or a device that is not under the control

of a processing unit. The medium is recorded, usually in a secondary or tertiary storage device, andthen physically removed or disconnected. It must be inserted or connected by a human operatorbefore a computer can access it again. Unlike tertiary storage, it cannot be accessed without humaninteraction.

Example : Optical discs and flash memory devices

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Memory Devices Hierarchy

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Memory HierarchyTypical Memory Parameters

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As you can see in the diagram above, the CPU accesses memory

according to a distinct hierarchy. Whether it comes from permanentstorage (the hard drive) or input (the keyboard), most data goes inrandom access memory (RAM) first.

The CPU then stores pieces of data it will need to access, often in a

cache, and maintains certain special instructions in the register.We'll talk about cache and registers later.

All of the components in your computer, such as the CPU, the harddrive and the operating system, work together as a team, andmemory is one of the most essential parts of this team.

From the moment you turn your computer on until the time youshut it down, your CPU is constantly using memory

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The most important parameters of a memorysystem are: Capacity - the maximum number of units of data that

it can store. Access time - the time taken to access the data in

memory.

Data transfer rate - the number of bits per second at

which data can be read. Cycle time - A measure of low often a memory can be

accessed.

Cost - Usually expressed in terms of dollars per bit.

Mainly the computer memory system is dividedinto two: Internal memory

External memory

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Virtual Memory Organization

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Virtual Memory

Solves problem of limited memory spaceCreates the illusion that more memory exists

than is available in system

Two types of addresses in virtual memory

systemsVirtual addressesReferenced by processes

Physical addresses- Describes locations in mainmemory

Memory management unit (MMU)

Translates virtual addresses to physical address

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Vi t l M S t

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Virtual Memory System

Processor

MMU

Cache

Main Memory

Disk

Storage

Virtual address

Physical address

Data

/ instructions

Physical address

Transfer it

reference not inphysical

memory

Controlled

by

processor

Controlledby

Operating

System

Data

/ instructions

i l

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The address space needed and seen byprograms is usually much larger than availablemain memory

Only one part of the program fits into main

memory, the rest stored on secondary memory(hard disk)

In order to be executed or data to be accessed,a certain segment of the program has to be firstloaded into main memory, in this case it has toreplace another segment already in memory.

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i l S

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Movement of programs and data, between mainmemory and secondary storage, is performedautomatically by the operating system. Thesetechniques are called virtualmemory

techniques. The binary address issued by the processor is a

virtual address, it considers a virtual addressspace, mush larger than the physical one

available in main memory

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Vi l M S

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If a virtual address refers to a part of programor data that is currently in the physical memory(cache, main memory), then the appropriatelocation is accessed immediately using the

respective physical address, if this is not thecase , the respective program/data has to betransferred first secondary memory.

A special hardware unit, Memory Management

Unit (MMU), translate virtual address intophysical ones.

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TWO common approaches of Virtual

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TWO common approaches of VirtualMemory Organization

Two common approaches of Virtual Memory

Linear Virtual Memory

Segmented Virtual Memory

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H Vi t l M i O i d?

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How Virtual Memory is Organized?

Virtual memory is organized by either:- paging or segmentation

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Vi t l M O i ti P i

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Virtual Memory Organization-Paging

The virtual programme space (instruction+data)is divided into equal, fixed-size chunks calledpages.

Physical main memory is organized as a

sequence of frames, a page can be assigned toan available frame in order to be stored (pagesize = frame size)

The page is the basic unit of information whichis moved between main memory and disk by thevirtual memory system

P i

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Paging

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Pages on disk

Frames in main memory

Pages

P i

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The program consists of a large amount ofpages which are stored on disk, at any one time,only a few pages have to be stored in mainmemory.

The OS is responsible for loading/ replacingpages so that the number of page faults isminimized

We have a page fault when the CPU refers to alocation in a page which is not in main memory,this page has then to be loaded and, if there isno available frame, it has to replace a pagewhich previously was in memory

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Paging

i

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paging

Virtual memory space : 2 GB

(31 address line, 2^31=2GB)

Physical memory space : 16 MB

(24 address line, 2^24=16MB)

Page length:

2^11 = 2KB

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paging

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paging

Total number of pages

Virtual memory space = 2^31 = 2^20 = 1MB

Page length 2^11

Total number of frames

Physical memory space = 2^24 = 2^13 = 8k

Page length 2^11

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Pages on disk= 20

Frames in main memory = 13

Pages

Paging

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Paging

Accessing a word in memory involves thetranslation of a virtual address into a physicalone

- Virtual address :page number + offset

- Physical address : frame number + offset

Paging

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Paging

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Virtual memory is divided into fixed-size blockscalled pages

typically a few kilobytes

should be a natural unit of transfer to/from disk

Page replacement LRU, MRU, Clock etc

Page placement

Fully associative - efficient

Segmentation

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Segmentation

Supports user view of memory. Virtual memory is divided into variable

length regions called segments

Virtual address consists of a segmentnumber and a segment offset

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Segmentation

Very few systems use the concept of segmentation forimplementing virtual memory.

In segmentation memory is divided in variable size segments.Segment number and an offset within the segment togetherform a virtual address.

If a processor wants a particular data item it first looks up for its

segment number in a segment table to find a segmentdescriptor.

Segment descriptor gives information whether the offset withinthe segment is less than the length of the segment and if it isn'tan interrupt is generated to notify that the segment is found.

If the processor is unable to find the segment in the main

memory it generates a hardware interrupt prompting theoperating system to swap in the segment. The operating system then searches for the segments that were

not in use for a long time and swaps them out of main memoryin order to make space for the new segments to be read in.

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Contrast Paging Vs Segmentation

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Contrast Paging Vs Segmentation

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Paging:

Block replacement easy

Fixed-length blocks

Segmentation:

Block replacement hard

Variable-length blocks

Need to findcontiguous, variable-sized, unused part ofmain memory

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Paging:

Invisible to applicationprogrammer

No external fragmentation

There is internalfragmentation

Unused portion of page

Units of code and data

are broken up intoseparate pages

Segmentation:

Visible to applicationprogrammer

No internalfragmentation

Unused pieces of mainmemory

There is external

fragmentation

Keeps blocks of code ordata as single units

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Cache Memory

Cache- Introduction

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Cache- Introduction

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Small amount of fast memory

Sits between normal main memory and CPU

May be located on CPU chip or module

Small capacity, fast

Large capacity, slow

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Is an intermediate bufferbetween CPU and main

memory. Objective :- to reduce the CPU waiting time

during the main memory accesses. Without cachememory, every main memory

access results in delay in instruction processing. Due to main memory access time is higher than

processor clock period. High speed CPUs time wastedduring memory

access (instruction fetch, operand fetch or result

storing) To minimizethe waiting time for the CPU, a small

but fast memory is introduced as a cachebuffer between main memory and CPU

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A portion of programand datais brought into the cache

memory in advance. The cache controller keeps track of locations of the main

memory which are copied In cache memory When CPU needs for instruction or operand, it receives

from the cache memory (if available) instead ofaccessing the main memory.

Thus the memory access is fast because the slow mainmemory appears as a fast memory.

The cache memory capacity is very small compared tomain memorybut the speed is several times better thanmain memory.

Transfer between the CPU and cache memory usuallyone word at a time.

The cache memory usually can be physically with processorIC as internal cache, also known as on-chip cache.

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Cache Memory Structure

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Cache Memory Structure

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Cache consists of C-lines.

Each line contains K wordsand a tagof a few bits.

The number of words in the line referred as line size.

Tag- a portion of main memory address.

Each line includes a tag identifies which particular blockis currently being stored.

Cache Operation - Overview

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Cache Operation - Overview

CPU requests contents of memory location

Check cache for this data

If present, get from cache (fast)

If not present, read required block from main

memory to cache

Then deliver from cache to CPU

Cache includes tags to identify which block of

main memory is in each cache slot

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Typical Cache Organization

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Typical Cache Organization

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Direct mapping cache example

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Direct mapping cache example

In a direct mapping cache with a capacity of 16KB and a line length of 32 bytes, determine thefollowing;

i) How many bits are used to determine thebyte that a memory operation references withinthe cache line?

ii) How many bits are used to select the line inthe cache that may contain the data.

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Direct mapping

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Direct mapping

Each block of main memory maps to only onecache line

i.e. if a block is in cache, it must be in onespecific place

Address is in two parts

Least Significant w bits identify unique word

Most Significant s bits specify one memory

block The MSBs are split into a cache line field r and

a tag of s-r (most significant)

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Di e t M i Add e St t e E le

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Direct Mapping Address Structure : Example

Tag Line or Slot Word

s-r r w

EXAMPLE : TAG=8, LINE = 14, WORD=2

24 bit address

2 bit word identifier (4 byte block)

22 bit block identifier

8 bit tag (=22-14)

14 bit slot or line No two blocks in the same line have the same Tag field

Check contents of cache by finding line and checkingTag

Direct Mapping Cache Line Table

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Direct Mapping Cache Line Table

Cache line Main Memory blocks held

0 0, m, 2m, 3m2s-m

1 1,m+1, 2m+12s-m+1

. .

. .

. .

m-1 m-1, 2m-1,3m-12s-1

Direct Mapping Cache Organization

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Direct Mapping Cache Organization

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Direct

MappingExample

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Connecting Memory Chips To Computer Bus

Describe the buses line to interface

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memory In computer architecture, a busis a subsystem that transfers data between

components inside a computer, or between computers.

How the RAM chip works?

a) Data bus-Carry information

b) Address bus- Determine where itshould be sent

c) Control bus - Determine its operation

Read cycle for a RAM chip

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Read cycle for a RAM chip Read Bus Cycle: Describes the operations carried out by the processor when a

memory read is executed.

Step of Read Bus Cycle:

Processor initiates a read bus cycle by floating the address of the memory location onthe address lines.

Once the address lines are stable, the processor asserts the address strobe signal onthe bus. The address strobe signals the validity of the address lines.

Processor then sets the Read/Write* signal to high, i.e. read.

Now the processor asserts the data strobe signal. This signals to the memory that theprocessor is ready to read data.

The memory subsystem decodes the address and places the data on the data lines.

The memory subsystem then asserts the data acknowledge signal. This signals to theprocessor that valid data can now be latched in.

Processor latches in the data and negates the data strobe. This signals to the memory

that the data has been latched by the processor. Processor also negates the address strobe signal.

Memory subsystem now negates the data acknowledgement signal. This signals theend of the read bus cycle.

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Read cycle

Write cycle for a RAM chip

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Write Bus Cycle: Sequence of operations in memory write is described here.

Step of Write Bus Cycle: Processor initiates a write bus cycle by floating the address of the memory location

on the address lines. Once the address lines are stable, the processor asserts the address strobe signal on

the bus. The address strobe signals the validity of the address lines. Processor then sets the Read/Write* signal to low, i.e. write. The processor then places the data on the data lines. Now the processor asserts the data strobe signal. This signals to the memory that the

processor has valid data for the memory write operation. The memory subsystem decodes the address and writes the data into the addressed

memory location. The memory subsystem then asserts the data acknowledge signal. This signals to the

processor that data has been written to the memory. Then the processor negates the data strobe, signaling that the data is no longer valid. Processor also negates the address strobe signal.

Memory subsystem now negates the data acknowledgement signal, signaling an endto the write bus cycle.

Write cycle for a RAM chip

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When you save a file and close the application, the file iswritten to the specified storage device, and then it and theapplication are purged from RAM.

In the list above, every time something is loaded or opened, itis placed into RAM. This simply means that it has been put inthe computer's temporary storage area so that the CPU canaccess that information more easily.

The CPU requests the data it needs from RAM, processes itand writes new data back to RAM in a continuous cycle. Inmost computers, this shuffling of data between the CPU andRAM happens millions of times every second.

When an application is closed, it and any accompanying filesare usually purged (deleted) from RAM to make room for newdata. If the changed files are not saved to a permanentstorage device before being purged, they are lost.

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Static Random Access Memory (SRAM)

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y ( )

Typically each bit is implemented with 6 transistors (6T)

Read operation The bitline and its inverse are precharged to Vdd (1)

Then set Wordline (WL) high

Depending on the value stored, either bitline or ~bitline goes low

Write operation

Put the new value on Bitline and its inverse on ~Bitline

Then set the Wordline to high

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BitLineBitLine

Wordline (WL)


Dynamic Random Access Memory (DRAM)

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Dynamic Random Access Memory (DRAM)

1-transistor DRAM cell

Write operation

Put value on bitline and then set WL=1

Read operation

Precharge bitline to Vdd (1)

Assert WL to 1

Storage decays, thus requires periodic refreshing

Read bitline data and write it periodically to keep the value in the memory cell

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Bitline

Wordline (WL)


Memory Description

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y p

Capacity of a memory is described as

# addresses x Word size

Examples:

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Memory # of addr # of data lines # of addr lines # of total bytes

1M x 8 1,048,576 8 20 1 MB

2M x 4 2,097,152 4 21 1 MB

1K x 4 1024 4 10 512 B

4M x 32 4,194,304 32 22 16 MB

16K x 64 16,384 64 14 128 KB

Example

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p

84

Memory with 2 Decoders

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y

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0

1

2

3

8 words x 4 bits2-to-4

Row

Decoder

A1

A2

1-to-2 Column Decoder

D0

D1D2D3

Tristate

Buffer

(read)

0 1

A0

CS

Chip Select CS

Read Operation

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p

86





0

1

2

3

8 words x 4 bits

A1

A2

D0

D1D2D3

0 1

A0 = 0

CS

Chip Select CS

Rd/Wr = 0

2-to-4

Row

Decoder


Write Operation

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p

87





0

1

2

3

A1

A2

D0

D1D2D3

0 1

A0 = 1

CS

Chip Select CS

Rd/Wr = 1


8 words x 4 bits

2-to-4

Row

Decoder



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g y y


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D3

D2

D1

D0

A19A18

A17

A0

1Mx4

R/WCS

D7

D6

D5

D4

A19A18

1Mx4

R/WCS

A17

A0CS


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89

A19

A18

A17

A0

1Mx4

R/WCS

A19

A18

A17

A0

1Mx4

R/WCS

A20 1-to-2

Decoder

CS

1

0

D3

D2

D1

D0


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90

A19A18A17

A0

1Mx4

CS R/W

A19A18A17

A0

1Mx4

CS R/W

A19A18A17

A0

1Mx4

CS R/W

A19A18A17

A0

1Mx4

CS R/W

D7D6

D5

D4

D3

D2

D1

D0

A19A18A17

A0

A20 1-to-2

Decoder

CS

1

0

Read-Only Memory (ROM)

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Non-volatile memory

Permanent binary information is stored Power off does not erase information stored

91

ROM

2kwords

(N-bit per word)

N-bit Data OutputK-bit addresslines

NK

32 x 8 (32 words x 8 bits) ROM 32 X 8 ROM85

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92

85

0

1

2

3

28

29

30

31

D7 D6 D5 D4 D3 D2 D1 D0

A4

A3

A2

A1

A0

5-to-32

Decoder

Eachrepresents32 wires

To read the cell, the bitline is weakly pulled HIGH. Then, the wordline is turned ON

If the transistor is present, it pulls the bitline LOW

If the transistor is not present, the bitline remanins HIGH

Programming the 32x8 ROM

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93

A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 1 1 0 0 0 1 0 1

0 0 0 0 1 1 0 0 0 1 0 1 1

0 0 0 1 0 1 0 1 1 0 0 0 0

1 1 1 0 1 0 0 0 1 0 0 0 0

1 1 1 1 0 0 1 0 1 0 1 1 0

1 1 1 1 1 1 1 1 0 0 0 0 1

012

293031

D7 D6 D5 D4 D3 D2D1 D0

A4

A3

A2

A1

A0

5-to-32

Decoder

Other Flavors of ROMs

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Reprogrammable ROMs

EPROM (Erasable Programmable ROM)

Use UV (Ultra Violet) light for erasing

EEPROM (Electrically Erasable Programmable ROM)

Flash memory

Read and Writable

Non-volatile Power off does not erase information stored

Modern ROMs are not really read-only

They can be reprogrammed as well

Flash memory has become extremely popular to store largeamounts of data in portable systems such as cameras and musicplayers

ec 303-chapter 5

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