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CHAPTER2

LOGIC DESIGN AND

COMPUTER

ARCHITECTURE

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COMPUTERAIDEDDESIGN- CAD

Primary approaches to IC chip design:

Mask-programmable ICsA ROM that can be programmed usingstandard PROM programmer withoutspecialized software or hardware.

Disadvantages:

Consume more powerSlower than dedicated logic circuit

OBE TECHNIQUE: LUCK OF THE DRAW STUDENTS

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Standard-cell devicesIn semiconductor design, standard cellmethodology is a method of designing

application-specific integrated circuits(ASICs) with mostly digital-logic features.Standard cell methodology is an exampleof design abstraction, whereby a low-levelvery-large-scale integration (VLSI) layoutis

encapsulated into an abstract logicrepresentation (such as a NAND gate).Cell-based methodology (the general classto which standard cells belong) makes itpossible for one designer to focus on the

high-level (logical function) aspect of digitaldesign, while another designer focuses onthe implementation (physical) aspect.
http://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/VLSIhttp://en.wikipedia.org/wiki/Integrated_circuit_layouthttp://en.wikipedia.org/wiki/Negated_AND_gatehttp://en.wikipedia.org/wiki/Negated_AND_gatehttp://en.wikipedia.org/wiki/Integrated_circuit_layouthttp://en.wikipedia.org/wiki/VLSIhttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/Application-specific_integrated_circuit

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Along with semiconductor

manufacturingadvances, standard cell

methodology has helped designersscale ASICs from comparatively simple

single-function ICs (of several

thousand gates), to complex multi-

million gate system-on-a-chip (SoC)devices.
http://en.wikipedia.org/wiki/Semiconductor_manufacturinghttp://en.wikipedia.org/wiki/Semiconductor_manufacturinghttp://en.wikipedia.org/wiki/Semiconductor_manufacturinghttp://en.wikipedia.org/wiki/Semiconductor_manufacturing

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PLDA programmable logic deviceor PLD isan electroniccomponent used to buildreconfigurabledigital circuits. Unlike a

logic gate, which has a fixed function, a

PLD has an undefined function at thetime of manufacture. Before the PLD canbe used in a circuit it must beprogrammed.For bigger logic circuits, complex PLDsor CPLDscan be used. CPLDs can replacethousands, or even hundreds of

thousands, of logic gates.As of 2005, most CPLDs are electricallyprogrammable and erasable, and non-volatile
http://en.wikipedia.org/wiki/Electronicshttp://en.wikipedia.org/wiki/Reconfigurable_Computinghttp://en.wikipedia.org/wiki/Reconfigurable_Computinghttp://en.wikipedia.org/wiki/Reconfigurable_Computinghttp://en.wikipedia.org/wiki/Digital_circuithttp://en.wikipedia.org/wiki/Logic_gatehttp://en.wikipedia.org/wiki/Reconfigurable_Computinghttp://en.wikipedia.org/wiki/Digital_circuithttp://en.wikipedia.org/wiki/Logic_gatehttp://en.wikipedia.org/wiki/CPLDhttp://en.wikipedia.org/wiki/CPLDhttp://en.wikipedia.org/wiki/CPLDhttp://en.wikipedia.org/wiki/Logic_gatehttp://en.wikipedia.org/wiki/Digital_circuithttp://en.wikipedia.org/wiki/Reconfigurable_Computinghttp://en.wikipedia.org/wiki/Electronics

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VHDLMany PAL programming devices accept

input in a standard fileformat, commonlyreferred to as 'JEDECfiles'.They areanalogous to softwarecompilers. Thelanguages used as source code for logiccompilersare called hardware description

languages, or HDLs.PALASMand ABELare frequently used forlow-complexity devices, while VerilogandVHDLare popular higher-level description

languages for more complex devices. Themore limited ABEL is often used forhistorical reasons, but for new designsVHDL is more popular, even for low-complexity designs.
http://en.wikipedia.org/wiki/JEDEChttp://en.wikipedia.org/wiki/Softwarehttp://en.wikipedia.org/wiki/Softwarehttp://en.wikipedia.org/wiki/JEDEChttp://en.wikipedia.org/wiki/Compilerhttp://en.wikipedia.org/wiki/Softwarehttp://en.wikipedia.org/wiki/Compilerhttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/PALASMhttp://en.wikipedia.org/wiki/Advanced_Boolean_Expression_Languagehttp://en.wikipedia.org/wiki/Veriloghttp://en.wikipedia.org/wiki/VHDLhttp://en.wikipedia.org/wiki/Veriloghttp://en.wikipedia.org/wiki/VHDLhttp://en.wikipedia.org/wiki/VHDLhttp://en.wikipedia.org/wiki/Veriloghttp://en.wikipedia.org/wiki/Advanced_Boolean_Expression_Languagehttp://en.wikipedia.org/wiki/PALASMhttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Compilerhttp://en.wikipedia.org/wiki/Softwarehttp://en.wikipedia.org/wiki/JEDEC

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SCHEMATICLOGICDESIGNUSINGCPLD

Overview

A schematic design defines thefunctionality of a logic circuit using one

or more schematic files, such as gates,flip-flops and building-block functionssimilar to 74xx TTL devices.

Schematics can also contain "custom"symbols for which you define thefunctionality using behavioral moduls.

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Design Flow Summary

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The Design Manager/Flow Engine

takes EDIF netlist, XNF or PLD filesfrom your design tool and fits them

onto devices.

You can select a specific device orlet the Design Manager select a

device for you, based on the most

economical solution that will satisfythe functional and timing parameters

of the design.

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GENERATEDREPORTS

By default the fitter produces the following

significant output files:

Fitting report (design_name.rpt)lists summary

and detailed information about the logic and I/O

pin resources used by the design, including the

pinout, error and warning messages, and

Boolean equations representing the

implemented logic.

Static timing report (design_name.tim)

showsa summary report of worst-case timing for all

paths in the design; optionally includes a

complete listing of all delays on each individual

path in the design.

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Guide file (design_name.gyd) contains allresulting pinout information required toreproduce the current pinout if thepinfreeze option is specified during the nextinvocation of the cpld command for the samedesign name. (The Guide file is written onlyupon successful completion of the fitter.)

Programming file (design_name.jed forXC9000) is a JEDECformatted (9k)programming file to be down-loaded into thecpld device.

Timing simulation database (design_name.nga)a binary database representing theimplemented logic of the design, including alldelays.

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SIMULATIONCONCEPT

Timing Simulation

The Design Manager optionally producestiming simulation data when you implement

your design, and produces either an EDIF,VHDL or Verilog HDL formatted netlistfor your simulator

*VHDL = VHSIC hardware descriptionlanguage

*VHSIC = very-high-speed integratedcircuits

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ELEMENTLOGICINCOMPUTERLOGIC Clock

Clock is the frequency of the processor atwhich its running.

The standard unit is hertz (Hz); most people

today use GHz and MHz. Generally, within the same CPU series, higher

processor clock speed means fasterprocessing time.

The technical term for processor clock is the

speed, in which a single atomic action can beperformed. Hence a 1GHz CPU can evaluate a single NAND

1 billion time a second.

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Positive edge

triggeredNegative edge

triggered

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CLOCK FUNCTION

In a synchronous digital system, the clocksignal is used to define a time reference forthe movement of data within that system.

Since the data signals are provided with atemporal reference by the clock signals, theclock waveforms must be particularly cleanand sharp.

Finally, the control of any differences in thedelay of the clock signals can severely limitthe maximum performance of the entiresystem.

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GATEDFLIP-FLOP:

SR Flip-flopD Flip-flop

Master-slave flip-flopJK Flip-flop

OBE TECHNIQUE: ONE MINUTE PAPER

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FLIP-FLOP

In electronics, a flip-flopor latchis acircuit that has two stable states and canbe used to store state information.

The circuit can be made to change stateby signals applied to one or more controlinputs and will have one or two outputs.

Flip-flops and latches are a fundamentalbuilding block of digital electronicssystems used in computers,

communications, and many other types ofsystems.

Flip-flops and latches are used as data storageelements.

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SR FLIP-FLOP

Symbol for active

high flip-flop

Symbol for active

low flip-flop

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SR FLIP-FLOP

It can store either a binary number 0 or 1 andthe circuit has two states known as SETandRESET.

When a flip-flop is flip to the set (where itstores a binary 1) or flop to the reset (where itstores the binary 0), the output of the circuitwill remain (Latched / locked) as long as it isbeen power supplied.

SR flip-flop can be construct using both NAND

or NORgates.

NAND GATE ACTIVE LOW

NOR GATE ACTIVE HIGH

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SR FLIP-FLOP

Active High SR Flip-flop Active Low SR Flip-flop

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SR FLIP-FLOP

Operation table for active high and active low SRFlip-flop:

S R

Operation

for activehigh

Operation

for activelow

0 0 hold invalid

0 1 reset set

1 0 set reset

1 1 invalid hold

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D FLIP-FLOP

Logic symbol for D Flip-flop

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D FLIP-FLOP

D flip-flop is known as Delay or Data flip-flop

because of its ability to store data and transfer theinformation after receiving the pulse.

It is called the D flip-flop for this reason, since the

output takes the value of the D input or data input,

and delays it by one clock cycle. D Flip-flop can be constructed using either SR or

JK flip-flop by connected with the inverter between

the input S and R, or J and K input.

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D FLIP-FLOP

D flip-flop schematic

CLK D Qt+1

0 0

1 1

Truth table for D flip-flop:

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MASTER-SLAVEFLIP-FLOP

Logic diagram

A master-slave flip-flop is constructed from twoseparate flip-flops.

One circuit serves as a master and the other asa slave.

The master flip-flop is enabled on the positiveedge of the clock pulse CP and the slave flip-flop

is disabled by the inverter.

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MASTER-SLAVEFLIP-FLOP

When the pulse returns to 0, the master flip-flop is disabled and the slave flip-flop is enabled.

The slave flip-flop then goes to the same stateas the master flip-flop.

Timing relationship in a master slave flip-flop:

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JK FLIP-FLOP

Logic symbol for JK flip-floppositive edge triggered

Logic symbol for JK flip-flop- negative edge triggered

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JK FLIP-FLOP

JK flip-flop operation is similar to the SR flip-flop operation. The only difference is the flip-flop does not have the forbidden or invalid state.

The truth table for both flip-flop are mostly thesame, except when the given input of J = K = 1,the flip-flop will be in the toggle state.

Toggle is a condition where the output of a flip-flop will invert from 0 to 1 and vice versa atpositive or negative clock edge triggered.

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JK FLIP-FLOP

Operation table for JK Flip-flop

J K Operation

0 0 Hold0 1 Reset

1 0 Set

1 1 Toggle

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FLIP-FLOPAPPLICATIONS

Shift Register

Binary Counter

Sequence Counter

Sequential Magnitude ComparatorBCD to Seven Segment Decoder

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SHIFTREGISTER

A shift register is a cascadeof flip-flops,sharing the same clock, which has the output ofany one but the last flip-flop connected to thedata input of the next one in the chain,

resulting in a circuit that shifts by one positionthe one-dimensional bit array stored in it,shifting in the data present at its input andshifting out the last bit in the array, when

enabled to do so by a transition of the clockinput.

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SHIFTREGISTERUSINGJK FLIP-FLOP

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SHIFTREGISTEROPERATION

Timing Diagram

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BINARYCOUNTER

A Counter is a device, which stores

(and sometimes displays) the number

of times a particular event has

occurred, often in relationship to aCLOCK Signal.

In electronics, counters can be

implemented quite easily usingmemory devices such as Flip-flops.

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COUNTER

Kinds of counter

Asynchronous (ripple) counter

Synchronous counter

Decade counter Up/down counter

Ring counter

Johnson counter

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ASYNCHRONOUS(RIPPLE) COUNTER

Schematic:

An asynchronous (ripple) counter is a single JK-type flip-flop, with its J (data) input fed fromits own inverted output.
http://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Flip-flop_(electronics)

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This circuit can store one bit, and hence cancount from zero to one before it overflows(starts over from 0).

This counter will increment once for every clockcycle and takes two clock cycles to overflow, so

every cycle it will alternate between a transitionfrom 0 to 1 and a transition from 1 to 0.

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You can continue to add additional flip-flops,always inverting the output to its own input, andusing the output from the previous flip-flop asthe clock signal.

The result is called a ripple counter, which cancount to 2n-1 where n is the number of bits (flip-flop stages) in the counter.

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SYNCHRONOUSCOUNTER

A simple way of implementing the logic for each bit

of an ascending counter is for each bit to togglewhen all of the less significant bits are at a logic

high state.

For example, bit 1 toggles when bit 0 is logic high;

bit 2 toggles when both bit 1 and bit 0 are logichigh; bit 3 toggles when bit 2, bit 1 and bit 0 are all

high; and so on.

Synchronous counters can also be implemented

with hardware finite state machines, which aremore complex but allow for smoother, more stable

transitions.

Hardware-based counters are of this type.
http://en.wikipedia.org/wiki/Finite_state_machinehttp://en.wikipedia.org/wiki/Finite_state_machine

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DECADECOUNTER

A decade counter is one that counts in decimal

digits, rather than binary.

The latter type of circuit finds applications in

multiplexersand demultiplexers, or wherever a

scanning type of behavior is useful

The decade counter is also known as a mod-

counter when it counts to ten (0, 1, 2, 3, 4, 5, 6,

7, 8, 9).

A Mod Counter that counts to 64 stops at 63because 0 counts as a valid digit.
http://en.wikipedia.org/wiki/Multiplexerhttp://en.wikipedia.org/wiki/Multiplexer

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UP/DOWNCOUNTER

A counter that can change state in either direction,

under the control of an up/down selector input, is

known as an up/down counter.

When the selector is in the up state, the counter

increments its value. When the selector is in the

down state, the counter decrements the count.

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RINGCOUNTER

A ring counter is a shift register(a cascade

connection of flip-flops) with the output of the last

one connected to the input of the first, that is, in a

ring.

Typically, a pattern consisting of a single bit is

circulated so the state repeats every n clock cycles

if n flip-flops are used.

It can be used as a cycle counter of n states.
http://en.wikipedia.org/wiki/Shift_registerhttp://en.wikipedia.org/wiki/Flip-flophttp://en.wikipedia.org/wiki/Flip-flophttp://en.wikipedia.org/wiki/Flip-flophttp://en.wikipedia.org/wiki/Flip-flophttp://en.wikipedia.org/wiki/Shift_register

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JOHNSONCOUNTER

A Johnson counter (or switchtail ring counter,

twisted-ring counter, walking-ring counter, orMoebius counter) is a modified ring counter, wherethe output from the last stage is inverted and fedback as input to the first stage.

The register cycles through a sequence of bit-patterns, whose length is equal to twice the lengthof the shift register, continuing indefinitely.

These counters find specialist applications,including those similar to the decade counter,

digital-to-analog conversion, etc. They can be implemented easily using D- or JK-

type flip-flops.

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BCDTO7 SEGMENTDECODER

7-segment LED(Light Emitting Diode) or LCD(Liquid Crystal) displays, provide a veryconvenient way of displaying information ordigital data in the form of numbers, letters oreven alpha-numerical characters and they consist

of 7 individual LED's (the segments), within onesingle display package.

7-Segment Display Format

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TRUTHTABLEFORA7-SEGMENTDISPLAY

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BINARYCODEDDECIMAL(BCD)

Binary Coded Decimal(BCD or "8421" BCD)numbers are made up using just 4 data bits (a nibbleor half a byte).

BCD numbers only range from 0 to 9, with thebinary number patterns of 1010 through to 1111 (A

to F) being invalid inputs for this type of display andso are not used as shown below.

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BCD TO7-SEGMENTDECODER

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BCD TO7-SEGMENTDECODER

An example of the 4-bit BCD input (0100) representing the number 4 is

given below:

ec 303 chapter 2

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