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DynamicMulti-ParameterResponseModelforSEEDAnalysis

ConferencePaper·November2015

DOI:10.1109/EMCCompo.2015.7358328

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Dynamic Multi-Parameter Response Model

for SEED Analysis

Mart Coenen

EMCMCC, the Netherlands

mart.coenen@emcmcc.nl

Ming Ye,

Huawei Technologies Sweden AB

ming.ye@huawei.com

Huichun Yu

Huawei Technologies Ltd, China

yuhuichun@huawei.com

Abstract — System Efficient ESD Design (SEED) [1] at present

requires static response data from the devices and circuitry used

along the protection chain, typically from the point of entry at the

PCB boundary i.e. connector up to the circuit on-chip to be

protected. On this path there may be external ESD protection i.e.

voltage clamping, interconnect path delay with specific

transmission line properties, package design, on-chip protection

design all with parasitic layout effects and ultimately the on-chip

circuit(s) to be protected, being unpowered or powered.

The present way of using transmission line pulse (TLP) [2-4] to

obtain the response parameters is inadequate as only the averaged

I/V response parameters are used after 70% of the TLP pulse

width used. With most commercially available TLP testers the

bandwidth used (to obtain these I/V parameters at typ. 70 ns) is

also insufficient to gather the full SEED information required.

For the multiple SEED applications to be implemented,

dynamic response parameters are needed in time and frequency

domain, as the protection device response parameters are affected

by the presence of RF energy e.g. with smart phone and other

wireless appliances. Furthermore, the dynamic response

parameters are a function of the DC bias voltage applied i.e.

devices being powered or unpowered as well as temperature.

In this 1st paper constraints and ideas are given to gather the

multi-dimensional response parameters together with their

rationales. At the end of the paper some examples will be

presented. Future parts will contain data analysis, model building

and model validation.

Keywords — System efficient ESD design, SEED, transmission

line pulse, TLP, RF, time - frequency domain, dynamic response,

multi-parameter responses

I. INTRODUCTION

Today’s ICs are becoming much more vulnerable to ESD due to the process shrinking e.g. CMOS below 24 nm, on the one hand and the increase of speed e.g. ≥ 100 Gb/s, using exotic 3-5 element processes on the other hand. At the appliance or product boundary, the electro-static discharge (ESD) [7, 8], electrical overstress (EOS) or cable discharge event (CDE) requirements remain unaffected. Neither of the requirements: ESD, EOS and CDE at the device level are legally enforced but the result of negotiations between IC-suppliers and IC-users.

For ESD device characterization the HBM [5] and CDM [6] test methods are formally published with their requirements and classifications as where TLP testing is used as an internal qualification procedure for interrogation, product enhancement and verification. At the appliance or product level the legally

enforced IEC 61000-4-2 [7] applies or the ISO 10605 [8] for specific automotive applications.

Nanometer CMOS circuits without any on-chip ESD protection can handle only a few volt before either an insulation breakdown or thermal overheating of the interconnect results. I/O-pad or supply pin ESD protection circuits serve as a primary on-chip protection for the internal circuit but are still unable to provide sufficient protection against the boundary appliance of product ESD requirements.

Additionally, by putting protective circuits and circuits to be protected in parallel the overall performance of the combined circuitry is affected as the response time may be altered due to the added capacitance. The circuit to be protected may initially clamp earlier, faster or at a lower voltage level in such a way that the added protective circuit isn’t able to respond at all. As the process dependent development of ESD, EOS and CDE protection structures is carried out in splendid isolation of the on-chip circuitry to be protected some incompatibilities may result after integration.

One step further is the integration of off-chip protection and clamping structures w.r.t. the boundary ESD protection structures on-die near the pads. Their placement, size and response parameters determine their ‘System Efficient ESD Design’ usefulness which needs to become more than a trial-and-error process. Unfortunately, the PCB structure, routing and component placements, typically placed near to the I/O connector concerned, plays an important role in the overall protection and clamping performance of such off-chip devices. As such, the data sheet of an off-chip i.e. on-PCB protection and clamping device only resolves a small part of the total ESD protection equation.

Last but not least, the protection and clamping performance of a device is also determined by the presence of RF, temperature and other parameters which do need to be included in the overall simulation environment to assure SEED.

The approach taken is to derive I/V versus time characteristics over the full duration time of an ESD, EOS or CDE event, in particular the initial (sub-nanosecond to nanosecond) part of the pulses applied. The presence of RF, temperature and light affect the clamping voltage to such an extent that the trigger and clamping voltage as set just above the nominal operational voltage is reduced such that these devices become dissipative even under nominal operating voltage conditions from which device i.e. product damage results even without ESD or EOS.

II. CLAMPING PERFORMANCE

From most of the clamping and protection devices it is known that the initial clamping response to ESD, EOS, CDE using TLP is cumbersome to measure, which was one of the reasons why only the averaged I/V values after 70% of the pulse duration were measured. If one assumes a 100 ns rectangular

TLP pulse, the I/V response at 70 ns ((πτr)-1 = 4.5 MHz) can be measured accurately using a 300 MHz bandwidth system. Skew of a few sub-nanosecond between I(t) and V(t) will hardly affect the result measured and even propagation delay between the point of reference measured against the position of where the clamping device is located hardly plays a role. Also a temporarily saturation of an inductive current probe during the initial clamping process could be ignored.

When the I(t) and V(t) values are required over the full time range from sub-nanoseconds up to microseconds, the analogue bandwidth needed is extended up to several GHz. This then requires an oscilloscope with e.g. 20 Gs/s, appropriate voltage and current probes and a fast TLP generator. Furthermore, the de-skewing algorithms to be used has to put the plane of reference at which the I- and V-values are taken at the right position. Literature already indicates the use of a broadband VSWR-bridge to derive the current and voltage (as a function of time) from the forward and reflected waves values applied rather than using separate voltage and current probes at spatial different locations. Time related data de-embedding, from the scattering data is then a hindrance to be taken, but most suited and known, from measurement techniques in the frequency domain.

The TLP signal stems from a 50 Ω transmission line, thus a

50 Ω source (rather than the 500 Ω or the HMM case). The TLP pulse rise-time can be as steep as 10 to 100 ps and the TLP pulse duration is determined by the length of transmission lines

stacked together e.g. 10 ns up to 1 µs. With these rise times, a protection device which represents 1 pF could yield an initial discharge current: IC = C·dU/dt = several hundred Amps using a test level of 1 kV. However, this initial discharge current is limited by the source impedance, being the characteristic

impedance of the coaxial cable (= 50 Ω). This limits the peak

current of the TLP pulse to: 1 kV/50 Ω = 20 Amps max.

First comes, first served. The protection device which triggers and clamps first will most likely take away the trigger and clamping conditions for the second device. As such, a single device may perform nicely after 70% of the pulse width applied as a standalone device but will not respond when put into parallel with another devices which might overall have less performance but triggers and clamps faster.

III. DEVICE CHARACTERIZATION

The device characterization can and needs to be done both in time and frequency domain or a combination thereof. As the EFT and ESD transient phenomena cover the frequency band from DC up to several hundred MHz (EFT, figure 1) or even several GHz (ESD), these time domain signals are hard to combine with RF signals as the levels of these RF signals in application will be about ten volts p-p, see figure 6. When TLP is used with a characteristic impedance of 50 Ω together with an RF signal at 50 Ω these could be combined. However, the nature of the transient and RF signals are so different: TLP up to kV’s

at several amps and tens of volts p-p for the RF signal, such that a RF signal combiner isn’t appropriate for the both of them. If the load, i.e. protection device impedance would be known, a fork network could be used but the dynamic impedance of the protection device is, in particular, part of problem.

Figure 1 – Frequency spectrum envelope of EFT (5/50 ns) pulses

at 200 volt measured in 100 kHz bandwidth

IIIa. Device characterization, static

The common way to characterize protection devices or non-linear devices is to use a source meter (SMU). The current or voltage is swept through its (DC) range while the voltage across and the current through is being measured. This setup can easily be extended by using an RF Bias-Tee (photo 1, right) by which an RF signal (from a VNA or RF generator, not shown) can be superimposed onto the DC I/V characterization signals.

Photo 1 - DC I/V characterization of clamping devices using a SMU

Figure 2 - DC I/V characterization of clamping devices setup

IIIb. Device characterization, frequency domain

Instead of using an RF signal source, a vector network analyzer (VNA) can be used to measure the RF impedance over frequency while applying a DC current (e.g. from the SMU) to

the device under test. A diagram of the total clamping voltage test setup is given in figure 2.

Figure 3 - DC clamping voltage characteristic at 10 volt RF

With this setup, the DC I/V characteristics can be measured while influenced by RF, see figure 3 for a 24 volt TVS. As can be seen, the TVS clamping voltage can be halved by adding an RF voltage across its junction. Considering the DC I/V clamping device test setup of photo 1, a total series inductance of about 80 nH is achieved by BNC-to-banana plug adapter which together with the stray capacitance of the TVS gives a resonance in the frequency range of 1 – 10 MHz. The affected clamping voltage then enters the nominal supply voltage range (to be protected), dissipates and then burns-out. The decline of the affected clamping voltage does reduce at higher forward biasing currents because: higher forward current means less impedance and the temperature increase of the diode. The influence of the DC biasing to the device under test (e.g. 1N400x) can be measured in the frequency domain, figure 4. Here too, the diode’s forward impedance is heavily dependent on the forward current applied. From 0 to 1 mA the diode’s depletion capacitance is altered which affects the impedance also at the higher frequencies (upper line).

Figure 4 - RF impedance diode DC bias:

1: 0 mA, 2: 10 mA, 3: 30 mA, 100 mA, 300 mA, 4: 1 Amp,

Y-scale: abs. impedance 10 dBΩ/div

Even from simple devices like diodes 1N400x, TVS or LEDs (as used in [9]), the impedance responses in either time or frequency domain from 1 MHz to 3 GHz, see figures 3, 4 and 5 can be measured. It can also be seen that the interaction between the RF signal applied and/or DC biasing applied to the device is

prominent. The LED already has a relative high inner series resistance (~ 30 Ω, = 30 dBΩ) compared to the diode (~ 1 Ω, = 0 dBΩ), when put in forward.

Figure 5 - RF impedance LED, DC bias:

1: 0 mA, 2: 1 mA, 3: 3 mA, 10 mA, 30 mA, 100 mA, 4: 300mA

Y-scale: abs. impedance 5 dBΩ/div

It is true too that at higher frequencies the RF voltage across the non-linear device under test will diminish due to the stray capacitance across the pn-junction of the device. As such, substantial interaction can be observed till about 300 MHz but less above. This stray capacitance condition provides a 1st-order decline of the RF voltage across the pn-junction of the diode and is typically valid in a damped 50 Ω measurement environment. In real applications, the trace and plane impedances, see figure 6, together with the lead and/or device length of the protection device will cause higher order effects w.r.t. the PDN impedance,

typically « 50 Ω (= 34 dBΩ), and resonances with proper quality factors may result, thus high local voltages or currents.

Figure 6 - Impedance resonances occurring in-between

2-layers of a small unpopulated PCB

The impedances achieved will be fully dependent upon the design of the power distribution network (PDN), its application and the decoupling elements used. When only reactive elements are used in the PDN, the quality factors at resonance will be substantial: e.g. with wide copper traces/ planes and many ceramic multilayer capacitors. When parallel RC-networks are used which match to the PDN trace/ plane impedances, the quality factor at these resonances can be diminished to unity or

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less over a very broad frequency range, thus lower the peak voltages.

When one wants to combine an EFT or TLP ESD pulse (both having a 50 Ω source impedance) with an RF disturbance, care shall be taken to protect the output of the RF source. One wants to have an as low as possible insertion loss for both RF and impulse signals towards the device under test. On the other hand one needs to have an as high as possible insulation between the input ports over a very broad frequency range. Most RF power splitters only provide a good isolation between the input ports

when the output is properly matched to 50 Ω. Proper attenuation shall also be given to RF signal generators which typically use automatic level control (ALC) on their RF output.

Figure 7 - Combined setup of TLP testing with RF (> 1 GHz)

HPF = high-pass filter

IIIc. Device characterization, time domain

If an RF signal generator is used followed by an RF power amplifier without a VSWR bridge and power sensor to control the forward output voltage in closed loop, the isolation requirement is less stringent up until the peak voltage level (resulting from the TLP) that the RF amplifier output can handle: before damage or becoming too non-linear. Again, the safe operation area (SOA) impulse withstand parameters for any RF power amplifier at its outputs is not specified and thus these properties have to be obtained by trial and error, or the likelihood of damage occurrence needs to be avoided by providing proper protection circuits which do not affect the nominal RF signals required. An example of an EFT or TLP impulse tester and RF combiner/ protection/ high-pass circuit is given in figure 7. The rationale for this test setup is the fact that the TLP signal energy is limited above 1 GHz, due to the low repetition rate, in combination with the input port-to-port isolation of the RF signal combiner.

By using a fast digitizing oscilloscope in parallel to the device under test, figure 8, the instantaneous voltage across and the impulse current through the device can be measured simultaneously. From these two parameters I and V, after de-embedding and de-skewing, the delayed response can be measured as a function of the discharge voltage applied. Furthermore, the peak voltage across the device can be measured during the rise time of the current i.e. the dynamic impedance can be derived from these measurement results.

The voltage versus current de-embedding and de-skewing is achieved by using resistive loadings of which the I/V relation and delay along the measurement chain are known. With these optimized settings or de-embedding algorithms, the response of

a clamping device can be measured with or without RF applied in parallel to the impulse.

Figure 8 - Combined setup of TLP testing with RF (> 1 GHz) extended with a

fast oscilloscope with current and voltage probe

The dynamic response test setup is now complete w.r.t. the ability to measure the device response under any stress condition. When the SMU is DC biasing the device (in pulsed mode to prevent i.e. minimize self-heating), the oscilloscope can be triggered accordingly. For the dynamic current measurements a Tektronix CT-1 current probe is used which has a bandwidth up to 1 GHz but only a current handling capability up to 12 amps.

Initially lacking a TLP tester, an EFT generator has been used with these response measurements. Measurements have been performed with low and high voltages and with various devices. The voltage (yellow) and current (red) response of the TVS @ 200 volt TLP voltage can found in figure 9. The same response under 600 volt TLP stress is given in figure 10.

Figure 9 - TVS I/V response @ 200 volt, yellow = voltage, red = current

What can be seen from figure 9 is that even with an EFT pulse, with a fairly slow voltage rise time of about 5 ns, a delay of about 10 ns can be noted between the current peak and the voltage peak. The ratio between the peak voltage: 71,6 volt for a 24 volt TVS device and the peak current (using a 10 dB RF attenuator in-between) thus 3,24 amps leads to an equivalent

absolute dynamic impedance of 22 Ω. Furthermore, it can be noted that the device’s clamping response (after triggering) is quite good as the half-with time of an EFT pulse is about 50 ns. To be noted is that it takes about 10 ns for the TVS to respond i.e. reach its maximum current in-between the circuit which needed the clamping protection may have died already.

Figure 10 - TVS I/V response @ 600 volt, yellow = voltage, red = current

Similar to the 200 volt case, the current is lacking behind

the voltage for nearly 15 ns, the peak voltage has increased to

242 volt and the peak current has become 10 amps. This leads

to an equivalent absolute impedance of 24,2 Ω, slightly higher

than in the previous case.

Applying the same stress to a LED [9], as used earlier with

the frequency dependent impedance analysis reveals that the

delay between current and voltage vanishes, figure 11.

Figure 11 - LED I/V response @ 200 volt, yellow = voltage, red = current

With a LED the main voltage and current wave shapes

coincide, probably dominated by the equivalent resistance that

LEDs are representing. Different from the TVS response is the

longer lasting overvoltage level. With these short high current

EFT pulse bursts, the LED lights up with a 3 Hz burst interval

of the EFT generator.

Also for this case, the stress voltage is increased to 600 volt

and the response is measured once more, figure 12.

Figure 12 - LED I/V response @ 600 volt, yellow = voltage, red = current

With this last case: LED @ 600 volt EFT, the full EFT pulse

width can be found back with the voltage waveshape as where

the current waveshape is limited in width. Different from the

200 volt case is the loss of the clamping voltage staircase,

present with figure 11, but gone with figure 12. Furthermore, a

small delay (≤ 5 ns) is introduced between the current and the

voltage waveshape. W.r.t. the total test setup used, nothing has

been changed other than the adjustment of the EFT generator’

output voltage.

A fair intermediate conclusion may be that the clamping

device response delay is dependent on the impulse voltage

applied which increases with higher impulse voltages.

If all these current/voltage ratios are measured after 70% of

the pulse duration e.g. at 70 ns, the I/V ratio responses found

are completely different compared to what is happening during

the first few ns i.e. the beginning where the device is not yet

clamping to a full extend.

Figure 13 - TVS I/V curves vs time; Courtesy HPPI

Figure 14 - TVS I/V curves vs time; Courtesy EMCESD

In the meanwhile TLP manufactures: HPPI, EMCESD

have put effort in representing the I/V/t-response data in 3D

plots while using extended measurement bandwidth, see figures

13 and 14, which confirm the presented findings. Voltage and

current probe bandwidths of several GHz are required

combined with sampling rates of 20 Gs/s or more.

CONCLUSIONS

The trigger and clamping voltage and the dynamic impedance of (clamping) diodes can be heavily affected by multiple parameters which also include RF across their pn-junction(s), DC-biasing and temperature.

At low bias current the clamping voltage level of the protection device can be affected by the presence of RF and specifically the local RF amplitude across the pn-junction. In the high current/conduction mode the impedance is determined by the dynamic resistance of the protection device but still in series with the physical stray inductance of the device and interconnect used.

Both external as internal overvoltage protection devices represent LC-networks which are used on signal and supply lines with varying impedances due to resonances, in particular at the higher frequencies. Specific device resonant frequencies may be excited by which higher voltages across their pn-junction(s) may arise.

Looking at the responses of single protection devices under test, the time domain and frequency domain impedance is determined by the encapsulation i.e. casing and the thermal pad sizes of the protection device used as these determine the stray inductance, capacitance and thermal behavior of these protection devices.

At high frequency (> 300 MHz) the RF impedance behavior of the protection device is hardly affected by the dynamic state in which the protection device is in and these basic parasitic parameters determine the first few nanoseconds of the device response in the time domain (ignoring the charging process w.r.t. device triggering).

A conclusion may also be that the clamping device response

delay is dependent on the impulse voltage applied which then

increases with higher impulse voltages.

If the current/voltage ratio is measured after 70% of the

pulse duration or after 70 ns, I/V ratio responses found are

completely different compared to what is happening during the

first few ns i.e. at the beginning where the device is not yet

triggered nor clamping to a full extend. A revision of the present

TLP standard is therefore recommended.

No international accepted nor draft standardized test methods could be found on the characterization of overvoltage protection circuits and clamping diodes which includes RF phenomena. Each well-respected protection device manufacturer (external devices) and silicon foundry (IC-process related on-die protection) is doing these developments in their own way.

FUTURE WORK

From this initial work it has become clear that responses to

overvoltages by protection devices are no simple functions but

ones which are affected by many parameters which contribute

to these responses.

The 1st step was to get COTS TLP manufactures convinced

to provide equipment by which comparable measurements can

be taken which then can feed better device modelling. When the

response relations become known, work will be carried out on

deriving behavior models to be used with enhanced circuit

simulations to enable a better forecast of SEED responses.

The next steps are further analysis of the RF influence on

the clamping devices as well as an analysis of the impact of the

impulse voltage on the response delay of the devices which was

one of the initial targets of this investigation.

ACKNOWLEDGMENT

This work has been done in close cooperation with Huawei Sweden and China. The research project is supported by the Dutch Ministry of Economic affairs (RVO).

REFERENCES

[1] White Paper 3: System Level ESD, Part I: Common Misconceptions and Recommended Basic Approaches, Part II: Implementation of Effective ESD Robust Designs

[2] ANSI/ESD STM5.5.1-2008 Electrostatic Discharge Sensitivity Testing – Transmission Line Pulse (TLP) – Component Level

[3] ANSI/ESD SP5.5.2-2007 Electrostatic Discharge Sensitivity Testing - Very Fast Transmission Line Pulse (VF-TLP) - Component Level

[4] IEC 62615 ed1.0, Electrostatic discharge sensitivity testing - Transmission line pulse (TLP) - Component level

[5] JEDEC JESD22-A114D Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM.)

[6] JEDEC JESD22-C101C Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[7] IEC 61000: Electromagnetic compatibility (EMC) Part 4-2: Testing and measurement techniques Electrostatic discharge immunity test.

[8] ISO 10605, Road vehicles -- Test methods for electrical disturbances from electrostatic discharge

[9] T. Li, J. Maeshima, H. Shumiya, D. J. Pommerenke, T. Yamada, and K. Araki, “An application of utilizing the system-efficient-ESD-design (SEED) concept to analyze an LED protection circuit of a cell phone,” in Proc. IEEE EMC Symp., 2012, pp. 346–350

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