dsp c5000 chapter 3 addressing modes copyright © 2003 texas instruments. all rights reserved

DSP C5000DSP C5000

Chapter 3Chapter 3

Addressing ModesAddressing Modes

Copyright © 2003 Texas Instruments. All rights reserved.Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 2

ObjectivesObjectives

Present the main addressing modes and Present the main addressing modes and allocation of sectionsallocation of sections

Present the main addressing modes of Present the main addressing modes of the C54 familythe C54 family

Present the main addressing modes of Present the main addressing modes of the C55 familythe C55 family

Explain how to use these addressing Explain how to use these addressing modesmodes

Do exercises to practice using the Do exercises to practice using the different addressing modesdifferent addressing modes


ESIEE, Slide 3

OutlineOutline

Generalities on addressing modesGeneralities on addressing modes

C54C54xx

C5C55x5x


ESIEE, Slide 4

Addressing Modes: What are the Problems?Addressing Modes: What are the Problems?

Specify operands per instruction:Specify operands per instruction: A single instruction can access several A single instruction can access several

operands at a time thanks to the many operands at a time thanks to the many internal data busses,internal data busses,

But how do we specify many addresses using But how do we specify many addresses using a small number of bits? a small number of bits?

Repeated processing on an array of data:Repeated processing on an array of data: Many DSP operations are repeated on an Many DSP operations are repeated on an

array of data stored at contiguous addresses array of data stored at contiguous addresses in data memory.in data memory.

There are cases where it is useful to be able There are cases where it is useful to be able to modify the addresses as part of the to modify the addresses as part of the instruction (increment or decrement).instruction (increment or decrement).


ESIEE, Slide 5

Main Addressing Modes of C5000 FamilyMain Addressing Modes of C5000 Family

ImmediateImmediate addressing addressing AbsoluteAbsolute addressing addressing DirectDirect addressing addressing IndirectIndirect addressing by register addressing by register

Support for circular indirect addressingSupport for circular indirect addressing DefinitionDefinition

Access to Memory Mapped Registers Access to Memory Mapped Registers MMRsMMRs


ESIEE, Slide 6

Allocating SectionsAllocating Sections


ESIEE, Slide 7

ExampleExample

RAM

x[3]

RAM

yC5000CPU

System Diagram

DROM

init[3]

EPROMEPROM

(code)(code)

y = x1 + x0 + x2Algorithm

How do we allocate the proper sections?

Allocate sections (code, constants, vars) Setup addressing modes Add the values (x1 + x0 + x2) Store the result (y)

Procedure


ESIEE, Slide 8

Writing relocatable codeWriting relocatable code The The programmerprogrammer should not have to give the should not have to give the

exact addressexact addresseses:: where to read the code in program memory,where to read the code in program memory, where to read the data in data memory.where to read the data in data memory.

The assembler allows to use symbolic addressesThe assembler allows to use symbolic addresses.. The assembler and the linker work with COFF The assembler and the linker work with COFF

files:files: COFF = Common Object File Format.COFF = Common Object File Format. In COFF files, specialized sectionsIn COFF files, specialized sections are used are used for code, for code,

variables or constants.variables or constants. The programmer specifies in a command file for the The programmer specifies in a command file for the

linker where the different sections should be linker where the different sections should be allocated in the memory of the system.allocated in the memory of the system.


ESIEE, Slide 9

Definition of SectionsDefinition of Sections

Different sections for code, vars, constants. Different sections for code, vars, constants. The sections can be initialized or not.The sections can be initialized or not.

An initialized section is filled with code or An initialized section is filled with code or constant values.constant values.

An uninitialized section reserves memory An uninitialized section reserves memory space for a variable.space for a variable.

The sections can have default names or The sections can have default names or names given by the programmer.names given by the programmer.


ESIEE, Slide 10

Definition and names of SectionsDefinition and names of Sections The programmer uses special The programmer uses special directives directives to to

identify the sections. identify the sections.

code VariablesCode or

constants

Named sections, name given by user

.sect .usect

Unnamed sections,

default name.text .data .bss

Initialized sectionsUnitialized sections,

reserve space for data


ESIEE, Slide 11

ExampleExample of sections of sections

Initialized named section: Initialization Initialized named section: Initialization of constants. Definition of address tblof constants. Definition of address tbl

Uninitialized named section: x[3], y[1], Uninitialized named section: x[3], y[1], Definition of address x and y.Definition of address x and y.

Initialized named section: codeInitialized named section: code

RAM

x[3]

RAM

y54xCPU

System Diagram

DROM

tbl[3]

EPROM

code

How are these sections placed into the memory

areas shown?

x .usect "vars",3 y .usect "result",1

.sect ”init" tbl .int 1,2,3

.sect “code”


ESIEE, Slide 12

C54x Addressing ModesC54x Addressing Modes


ESIEE, Slide 13

Format of Data and Instructions, Internal Format of Data and Instructions, Internal Busses of the C54x FamilyBusses of the C54x Family

In the C54x DSP, the data and program In the C54x DSP, the data and program memories are organized in 16-bit words. memories are organized in 16-bit words. Data busses have a 16-bit width.Data busses have a 16-bit width.

Data and instructions are generally of size Data and instructions are generally of size N=16 bits.N=16 bits.

Some instructions may take several 16-bit Some instructions may take several 16-bit words.words.

Some data operands may be double Some data operands may be double precision and occupy 2 words.precision and occupy 2 words.

Internal busses: 2 data read, 1Internal busses: 2 data read, 1 data writedata write


ESIEE, Slide 14

Terms from the User’s GuideTerms from the User’s Guide

Term What it means

Smem 16-bit single data memory operand

pmad 16-bit immediate program memory address (0 - 65,535) This includes extended program memory devices

dmad 16-bit immediate data memory address (0 - 65,535)

Ymem 16-bit dual data-memory operand used in dual-operand instructions. Read through C bus.

Xmem 16-bit dual data memory operand used in dual-operand instructions and some single-operand instructions. Read through D bus.

PA 16-bit port (I/O) immediate address (0 - 65,535)

src Source accumulator (A or B) dst Destination accumulator (A or B)

lk 16-bit long constant


ESIEE, Slide 15

Immediate Addressing Mode Immediate Addressing Mode ##

Instruction contains the value of the Instruction contains the value of the operand. Value is preceded by operand. Value is preceded by #.#.

Example:Example: Add the value 4 to the content of Add the value 4 to the content of

accumulator A.accumulator A. Useful for initializations.Useful for initializations. Long (16 bits) or short values:Long (16 bits) or short values:

For long values: instruction uses 2 words.For long values: instruction uses 2 words.

ADD ADD #4,A#4,A


ESIEE, Slide 16

Immediate Addressing Mode Immediate Addressing Mode ##

16 bit value16 bit value 2 words, 2 cycles2 words, 2 cycles Initialization of ARi for Initialization of ARi for

exampleexample

Short valueShort value 3, 5, 8, 9 bits constant3, 5, 8, 9 bits constant 1 word, 1 cycle1 word, 1 cycle To initialize short To initialize short

length registers or bit length registers or bit fields:fields: DP, ASM …DP, ASM …

Not always availableNot always available

Example:

STM #1234h,AR2Load AR2 with the value 1234h.

Example:

LD #6, DPLoad DP with the value 6.


ESIEE, Slide 17

ExampleExample:: MMR MMR (Memory Mapped Registers) (Memory Mapped Registers) and Immediate Addressingand Immediate Addressing

STM (STore to Memory-mappedregister) stores an immediatevalue to the specified MMR orScratch address.

#tbl is the 16-bit address of thefirst element of the array tbl.



.sect “code”

start: STM #tbl,AR1 STM #x,AR2

0000h

0060h 007F

MMRs

Scratch

MMR = Memory Mapped Registers

Scratch memory


ESIEE, Slide 18

Direct Addressing Mode Direct Addressing Mode @@

Direct addressing = random access from Direct addressing = random access from a specified base address.a specified base address. The instruction contains an offset relative The instruction contains an offset relative

to the base address.to the base address. The base address can be the beginning The base address can be the beginning

of a data memory page or the stack of a data memory page or the stack pointer.pointer. The data memory is virtually divided in The data memory is virtually divided in

512512 pages of 128 wordspages of 128 words (512x128 = 2 (512x128 = 21616)).. Data Page Data Page DPDP relative direct address relative direct address

CPL bit (ComPiler Mode bit) = 0 in ST1CPL bit (ComPiler Mode bit) = 0 in ST1 Stack Pointer Stack Pointer SPSP relative direct address relative direct address

CPL bit = 1 in ST1CPL bit = 1 in ST1


ESIEE, Slide 19

Data memory pagesData memory pages

Page 0

Data memory Hex

0000

0080

FFFF

0100

Addresses in Dec

0

128

256

65 535

Page 1

Page 2

Page 511

128 words

128 words

128 words

128 words

512 Pages


ESIEE, Slide 20


For DP relative mode: For DP relative mode: The 16 bit address is split into 9 MSB and The 16 bit address is split into 9 MSB and

7 LSB.7 LSB. The 7 LSB of the operand address are given The 7 LSB of the operand address are given

in the instructionin the instruction,, The 9 MSB are in the DP registerThe 9 MSB are in the DP register..

For SP relative modeFor SP relative mode The 7 bits given in the instruction are The 7 bits given in the instruction are

used as an offset from the SP to obtain used as an offset from the SP to obtain the addressthe address..

In both cases, only 7 bits are used in In both cases, only 7 bits are used in the instruction for the operand the instruction for the operand address.address.


ESIEE, Slide 21


Opcode I=0 dma

15 - 8 7 6 - 0

7-bit dma9-bit DP

InstructionInstruction

DP relative, CPL = 0DP relative, CPL = 0

AddressAddress

SP relative, CPL = 1SP relative, CPL = 1

16-bit Stack Pointer

7-bit dma+

16-bit Data Memory AddressAddressAddress

9-bit DPDP registerDP register

SP RegisterSP Register


ESIEE, Slide 22

Direct Addressing Mode Direct Addressing Mode @@, example, example

Page 0

Data memory Hex

0000

0080

FFFF

0100

Addresses in Dec

0

128

256

65 535

Page 1

Page 2

Page 511

128 words

128 words

128 words

128 words

0 1

127

Page 3 to 510

DP = 2DP = 2, page 2, page 2

Offset in the Offset in the instruction = instruction = 11

Address = 0101 Address = 0101 in hexadecimalin hexadecimal


ESIEE, Slide 23

Example Example

This instruction loads the upper9 bits of address x into DP (in ST0)

CPL = 0

To be sure that x and x+1 are in the same page: use Blocking.

LD @x+1,A ADD @x,A ADD @x+2,A



.sect “code”

start: STM #tbl,AR1 STM #x,AR2

LD #x,DP


ESIEE, Slide 24

Direct Addressing Mode Direct Addressing Mode @, DP relative@, DP relative When DP is initialized, it allows single-When DP is initialized, it allows single-

word single-cycle instructions with easy word single-cycle instructions with easy to understand symbols for addresses.to understand symbols for addresses.

Defines 512 pages (selected by the 9 bits Defines 512 pages (selected by the 9 bits of DP) of 128 words (selected by the 7 of DP) of 128 words (selected by the 7 bits in instruction) in data memory.bits in instruction) in data memory.

CPL is reset by:CPL is reset by: RSBX CPL ; CPL = 0 on resetRSBX CPL ; CPL = 0 on reset

Blocking Blocking of data in the same pageof data in the same page In the linker command file:In the linker command file:

.bss : > RAM BLOCK = 128.bss : > RAM BLOCK = 128 In the assembler fileIn the assembler file

.bss x, 2, .bss x, 2, 11 ; specify all variables in one page ; specify all variables in one page


ESIEE, Slide 25

Direct Addressing Mode Direct Addressing Mode @, SP relative@, SP relative

Used by the C compilerUsed by the C compiler Useful for stack based operationsUseful for stack based operations Controlled by the CPL bit. Set by:Controlled by the CPL bit. Set by:

SSBX CPLSSBX CPL


ESIEE, Slide 26

Indirect Addressing Mode Indirect Addressing Mode *ARi*ARi

Compatible with Compatible with pointerspointers in C.in C. 8 ARi8 ARi Auxiliary Registers to store the Auxiliary Registers to store the

addresses of the operands.addresses of the operands. They are They are used as pointers.used as pointers.

2 ARAU2 ARAU = Auxiliary Registers = Auxiliary Registers Arithmetic Units to realize operations Arithmetic Units to realize operations on the addresses stored in the ARi.on the addresses stored in the ARi.

1 operand (Smem) or 2 operands 1 operand (Smem) or 2 operands (Xmem, Ymem) can be specified by (Xmem, Ymem) can be specified by indirect addressing in 1 instruction.indirect addressing in 1 instruction.

Very efficient for DSP operations.Very efficient for DSP operations.


ESIEE, Slide 27

Indirect addressing mode Indirect addressing mode *ARi*ARi

AR0AR0 can be used as an index. can be used as an index. Support for Support for circularcircular addressing addressing

details in next slidesdetails in next slides Bit Reversed Bit Reversed BRBR addressing for FFT addressing for FFT ARi can be modified during the ARi can be modified during the

instructioninstruction The possible modifications or operations on The possible modifications or operations on

ARi depend on the number of operands ARi depend on the number of operands specified by indirect addressing in the specified by indirect addressing in the instruction.instruction.

Pointers (ARi) must be initialized before Pointers (ARi) must be initialized before use.use.


ESIEE, Slide 28

Circular buffer and addressing on C54xCircular buffer and addressing on C54x

Data Memory

Start_address = xxxxxxxxxxx00000

ARi

End_address = xxxxxxxxxxx11111

xxxxxxxxxxx00010

ARi BK

N=30=1 1 1 1 0


ESIEE, Slide 29

Circular addressing with C54xCircular addressing with C54x Circular indirect addressing mode: Circular indirect addressing mode: %%

*ARi-%, *ARi+%, *ARi-0%, *ARi+0%, *ARi-%, *ARi+%, *ARi-0%, *ARi+0%, *ARi(lk)%*ARi(lk)%

In dual operand mode Xmem, Ymem:In dual operand mode Xmem, Ymem: *ARi+0%*ARi+0% only valid mode only valid mode To perform a decrement, store a negative value To perform a decrement, store a negative value

in AR0.in AR0.

BKBK register: register: Stores the size N of the circular buffer.Stores the size N of the circular buffer. Must be initialized before use.Must be initialized before use. There may be several circular buffers at There may be several circular buffers at

different addresses at the same time but different addresses at the same time but with the same length.with the same length.


ESIEE, Slide 30

Limitations on Start Addresses of Circular Limitations on Start Addresses of Circular BuffersBuffers

If N is written on nb bits in binary, the If N is written on nb bits in binary, the start address must have its nb LSB at 0:start address must have its nb LSB at 0: Examples:Examples:

for N=32, 6 LSB of start address =0for N=32, 6 LSB of start address =0 for N=30, 5 LSB of start address =0for N=30, 5 LSB of start address =0

To access a circular buffer:To access a circular buffer: Initialize BK with N (nb bits)Initialize BK with N (nb bits) Choose 1 ARi as a pointerChoose 1 ARi as a pointer

The effective start address of the buffer is the The effective start address of the buffer is the value in ARi with its nb LSB at 0.value in ARi with its nb LSB at 0.

The end address = start addess +N-1.The end address = start addess +N-1.


ESIEE, Slide 31

Indirect Addressing: Indirect Addressing: ARi Specifications and ARi Specifications and Options for ModificationOptions for Modification

For a single operand Smem:For a single operand Smem: 16 possible options for Smem,16 possible options for Smem, 4 bits for the option + 3 bits for the ARi.4 bits for the option + 3 bits for the ARi. The address is specified by 4 + 3 = 7 bits.The address is specified by 4 + 3 = 7 bits.

For 2 operands Xmem, Ymem:For 2 operands Xmem, Ymem: Only 4 ARi can be used: AR2 to AR5.Only 4 ARi can be used: AR2 to AR5. Only 4 possible options for the operations Only 4 possible options for the operations

on the ARi.on the ARi. Each address needs 2 + 2 = 4 bits, so 2x4=8 Each address needs 2 + 2 = 4 bits, so 2x4=8

bits are necessary for the 2 addresses.bits are necessary for the 2 addresses.


ESIEE, Slide 32

Indirect Addressing Options for Indirect Addressing Options for ARi ARi modifications,modifications, Single operand Smem Single operand Smem

No Modification *ARn no modification to ARn

Option Syntax Action Affected by:

Absolute *(lk) 16-bit lk is used as an absolute address See Absolute Addressing

Pre-modify *ARn (lk) *(ARn+LK), ARn unchanged *+ARn (lk) *(ARn+LK), ARn changed *+ARn (lk)% *(ARn+LK), ARn changed - circular BK *+ARn pre-increment by 1, during write only

Bit-Reversed *ARn+0B post inc. ARn by AR0 with reverse carry AR0 *ARn-0B post dec. ARn by AR0 with reverse carry (=FFT size/2)

Circular *ARn+% post increment by 1 - circular BK *ARn-% post decrement by 1 - circular *ARn+0% post increment by AR0 - circular BK, AR0 *ARn-0% post decrement by AR0 - circular

Indexed *ARn+0 post increment by AR0 AR0 *ARn-0 post decrement by AR0

Increment / *ARn+ post increment by 1 Decrement *ARn- post decrement by 1


ESIEE, Slide 33

Indirect Addressing Options for Indirect Addressing Options for ARiARifor Double Operand Xmem and Ymemfor Double Operand Xmem and Ymem

No Modification *ARn no modification to ARn

Option Syntax Action Affected by:

Circular *ARn+0% post increment by AR0 - circular BK, AR0

Increment / *ARn+ post increment by 1 Decrement *ARn- post decrement by 1


ESIEE, Slide 34


There are latencies to consider:There are latencies to consider: no latencyno latency STM, MVDKSTM, MVDK 1 cycle1 cycle MVDM, MVKD, MVDDMVDM, MVKD, MVDD 2 cycles2 cycles STLM, ST, etcSTLM, ST, etc

ARi are read/modified in access phase, so the ARi are read/modified in access phase, so the debugger will appear to show ARs changing early.debugger will appear to show ARs changing early.

CMPT must = 0 (bit5, ST1)CMPT must = 0 (bit5, ST1) is 0 on resetis 0 on reset is forced to 0 with RSBX CMPTis forced to 0 with RSBX CMPT CMPT (Compatibility Mode Bit) = 1 allows CMPT (Compatibility Mode Bit) = 1 allows

‘C2x/’C2xx/C5x styled ARP operation for ARs. ‘C2x/’C2xx/C5x styled ARP operation for ARs. But this mode is discouraged.But this mode is discouraged.


ESIEE, Slide 35

ExampleExample

Initialization of AR1 and AR2.

Copy the values from table in DROM to RAM (via A). Indirect addressing allows sequential access to data.

RAM

x[3]

RAM

y54xCPU

System Diagram

DROM

tbl[3]

EPROM

code



.sect “code” start: STM #tbl,AR1

STM #x,AR2


LD #x,DP

LD *AR1+,A STL A,*AR2+ ;...


ESIEE, Slide 36

Absolute Addressing Mode Absolute Addressing Mode *()*()

Allows us to specify a complete operand Allows us to specify a complete operand address in an instruction. address in an instruction. *(Address)*(Address)

The address can be in data, program or The address can be in data, program or IO memory. 16 bits. IO memory. 16 bits.

2 words, 2 cycles.2 words, 2 cycles.Data Memory

Addr Data . . . . x: 01FF 1000y: 0200 0500 . . . .

0 0 0 0 0 0 1 0 0 0Acc A

0 0 0 0 0 0 1 5 0 0

.data

x: .word 1000h

y: .word 0500h

.text

LD *(x),A

ADD *(y),A


ESIEE, Slide 37

ExampleExample

RAM

x[3]

RAM

y54xCPU

System Diagram

DROM

tbl[3]

EPROM

code

Save accumulator A at address y

X .usect "vars",3 Y .usect "result",1


.sect “code” Start: STM #tbl,AR1

STM #x,AR2


LD #x,DP

LD *AR1+,A STL A,*AR2+ ;...

STL A,*(y)


ESIEE, Slide 38

MMR Memory Mapped RegistersMMR Memory Mapped Registers AddressingAddressing MMRs are in page 0 of data memory.MMRs are in page 0 of data memory. They can be accessed by some specific MMR They can be accessed by some specific MMR

instructions allowing simple access to page 0.instructions allowing simple access to page 0. In these cases DP, SP and CPL are ignoredIn these cases DP, SP and CPL are ignored

0000h

0060h

007Fh

MMRs

Scratch

Tip: use the .mmregs directive to allow MMR names to be interpreted as addresses

LDM, STLM MMR AccSTM # MMRPSHM, POPM MMR StackMVDM, MVMD MMR DmemMVMM AR, SP AR, SP


ESIEE, Slide 39

MMR Memory Mapped RegistersMMR Memory Mapped Registers

Addr. Name (Hex) Description

IMR 0000 Interrupt Mask Register

IFR 0001 Interrupt Flag Register

----- 2 - 5 Reserved

ST0 0006 Status 0 Register

ST1 0007 Status 1 Register

AL 0008 A accumulator low (A[15:00])

AH 0009 A accumulator high (A[31:16])

AG 000A A accumulator guard (A[39:32])

BL 000B B accumulator low (B[15:00])

BH 000C B accumulator high (B[31:16])

BG 000D B accumulator guard (B[39:32])

T 000E Temporary Register

TRN 000F Transition Register

Addr.Name (Hex) Description

AR0 0010 Address Register 0








SP 0018 Stack Pointer Register

BK 0019 Circular Size Register

BRC 001A Block Repeat Counter

RSA 001B Block Repeat Start Address

REA 001C Block Repeat End Address

PMST 001D PMST Register

------- 01E-01F Reserved

Note: XPC and Peripheral MMR locations are device dependent


ESIEE, Slide 40

MMR Memory Mapped Registers AddressingMMR Memory Mapped Registers Addressing

When accessing MMRs, latencies need When accessing MMRs, latencies need to be considered.to be considered.

STM (STore to Memory-mapped STM (STore to Memory-mapped register):register): Stores an immediate value to the specified Stores an immediate value to the specified

MMR or ScratchMMR or Scratch memory memory address. address. Writes the values during the access phase Writes the values during the access phase

of the pipeline to avoid latencies.of the pipeline to avoid latencies.


ESIEE, Slide 41

Exercise on Addressing Modes of C54xExercise on Addressing Modes of C54xGiven: DP=0 DP=4 DP=6 Address/Data (HEX) 60 20 200 100 300 100CPL=0 61 120 201 60 301 30CMPT=0 62 202 40 302 60

Program A B DP AR0 AR1 AR2LD #0,DPSTM #2,AR0STM #200h,AR1STM #300h,AR2LD @61h,AADD *AR1+,ASUB @60h,A,BADD *AR1+,B,ALD #6,DPADD @1,AADD *AR2+,ASUB *AR2+,ASUB #32,AADD *AR1-0,A,BSUB *AR2-0,B,ASTL A,62h

120

260

390

380

Addr Mode


ESIEE, Slide 42

Exercise on Addressing Modes of C54xExercise on Addressing Modes of C54xGiven: DP=0 DP=4 DP=6 Address/Data (HEX) 60 20 200 100 300 100CPL=0 61 120 201 60 301 30CMPT=0 62 202 40 302 60

Program A B DP AR0 AR1 AR2

LD #0,DP STM #2,AR0 STM #200h,AR1 STM #300h,AR2 LD @61h,A ADD *AR1+,A SUB @60h,A,B ADD *AR1+,B,A LD #6,DP ADD @1,A ADD *AR2+,A SUB *AR2+,A SUB #32,A ADD *AR1-0,A,B SUB *AR2-0,B,A STL A,62h

Addr Mode 120 260 390 380

IMMED 0 MMR 2 MMR 200 MMR 300 DIRECT INDIRECT 220 201 DIRECT 200 INDIRECT 202 IMMED 6 DIRECT 290 INDIRECT 301 INDIRECT 360 302 IMMED 340 INDIRECT 200 INDIRECT 320 300 DIRECT


ESIEE, Slide 43

C55x Addressing ModesC55x Addressing Modes


ESIEE, Slide 44

Format of Data and Instructions, Internal Format of Data and Instructions, Internal Busses for the C55x FamilyBusses for the C55x Family

Unified program-data memory map: Unified program-data memory map: byte-aligned for program and word-byte-aligned for program and word-aligned for data.aligned for data.

Has a variable length instruction set (8-Has a variable length instruction set (8-16-24-32-40-48 bits). 16-24-32-40-48 bits). Program address bus: 24 bits, 16 MbytesProgram address bus: 24 bits, 16 Mbytes 4 instructions bytes are fetched at a time4 instructions bytes are fetched at a time 6 bytes are decoded at a time6 bytes are decoded at a time

Internal data busses: 3 data read, 2 data Internal data busses: 3 data read, 2 data writewrite Data addresses: 8 Mwords of 16 bits Data addresses: 8 Mwords of 16 bits

segmented into 64K pages, segmented into 64K pages, 23-bit address.23-bit address. A 24-bit address is automatically generated A 24-bit address is automatically generated by the hardware by adding a LSB = 0.by the hardware by adding a LSB = 0.


ESIEE, Slide 45

C55x Addressing ModesC55x Addressing Modes DirectDirect IndirectIndirect AbsoluteAbsolute MMRMMR Loading constants in registers (e.g. Loading constants in registers (e.g.

immediate)immediate)

y = x0 + xy = x0 + x11 + x + x22

AlgorithmAlgorithm

RAMRAM

x[x[33]]

RAMRAM

yy

II PP

DD AA

55xx55xxCPUCPU

System DiagramSystem Diagram

ROMROM

tbl[tbl[33]]

y = x0 + xy = x0 + x11 + + x x22

This algorithm will again be used This algorithm will again be used as an example for the different as an example for the different addressing modes.addressing modes.


ESIEE, Slide 46

Loading Constants in Registers Loading Constants in Registers ##

Used for initialization of registers.Used for initialization of registers. Used to be called immediate addressingUsed to be called immediate addressing

Addressing registers:Addressing registers: 16-bits long: 16-bits long: ARi, DP, CDP (Coefficient ARi, DP, CDP (Coefficient

Data Pointer)Data Pointer) 23-bits long: 23-bits long: XARi, XDP, XCDPXARi, XDP, XCDP The 7 MSB of Xreg specify the 64K page. The 7 MSB of Xreg specify the 64K page.

The The ARAUARAU auxiliary Register auxiliary Register Arithmetic Unit is 16 bits wide: update Arithmetic Unit is 16 bits wide: update of ARi and CDP are done modulo 64K.of ARi and CDP are done modulo 64K.

Initialization example:Initialization example: AMOV AMOV #adr,XAR3#adr,XAR3


ESIEE, Slide 47

ExampleExamplexx .usect “vars”,4 .usect “vars”,4yy .usect “vars”,1 .usect “vars”,1

.sect “init”.sect “init”tbltbl .int 1,2,3,4 .int 1,2,3,4

.sect “code”.sect “code”

indir: AMOV #x,XAR0indir: AMOV #x,XAR0 AMOV #tbl,XAR6AMOV #tbl,XAR6

RAMRAM

x[x[33]]

RAMRAM

yy

II PP

DD AA

55xx55xxCPUCPU

ROMROM

tbl[tbl[33]]

y = x0 + xy = x0 + x11 + + x x22

== 23-bit address23-bit address

16-bit ARn16-bit ARn23-bit XARn23-bit XARn

XX


ESIEE, Slide 48


Gives the instruction a positive 7bit Gives the instruction a positive 7bit offset from DP (non-aligned).offset from DP (non-aligned). In the case where the bit CPL=0 in ST1.In the case where the bit CPL=0 in ST1. Calculation in the ARAU modulo 64KCalculation in the ARAU modulo 64K

7-bit @x7-bit @x

==

++

23-bit address23-bit address

16-bit DP16-bit DP23-bit XDP23-bit XDP

XX


ESIEE, Slide 49

ExampleExamplexx .usect “vars”,4 .usect “vars”,4yy .usect “vars”,1 .usect “vars”,1

.sect “init”.sect “init”tbltbl .int 1,2,3,4 .int 1,2,3,4

.sect “code”.sect “code”

How is XDP initialized?How is XDP initialized?

RAMRAM

x[x[33]]

RAMRAM

yy

II PP

DD AA

55xx55xxCPUCPU

ROMROM

tbl[tbl[33]]

y = x0 + xy = x0 + x11 + + x x22

ADD: MOV @(x+0),AC0ADD @(x+1),AC0

ADD @(x+2),AC0


ESIEE, Slide 50

ExampleExample

Constant value contained Constant value contained in instruction opcodein instruction opcode

(-x) (-x) used in instruction to tellused in instruction to tellthe the assemblerassembler HOW to create the HOW to create the7-bit offset from non-aligned XDP7-bit offset from non-aligned XDP

A in AMOV means in AD-phase.A in AMOV means in AD-phase.

The MDP has to be reloaded The MDP has to be reloaded every time we cross a 64K page.every time we cross a 64K page.

dir: AMOV #x,XDP

x .usect “vars”,4 y .usect “vars”,1 .sect “init” tbl .int 1,2,3,4 .sect “code”

ADD: MOV @(x+0-x),AC0 ADD @(x+1-x),AC0 ADD @(x+2-x),AC0


ESIEE, Slide 51

Directive Directive .dp.dp for Direct Addressing for Direct Addressing

Instead of using (-x) to help the assemblerInstead of using (-x) to help the assemblercalculate the proper 7-bit offset,calculate the proper 7-bit offset,

We can use the directive We can use the directive .dp .dp to set the base address to set the base address for the assembler calculation of the 7-bit offset.for the assembler calculation of the 7-bit offset. .dp base_address.dp base_address

The @addr in the instruction is The @addr in the instruction is interpreted as a 23-bit address.interpreted as a 23-bit address.

The .dp provides a compile-time base The .dp provides a compile-time base address.address.

The assembler determines the 7-bit The assembler determines the 7-bit offset by: (@addr-.dp_value)&7Foffset by: (@addr-.dp_value)&7F

.dp x dir: AMOV #x,XDP

ADD: MOV @(x+0),AC0 ADD @(x+1),AC0 ADD @(x+2),AC0


ESIEE, Slide 52


Similar to the case of the C54x, but:Similar to the case of the C54x, but: 23-bit addresses,23-bit addresses, Extended registers XARi on 23 bits specify Extended registers XARi on 23 bits specify

the complete address,the complete address, ARAU calculates on 16 bits (modulo 64K)ARAU calculates on 16 bits (modulo 64K),, 8 ARi 16-bit pointers used in the 8 ARi 16-bit pointers used in the

instructions.instructions.

== 2233--bbiitt aaddddrreessss

1166--bbiitt AARRnn 2233--bbiitt XXAARRnn

XX


ESIEE, Slide 53

Indirect Addressing Options for Pointer Indirect Addressing Options for Pointer ARi ARi ModificationsModifications

Assumes ST2_55Assumes ST2_55ARMSARMS=0 and ST1_55=0 and ST1_55C54CMC54CM=0.=0.

The reset condition is C54CM=1. The reset condition is C54CM=1.

*ARn(T0/1) No Modify w/offset *ARn(#k16) No Modify w/offset *(ARn +/- T0/1) Post Modify (+/- by T0/1) *+/- ARn (+/-) Pre Modify *+ ARn(#k16) (+ #k16) Pre Modify *(ARn +/- T0B) Bit reversed using T0 *CDP No Modify *CDP(#k16) No Modify w/offset *CDP +/- Post Modify (+/-) *+CDP(#k16) (+ #k16) Pre Modify

*ARn No Modify *ARn +/- Post Modify (+/-)


ESIEE, Slide 54

Address Register Mode Select Bit ARMSAddress Register Mode Select Bit ARMS

ARMS bit = bit 15 of ST2_55ARMS bit = bit 15 of ST2_55 ARMS=0 at reset DSP modeARMS=0 at reset DSP mode For ARMS=1, CONTROL modeFor ARMS=1, CONTROL mode

T1 cannot be used as offsetT1 cannot be used as offset No bit reversed addressingNo bit reversed addressing New mode: New mode:

*ARi(short(#k3))*ARi(short(#k3)) or or *SP(short(#k3))*SP(short(#k3)) Useful for the C compilerUseful for the C compiler

The C compiler sets ARMS = 1.The C compiler sets ARMS = 1.


ESIEE, Slide 55

Modifying TAs RegistersModifying TAs Registers

TAx registers = T0-3, AR0-7TAx registers = T0-3, AR0-7.. Special instructions:Special instructions:

AAADD, ADD, AASUB, SUB, AAMOVMOV Can be used to modify TAs registers Can be used to modify TAs registers

during the address (AD) phase of the during the address (AD) phase of the pipeline, while instructions without A pipeline, while instructions without A operates during the execution (X) phase.operates during the execution (X) phase.

They only work on the TAx registers.They only work on the TAx registers.ExamplesExamples::

AADD #const,AR1 ASUB AR1,T0 AMOV #k23,XAR2


ESIEE, Slide 56

ExampleExample

+ ++ +

RAMRAM

x[4]x[4]

RAMRAM

yy

II PP

DD AA

55xx55xxCPUCPU

ROMROM

tbl[4]tbl[4]

y = x0 + xy = x0 + x11 + + x1 x1

x .usect “vars”,4 y .usect “vars”,1 .sect “init” tbl .int 1,2,3,4 .sect “code”

.dp x

dir: AMOV #x,XDP


indir: AMOV #x,XAR0 AMOV #tbl,XAR6

COPY: MOV *AR6+, AR0+ MOV *AR6+,*AR0+ MOV *AR6 ,*AR0


ESIEE, Slide 57

Circular Buffer Addressing ModeCircular Buffer Addressing Mode

== Buffer Start Address

== Buffer Length BKzz[15:0]

Offset into Buffer ==

BSAxx[15:0] Xeven[22:16]

== Calculated Address BSAxx + ARn/CDP Xeven[22:16]

ARn/CDP ++


ESIEE, Slide 58

Circular Buffer Addressing ModeCircular Buffer Addressing Mode

Offset XevenBuffer Start

Address

Block size Register

AR0AR1AR2AR3AR4AR5AR6AR7CPD XCDP[22:16] BSAC BKC

XAR0[22:16]

XAR2[22:16]

XAR4[22:16]

XAR6[22:16]

BK03

BK03

BSA01

BSA01

BSA01

BSA01

The even XARn (i.e. 0,2,4,6) determines the 64K PageThe even XARn (i.e. 0,2,4,6) determines the 64K Page


ESIEE, Slide 59

Selecting Circular or Linear Addressing Selecting Circular or Linear Addressing ModeMode

Use the LSB of Status word ST2_55Use the LSB of Status word ST2_55

00 == lliinneeaarr mmooddee 11 == cciirrccuullaarr mmooddee

SSTT22__5555

AARR77LLCC

AARR66LLCC

AARR55LLCC

AARR44LLCC

AARR33LLCC

AARR22LLCC

AARR11LLCC

AARR00LLCC

CCDDPPLLCC

ootthheerr bbiittss oorr rrssvvdd

00 11 22 33 44 55 66 77 88 99 1155

((ddeeffaauulltt))

Set or reset Set or reset statusstatus bits: bits: BBSSEETT AARR55LLCC ;;AARR55 iinn cciirrccuullaarr mmooddee BBCCLLRR AARR33LLCC ;;AARR33 iinn lliinneeaarr mmooddee


ESIEE, Slide 60

Circular Buffer ExerciseCircular Buffer ExerciseUse AR4 as a circular pointer to x{5}:Use AR4 as a circular pointer to x{5}:

AARR44 77 11 99 66 22

00

11

22

33

44

xx

AARR44

..sect “data” x .int 7,1,9,6,2 ;init data .sect “code” __________________ ;init XAR __________________ ;init start addr __________________ ;init length __________________ ;init AR4 to top __________________ ;set AR4 to circ MOV #3,T0 ;index MOV *(AR4+T0),AC0 ;AC0 =__7__, AR4 =_3____ MOV *+AR4(#4h),AC1 ;AC1 =_9__, AR4 =_2____ MOV *AR4(T0),AC2 ;AC2 =_7__, AR4 =_2__

AMOV #x,XAR4 MOV #x,BSA45 MOV #5,BK47 MOV #0,AR4 BSET AR4LC

Results areResults arecumulativecumulative


ESIEE, Slide 61

Comparison of C54x andComparison of C54x and C55x circular C55x circular addressing modesaddressing modes

3 BK registers in C55X instead of 1 in 3 BK registers in C55X instead of 1 in C54x: allows for several simultaneous C54x: allows for several simultaneous circular buffers with different size.circular buffers with different size.

In C54x, circular addressing mode is In C54x, circular addressing mode is specified in indirect addressing type % specified in indirect addressing type % in the instructionsin the instructions..

In C55x, the mode in set in status In C55x, the mode in set in status register ST2_55 for each register (linear register ST2_55 for each register (linear or circular).or circular). No memory alignment No memory alignment constraint.constraint.


ESIEE, Slide 62

Absolute Addressing Absolute Addressing *(#)*(#)

*(#)*(#) = 23 bit address = 23 bit address Fast: no initialization,Fast: no initialization, But long instruction because it contains But long instruction because it contains

the 23 bit address.the 23 bit address. If the address is in the 64K work page, If the address is in the 64K work page,

it is possible to specify a 16-bit only it is possible to specify a 16-bit only address:address: abs16*(#label)abs16*(#label)


ESIEE, Slide 63

ExampleExample

RAMRAM

x[4]x[4]

RAMRAM

yy

II PP

DD AA

55xx55xxCPUCPU

ROMROM

tbl[4]tbl[4]

y = x0 + xy = x0 + x11 + + x2 x2

X .usect “vars”,4 Y .usect “vars”,1

.sect “init” tbl .int 1,2,3,4

.sect “code”

.dp x

dir: AMOV #x,XDP


indir: AMOV #x,XAR0 AMOV #tbl,XAR6

COPY: MOV *AR6+,*AR0+ MOV *AR6+,*AR0+

MOV *AR6 ,*AR0

STORE: MOV AC0,*(#y)


ESIEE, Slide 64

MMR Addressing Using mmap()MMR Addressing Using mmap()

MMRs are located between 0 and 5F.MMRs are located between 0 and 5F. Scratch memory is located between 60 Scratch memory is located between 60

and 7F.and 7F. mmap() forces bits 22:7 to zero.mmap() forces bits 22:7 to zero.

Useful to access MMR and scratch memory Useful to access MMR and scratch memory without initialization of addressing without initialization of addressing registers.registers.

Useful only for direct addressing.Useful only for direct addressing. ; write #1234h to ST0_55 AMOV #0,XDP MOV #1234h, @(ST0_55 - 0)

; write #1234h to ST0_55 MOV #1234h, mmap(@ST0_55)


ESIEE, Slide 65

Access Peripheral RegistersAccess Peripheral Registers

The I/O space is internal.The I/O space is internal. The PDP (Peripheral Data Pointer) The PDP (Peripheral Data Pointer)

register is used to access ports using register is used to access ports using direct addressing.direct addressing. It is a 9bit register. Its value is It is a 9bit register. Its value is

concatenated with the 7 bits in the concatenated with the 7 bits in the instruction to obtain a full 16-bit instruction to obtain a full 16-bit peripheral address.peripheral address.

The port() modifier selects the The port() modifier selects the peripheral mapperipheral map


ESIEE, Slide 66

Access Peripheral RegistersAccess Peripheral Registers

0000h0000h

FFFFhFFFFh

I/O - PeripheralI/O - PeripheralMemory MapMemory Map

DMADMA

McBSPMcBSP

EHPIEHPI

EMIFEMIF

TimersTimers

Power DwnPower Dwn

Instr CacheInstr Cache

GPIOGPIO

abs: MOV port(#addr),T1abs: MOV port(#addr),T1

dir: MOV #addr,PDPdir: MOV #addr,PDP MOV T1,port(@addr)MOV T1,port(@addr)

indir: AMOV #addr,AR4indir: AMOV #addr,AR4 MOV port(*AR4),T1MOV port(*AR4),T1


ESIEE, Slide 67

Directives for Addressing ModesDirectives for Addressing Modes

3 Mode bits affect addressing:3 Mode bits affect addressing: ARMS: Address Register Mode SelectARMS: Address Register Mode Select C54CM: C54 Compatibility ModeC54CM: C54 Compatibility Mode

C54CM=1 on reset, native C55x coding C54CM=1 on reset, native C55x coding requires C54CM=0.requires C54CM=0.

CPL: ComPiLer ModeCPL: ComPiLer Mode 3 directives help the assembler to check 3 directives help the assembler to check

the syntax and responds with ERROR the syntax and responds with ERROR in case of inconsistency:in case of inconsistency: .arms_on .arms_on or .arms_offor .arms_off .c54cm_on .c54cm_on or .c54cm_offor .c54cm_off .cpl_on.cpl_on or .cpl_offor .cpl_off


ESIEE, Slide 68

Modifying Status BitsModifying Status Bits

BCLR BCLR ARMSARMS ;clear ;clear ARMSARMS

BSET BSET CPLCPL ;set ;set CPLCPL

BCLR C54CMBCLR C54CM ;clear C54CM;clear C54CM

BSET/BCLR bit_nameBSET/BCLR bit_name


ESIEE, Slide 69

Addressing ExerciseAddressing Exercise02_0105h02_0105h 21h21h

x = 02_0106hx = 02_0106h02_0107h02_0107h02_0108h02_0108h

02_0206h02_0206h

XDPXDP

The The initialinitial state of state of eacheach instruction is instruction isshown here...shown here...

Below, write downBelow, write downthe state the state afterafter each instr each instr

30h30h40h40h50h50h

60h60h

XAR1XAR1

T0T0 22

02_0106h02_0106h

02_0106h02_0106h

.dp x.dp x

AR1 AC0 T1 02_0106h ST1M40 MOV @(x+1),AC0 MOV @(x+80h),AC0 MOV T0,*AR1+ MOV *(#x),AC0 MOV #4,@(x+128) MOV *(AR1+T0),T1 BSET M40 MOV @(x+2),AC0 MOV *AR1(T0),AC0 MOV *AR1(#100h),T1 MOV @(x+129),AR1 MOV *+AR1(#-1),AC0


ESIEE, Slide 70

Addressing Exercise – SolutionAddressing Exercise – Solution02_0105h02_0105h 21h21h

x = 02_0106hx = 02_0106h02_0107h02_0107h02_0108h02_0108h

02_0206h02_0206h

XDPXDP

The The initialinitial state of state of eacheach instruction is instruction isshown here...shown here...

Below, write downBelow, write downthe state the state afterafter each instr each instr

30h30h40h40h50h50h

60h60h

XAR1XAR1

T0T0 22

02_0106h02_0106h

02_0106h02_0106h

.dp x.dp x

AR1 AC0 T1 02_0106h ST1M40 MOV @(x+1),AC0 MOV @(x+80h),AC0 MOV T0,*AR1+ MOV *(#x),AC0 MOV #4,@(x+128) MOV *(AR1+T0),T1 BSET M40 MOV @(x+2),AC0 MOV *AR1(T0),AC0 MOV *AR1(#100h),T1 MOV @(x+129),AR1 MOV *+AR1(#-1),AC0

40h 30h 107h 2 30h 4 108h 30h 1 50h 106h 50h 106h 60h 40h 105h 21h


ESIEE, Slide 71


ESIEE, Slide 72

Circular buffer and circular addressingCircular buffer and circular addressing

A circular buffer of length N is a block A circular buffer of length N is a block of contiguous memory words addressed of contiguous memory words addressed by a pointer using a modulo N by a pointer using a modulo N addressing mode. addressing mode. The 2 extreme words of the memory block The 2 extreme words of the memory block

are considered as contiguous.are considered as contiguous. Characteristics of a circular buffer:Characteristics of a circular buffer:

Instead of moving the N data in memory, Instead of moving the N data in memory, just modify the pointers.just modify the pointers.

When a new data x(n) arrives, the pointer When a new data x(n) arrives, the pointer is incremented and the new data is written is incremented and the new data is written in place of the oldest one.in place of the oldest one.


ESIEE, Slide 73

Trace of Memory and Pointer in a Circular Trace of Memory and Pointer in a Circular Buffer of Length 3Buffer of Length 3

Time n Time n+1 Time n+2 Time n+3

x(n-1) x(n-1) x(n+2) x(n+2)x(n) x(n) x(n) x(n+3)

x(n-2) x(n+1) x(n+1) x(n+1)

Very often used for FIR filters.Very often used for FIR filters.

dsp c5000 chapter 3 addressing modes copyright © 2003 texas instruments. all rights reserved

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