1
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CoverSheet_01.SchDoc
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Size:
Mod. Date:
File:Sheet: of
B http://www.ti.comContact: http://www.ti.com/support
TI 66AK2L06 JESD Attach to Wideband ADCs and DACsProject Title:Designed for: Public Release
Assembly Variant: [No Variations]
© Texas Instruments 2015Drawn By:Engineer: a0271760
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Version control disabledSVN Rev:TIDEP0034Number: Rev: E1
TID #: TIDEP0034Orderable: EVM_orderable
Revision HistoryRevision Notes
Rev 1.0 Initial revision release
TI 66AK2L06 JESD Attach to Wideband ADCs and DACs
Major Component Product Pages
Table of ContentsPage Name Page Description
k2l_soc_05.SchDoc K2L Resets, Core PLL and SERDES PLL Inputs
k2l_soc_06_1.SchDoc K2L Boot-Config, I2C, SPI, UART, Timer, and USIM
k2l_soc_08.SchDoc K2L DFE JESD204B SYSREF, SYNCIN/OUT and DFE I/O
adc12j4000_01.SchDoc ADC power pins, power filtering and decoupling capacitors
adc12j4000_02.SchDoc ADC Input, JESD204B interface, SPI and discrete I/O control
dac38j84_01.SchDoc DAC power pins, power filtering and decoupling capacitors
dac38j84_02.SchDoc DAC Output, JESD204B interface, SPI and discrete I/O control
Page Number
11
13
15
25
26
27
29
lmk04828_01.SchDoc LMK04828 power pins, power filtering and decoupling capacitors
lmk04828_02.SchDoc Clock input, clock output, SPI and discrete I/O control
30
31
TI LMK04828 Product Page
TI ADC12J4000 Product Page
TI DAC38J84 Product Page
TI 66AK2L06 Product Page
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
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system_diagram.SchDoc
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Size:
Mod. Date:
File:Sheet: of
B http://www.ti.comContact: http://www.ti.com/support
TI 66AK2L06 JESD Attach to Wideband ADCs and DACsProject Title:Designed for: Public Release
Assembly Variant: [No Variations]
© Texas Instruments 2015Drawn By:Engineer:
a0271760a0271760
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Version control disabledSVN Rev:TIDEP0034Number: Rev: E1
TID #: TIDEP0034Orderable: EVM_orderable
MDIO
DDR3ACLK
PCIECLK
SGMIICLK
66AK2L06 SoC
DDR3A (72-bit)
USB 3.0 Super-Speed
USBCLK
DFE SYNCOUT
Core DSP + ARM AVS Supply
JESD RX[0]
JESD RX[1]
CSIS2_2 SGMII[1:0]
CSIS2_3PCIe[1:0]/SGMII[2:3]
CSISC2_1_CLK
ALTCORECLK
DFESYSREF
SYSCLK
CSISC2_0_CLK
AVSControl
JTAG
GPIO[31:0]/BOOT/EMU
UART0/SPI 2
I2C2
Reset /Boot/Config Control
I2C1
SPI 0 (CS0)
EMIF16 (16-bit)
I2C0
Digital I /O Supplies
1.8V
PLL/DLL Analog Supplies
SERDES/USB Analog Supplies
DDR 3 SO-DIMM or Discrete SDRAM
Array
NAND Flash
Digital SRAM Supply
DAC38 J84
IOUTA
DACCLK
SPI
SYNCB
SYSREF
VDDT 09
D0JESD TX [0]
JESD TX [1] D1
VDDS 18
VDDIO 18
JTAG
TXENABLE IOUTB
EXTIO
RBIAS
VDDAREF18
VDDADAC33
VDDDAC09
VDDDIG 09
PLLLLPF
VDDAPLL18
VDDCLK09
RESETB
SLEEP
ALARM
RBIAS
ADC12 J4000
VBG
VCMO
VIN
DS 0
DS 1
DS 5 / NCO _0
DS 6 / NCO _1
DS 7 / NCO _2
OR_T0
OR_T1
SPI
DEVCLK
SYSREF
SYNC /TMST
VA12
VA19
VD12
VNEG
VNEG_OUT
Balun(If Required )
DFE GPIO[0]
DFE GPIO[1]
DFE GPIO[2]
DFE GPIO[3]
Filter/Termination OutputConnector
Filter/Termination OutputConnector
ADC12J4000Power Solution
DAC38J84Power Solution
66 AK2LPower Solution
Input Connector
Test Point
Reference Resistor
66 AK2LClock Solution
DFE GPIO[4]
DFE GPIO[5]
DFE GPIO[6]
DFE GPIO[7]
JTAG Emulation Header
JTAG Emulation Header
SYSREFGeneration To DAC SYSREF
Test Point
ADC12J4000Clock Solution
From SYSREF Generator
DFE SYNCIN
K2L RecommendedEthernet Solution
USB3.0 Connector
PCIe Card -Edge Fingers /Connector
TM4C1231 H6PZ MCU
Clock Control
System Power Control
Reset/Boot Control
DAC38J84Clock Solution
From SYSREF Generator
Loop Filter Circuit
Test Point
Output Current Set Resistor
To ADC SYSREF
UART System Control
USB Connector(Linux Terminal)
USB-to-UARTBridge
USB Connector(System Terminal)
USB-to-UARTBridge
I2C Accessory IC
SoCIndicator LEDs
SystemIndicator LEDs
GPIO
TI PoE Solution
HID GPIO
VDD
MCUPower Solution
MCU ClockingMCU
Clock Solution
VDDA
VDDC
Filter
VDDR 18
To ADC Clock Generation
To DAC Clock Generation
SPI 1 (CS0)
1
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2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
3 35
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system_power_diagram.SchDoc
Sheet Title:
Size:
Mod. Date:
File:Sheet: of
B http://www.ti.comContact: http://www.ti.com/support
TI 66AK2L06 JESD Attach to Wideband ADCs and DACsProject Title:Designed for: Public Release
Assembly Variant: [No Variations]
© Texas Instruments 2015Drawn By:Engineer: a0271760
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Version control disabledSVN Rev:TIDEP0034Number: Rev: E1
TID #: TIDEP0034Orderable: EVM_orderable
SERDES Analog 0.9 V
SERDES Analog 0.9 V
SERDES Analog 0.9 V
Analog 1.9 V
Digital 1.2 V
Analog 1.2 V
ARM PLL Supply (1.8V)
DDR3A PLL Supply (1.8V)
DSP /ARM AVS Core (1.0-0.70 V)CVDD
DSP /ARM Fixed Core (1.0V)CVDD 1
SERDES Low Voltage (0.85 V)AVDDALV
SERDES High Voltage (1.8V)AVDDAHV
I/O Supply (1.8V)DVDD 18
DDR3/DDR3L I/O Supply (1.35 /1.5V)DVDDR
DDR3A I/O Reference (DVDDR/2)VREFSSTLA
Main PLL Supply (1.8V)
AVDDA 1
AVDDA 2
AVDDA 3
PA PLL Supply (1.8V)AVDDA 4
DDR3A DLL Supply (1.8V)AVDDA 6
DDR3A DLL Supply (1.8V)AVDDA 7
DDR3A DLL Supply (1.8V)AVDDA 8
DDR3A DLL Supply (1.8V)AVDDA 9
DFE PLL Supply (1.8V)AVDDA 5
USB Digital Supply (3.3V)DVDD 33
USB Digital I/O Supply (0.85 V)VDDUSB
USB PHY High Super -Speed Supply (3.3V)VPH
USB PHY Low Super -Speed Supply (0.85 V)VP
USB PHY Transmit Supply (0.85 V)VPTX
66A2KL AVS Core Supply
0.95V – 1.05V, 15A
Channel 1: 3.3V, 4A
VTT/VREF Source-Sink
Regulator TPS51200
K2L_CVDD
Channel 2: 1.8V, 4A
Filter
Filter
Filter
Filter
Filter
Filter
Channel 3: 0.85V, 2A Filter
Channel 4: 1.0V, 2A
Filter
Filter
Filter
Filter
66 AK2L06 SoC Power Nets
SDRAM Core and I/O Supply (1.35 V/1.5V)VDD
SDRAM I/OReference (VDD/2)VREF
SDRAM Termination (VDD/2)VTT
DDR3A DLL Supply (1.8V)AVDDA 10
Filter
AVS ControlVCNTL/I2C0TPS 65400
Quad-Channel Buck Converter
TPS544B24 AVS Supply
VSYS_DVDD 18
VSYS_DVDD 0V85
K2L_CVDD 1V0
PMBUS Control
VA12
VA19
VD12
ADC12 J4000 Power Nets
Filter
Digital Core 0.9 V
DAC38 J84 Power Nets
Filter VDDT 09
VDDDAC 09
VDDDIG 09
VDDCLK09
Filter
Filter
Digital 3.0 V
Digital 3.3 V
Digital 3.3 V
TM4C1231 H6PZ MCU Power Nets
VDD
VDDA
VDDC
Channel 1: 1.35/1.5V, 4A
Channel 2: 1.2V, 4A
Channel 3: 0.90V, 2A
Channel 4: 1.9V, 2A
TPS 65400Quad-Channel
Buck Converter
PMBUS Control
VSYS_DVDDR
PMBUS Control
VSYS_DVDD 0V9
VSYS_DVDD 1V2
VSYS_DVDD 1V9
3.3V, 400mA
TPS73633DRB Single-Channel LDO
Filter
Analog 3.3 VVDDADAC 33Filter
VSYS_DVDD 3V3
LMK04828 Power Nets
Clock Group 1 3.3V
Clock Group 1 3.3VVCC 1_VCO
VCC 2_CG 1
Clock Group 2 3.3V
SYSREF and SYNC 3.3VVCC 3_SYSREF
VCC 4_CG 2
Filter
Filter
Filter
Filter
Digitial 3.3VVCC 5_DIG
PLL1 3.3VVCC 6_PLL1
Oscillator Out 3.3VVCC 7_OSCOUT 1
Oscillator In 3.3VVCC 8_OSCIN 1
Charge Pump 2 3.3VVCC 9_CP 2
PLL2 3.3VVCC 10_PLL2
Clock Group 3 3.3VVCC 11_CG 3
Clock Group 0 3.3VVCC 12_CG 0
Filter
Filter
Filter
Filter
Filter
Filter
Filter
Digital I/O 1.8V
SERDES Analog 1.8 V
Reference Analog 1.8 V
PLL Analog 1.8 V
VDDS 18
VDDIO 18
VDDAREF18
VDDAPLL18
Filter
Filter
Filter
SERDES Analog 1.8 VVDDR 18Filter
CDCM6208 v2Power Nets
Primary Input 1.8V
Digital 1.8VDVDD
VDD _PRI_REF
VCO 1.8V
Secondary Input 1.8VVDD _SEC_REF
VDD _VCO
Filter
Filter
PLL1 1.8VVDD _PLL1
PLL2 1.8VVDD _PLL2
Outputs Y0/Y1 1 1.8VVDD _Y0_Y1_1
Outputs Y0/Y1 2 1.8VVDD _Y0_Y1_2
Outputs Y2/Y3 1 1.8VVDD _Y2_Y3_1
Outputs Y2/Y3 2 1.8VVDD _Y2_Y3_2
Outputs Y4 1.8VVDD _Y4
Outputs Y5 1.8VVDD _Y5
Filter
Outputs Y6 1.8VVDD _Y6
Outputs Y7 1.8VVDD _Y7
Filter
Filter
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
4 35
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system_clocking_diagram.SchDoc
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Mod. Date:
File:Sheet: of
B http://www.ti.comContact: http://www.ti.com/support
TI 66AK2L06 JESD Attach to Wideband ADCs and DACsProject Title:Designed for: Public Release
Assembly Variant: [No Variations]
© Texas Instruments 2015Drawn By:Engineer: a0271760
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Version control disabledSVN Rev:TIDEP0034Number: Rev: E1
TID #: TIDEP0034Orderable: EVM_orderable
JESD 204 B PHYReference Clock
DSP /ARM Main PLL Reference Clock
66 AK2L06 SoCReference Clocks
ADC Sampling Clock/SERDES Clock
JESD 204 B SYSREF
ADC12 J4000 Reference Clocks
SYSCLK
CSISC2_0_CLK
DEVCLK
SYSREF
2.94912 GHz
I2C Control
RESET
CLKin 1
SYNC /SYSREF_REQ
LMK04828 BISQ
Status_LD1
Status_LD2
CLKin 0
DCLKout4
SDCLKout5
DCLKout6
SDCLKout7
DCLKout0
SDCLKout1
JESD204B SERDES TX : 7.3728Gbps, (2.5x mode)DEVCLK = 2.94912 GHz
122.88 MHz
122.88 MHz
Primary Oscillator Input
Sleep Oscillator Input
TM4C1231 H6PZ MCUReference Clocks
XOSC0
XOSC1
16MHz XO
32.768KHz XO
19.2MHz TCXO
JESD 204 B SYSREFDFESYSREF
JESD 204 B PHYReference ClockCSISC2_0_CLK122.88 MHz
DDR3 ControllerPLL Reference ClockDDR 3ACLK
CDCM6208 v2
Y1
SPI Control
Y0
OSCin25MHz TCXO
SGMII SERDES ClockSGMIICLK
PCIe SERDES ClockPCIECLK
USB ClockUSBCLKY3
Y2
100 MHz
156.25 MHz
100 MHz
100 MHz
DCLKout2
SDCLKout3
DAC Main Clock
JESD 204 B SYSREF
DAC38 J84Reference Clocks
SYSREF
DACCLK122.88 MHz
JESD204B SERDES RX: 7.3728GbpsFdata = 368.64Msps
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
11 35
4/15/2015
k2l_soc_05.SchDoc
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Size:
Mod. Date:
File:Sheet: of
B http://www.ti.comContact: http://www.ti.com/support
TI 66AK2L06 JESD Attach to Wideband ADCs and DACsProject Title:Designed for: Public Release
Assembly Variant: [No Variations]
© Texas Instruments 2015Drawn By:Engineer: a0271760
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Version control disabledSVN Rev:TIDEP0034Number: Rev: E1
TID #: TIDEP0034Orderable: EVM_orderable
CORECLKSEL0AE27
BOOTCOMPLETE AG3
CORECLKSEL1AF27
CORESEL0_BOOTMODE13AE5
CORESEL1_BOOTMODE14AG6
CORESEL2_BOOTMODE15AH6
RESETFULLZAE2RESETSTATZ AE4
LRESETNMIENZAF2
RESETZAF3
HOUT AH2
NMIZAJ2LRESETZAK3
PORZG4
Resets and Core Config
U1I
TCI6630K2L
ALTCORECLKPAG30
ALTCORECLKNAH30
PCIECLKNAE19PCIECLKPAE20
SHARED_SERDES_1_REFCLKPAF14
SHARED_SERDES_1_REFCLKNAF15
SHARED_SERDES_0_REFCLKPAF17
SHARED_SERDES_0_REFCLKNAF18
SGMIICLKPAF23
SGMIICLKNAF24
DDR3ACLKPF30DDR3ACLKNG30
RSV005 AE28RSV004 AE29
SYSCLKOUT AF28SYSCLKPAF29
SYSCLKNAG29PLLLOCK AH29
Chip-Level PLL References Inputs
SERDES PLL Reference Inputs
U1J
TCI6630K2L
K2L_RESETSTATZK2L_BOOTCOMPLETE
K2L_RESETZK2L_RESETFULLZK2L_PORZ
K2L_LRESETZK2L_NMIZK2L_LRESETNMIENZ
K2L_CORESEL0_BOOTMODE13K2L_CORESEL1_BOOTMODE14K2L_CORESEL2_BOOTMODE15K2L_CORECLKSEL0K2L_CORECLKSEL1
K2L_SYSCLKPK2L_SYSCLKN
K2L_DDR3ACLKN
K2L_JESD_SERDES0_REFCLKNK2L_JESD_SERDES0_REFCLKP
K2L_JESD_SERDES1_REFCLKPK2L_JESD_SERDES1_REFCLKN
K2L_SGMIICLKPK2L_SGMIICLKN
K2L_PCIECLKNK2L_PCIECLKP
K2L_PLLLOCK
K2L Reset and Core Configuration
K2L Core and Peripheral PLL Reference Clock Inputs
1.00kR6
1.00kR7
1.00kR8
GND
4.75kR1
4.75kR2
4.75kR3
VSYS_DVDD1V8
1.00kR4
1.00kR5
GND
10.0R11K2L_SYSCLKOUT_RS
1.00kR12
GND
K2L_SYSCLKOUT0.1µFC267
0.1µFC268K2L_SYSCLKP_CSK2L_SYSCLKN_CS
0.1µFC2690.1µFC270K2L_DDR3ACLKP
K2L_DDR3ACLKNK2L_DDR3ACLKP
K2L_ALTCORECLKPK2L_ALTCORECLKN
1.00kR9
1.00kR10
GND
K2L_RESETZK2L_RESETFULLZ
K2L_PORZ
K2L_LRESETZK2L_NMIZ
K2L_LRESETNMIENZ
K2L_CORESEL0_BOOTMODE13K2L_CORESEL1_BOOTMODE14
K2L_CORECLKSEL0K2L_CORESEL2_BOOTMODE15
K2L_CORECLKSEL1
K2L_RESETSTATZK2L_BOOTCOMPLETE
K2L_PLLLOCKK2L_SYSCLKOUT_RS
K2L_SYSCLKPK2L_SYSCLKN
K2L_DDR3ACLKNK2L_DDR3ACLKP
K2L_JESD_SERDES0_REFCLKPK2L_JESD_SERDES0_REFCLKN
K2L_JESD_SERDES1_REFCLKPK2L_JESD_SERDES1_REFCLKN
K2L_SGMIICLKPK2L_SGMIICLKN
K2L_PCIECLKNK2L_PCIECLKP
1.00kR13
1.00kR14
GND
VSYS_DVDD1V8
K2L_ALTCORECLKPK2L_ALTCORECLKN
K1
TI 66AK2L06 Product Page
CORECLKSEL[1:0] = 0b00Select SYSCLK as source for K2L Main PLL
DDR3 controller reference clock solution not shown. Please see K2L EVM schematics.
SGMII and PCIe SERDES reference clock solution not shown. Please see K2L EVM schematics.
K2L JESD SERDES0/1 reference clock sourced my LMK04828. When utilizing LVDS outputs of LMK04828 no AC-coupling or external bias or termination network is necessary.
Not utilizing ALTCORECLK. Pull-up/down resistor necessary to reserve off clock input.
K2L PLLLOCK monitored by System Controller (microcontroller) not shown here.
K2L SYSCLK sourced my LMK04828. When utilizing LVDS outputs of LMK04828 only AC-coupling is necessary.
K2L BOOTMODE and RESET pins mastered by Board Mangement Controller (microcontroller) not shown here.
K2L RESETSTAT and BOOTCOMPLETE monitored by System Controller (microcontroller) not shown here.
For schematic and layout recommendations and requirements see the K2L product page linked below.
PIC26701PIC26702COC267
PIC26801PIC26802COC268
PIC26901PIC26902COC269
PIC27001PIC27002COC270
PIK101COK1
PIR101
PIR102COR1
PIR201
PIR202COR2
PIR301
PIR302COR3
PIR401
PIR402COR4
PIR501
PIR502COR5
PIR601
PIR602COR6
PIR701
PIR702COR7
PIR801
PIR802COR8
PIR901
PIR902COR9
PIR1001
PIR1002COR10
PIR1101 PIR1102COR11
PIR1201
PIR1202COR12
PIR1301
PIR1302COR13
PIR1401
PIR1402COR14
PIU10AE2
PIU10AE4
PIU10AE5
PIU10AE27
PIU10AF2
PIU10AF3
PIU10AF27
PIU10AG3
PIU10AG6
PIU10AH2
PIU10AH6
PIU10AJ2
PIU10AK3
PIU10G4
COU1I
PIU10AE19
PIU10AE20
PIU10AE28
PIU10AE29
PIU10AF14
PIU10AF15
PIU10AF17
PIU10AF18
PIU10AF23
PIU10AF24
PIU10AF28
PIU10AF29
PIU10AG29
PIU10AG30
PIU10AH29
PIU10AH30
PIU10F30
PIU10G30
COU1J
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
13 35
4/14/2015
k2l_soc_06_1.SchDoc
Sheet Title:
Size:
Mod. Date:
File:Sheet: of
B http://www.ti.comContact: http://www.ti.com/support
TI 66AK2L06 JESD Attach to Wideband ADCs and DACsProject Title:Designed for: Public Release
Assembly Variant: [No Variations]
© Texas Instruments 2015Drawn By:Engineer: a0271760
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Version control disabledSVN Rev:TIDEP0034Number: Rev: E1
TID #: TIDEP0034Orderable: EVM_orderable
TIMI0_AVSIFSEL0 J2
TIMI1_AVSIFSEL1 J1
TIMO1_CSISC20CLKCTL J3
USIMRSTF1USIMIOF2USIMCLKF3
TIMO0_CSISC20MUX H3
UART1RTS_SPI2SIMO J4
UART1TXD J5
UART0RTS_SPI2SCS0 K2
SPI0SCS1K28
SPI0SCS3K29
UART0TXD K3
SPI0SCS2K30
UART1CTS_SPI2SOMI K4
UART0RXD K5
SPI1SOMIL26
SPI0SIMOL27
SPI1SCS1L28
SPI0CLKL29
SCL1L3
SPI0SCS0L30
UART0CTS_SPI2CLK L4
UART1RXD L5SDA0M2
SPI1CLKM26
SPI1SCS2M27
SPI1SCS0M28
SPI0SCS4M29
SCL2M3
SDA2M4
SDA1M5
SCL0N2
SPI1SIMON26
SPI0SOMIN27
I2C1
I2C0
I2C2
SPI0
SPI1
USIM
UART0/SPI2
UART1/SPI2
TIMER1/Bootstrap
TIMER0/Bootstrap
U1N
TCI6630K2L
K2L Boot-Config, I2C, SPI, UART, Timer, and USIM
K2L_TIMI0_AVSIFSEL0K2L_TIMO0_CSISC20MUX
K2L_TIMI1_AVSIFSEL1K2L_TIMO1_CSISC20CLKCTL
K2L_ADC_SPI0CLK K2L_ADC_SPI0CLK_RSK2L_ADC_SPI0SIMO K2L_ADC_SPI0SIMO_RSK2L_ADC_SPI0SOMI
K2L_ADC_SPI0SCS0 K2L_ADC_SPI0SCS0_RS
K2L_SPI0CLKK2L_SPI0SIMOK2L_SPI0SOMI
K2L_TIMO0K2L_TIMI0
K2L_TIMI1K2L_TIMO1
K2L_SPI0SCS0
10.0R1710.0R18
10.0R19
K2L_DAC_SPI1CLK K2L_DAC_SPI1CLK_RSK2L_DAC_SPI1SIMO K2L_DAC_SPI1SIMO_RSK2L_DAC_SPI1SOMI
K2L_DAC_SPI1SCS0 K2L_DAC_SPI1SCS0_RS
K2L_SPI1CLKK2L_SPI1SIMOK2L_SPI1SOMI
K2L_SPI1SCS0
10.0R2010.0R21
10.0R22
K2L_SCL1K2L_SDA1K2L_SCL1
K2L_SDA1
4.75kR15
VSYS_DVDD1V8
4.75kR16
TI K2L Demo 1 software utilizes SPI_0 for controlling ADC
TI K2L Demo 1 software utilizes SPI_1 for controlling DAC
TI K2L Demo 1 software utilizes I2C_0 for configuring/reading ADC temperature sensor.
I2C0 utilized for Smart-Reflex control of TPS544x24 CVDD power supply. Solution not shown here. Please see K2L EVM schematics.
PIR1501
PIR1502COR15
PIR1601
PIR1602COR16
PIR1701 PIR1702COR17
PIR1801 PIR1802COR18
PIR1901 PIR1902COR19
PIR2001 PIR2002COR20
PIR2101 PIR2102COR21
PIR2201 PIR2202COR22
PIU10F1
PIU10F2
PIU10F3
PIU10H3
PIU10J1
PIU10J2
PIU10J3
PIU10J4
PIU10J5
PIU10K2
PIU10K3
PIU10K4
PIU10K5
PIU10K28
PIU10K29
PIU10K30
PIU10L3
PIU10L4
PIU10L5
PIU10L26
PIU10L27
PIU10L28
PIU10L29
PIU10L30
PIU10M2
PIU10M3
PIU10M4
PIU10M5
PIU10M26
PIU10M27
PIU10M28
PIU10M29
PIU10N2
PIU10N26
PIU10N27
COU1N
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
15 35
4/15/2015
k2l_soc_08.SchDoc
Sheet Title:
Size:
Mod. Date:
File:Sheet: of
B http://www.ti.comContact: http://www.ti.com/support
TI 66AK2L06 JESD Attach to Wideband ADCs and DACsProject Title:Designed for: Public Release
Assembly Variant: [No Variations]
© Texas Instruments 2015Drawn By:Engineer: a0271760
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Version control disabledSVN Rev:TIDEP0034Number: Rev: E1
TID #: TIDEP0034Orderable: EVM_orderable
SHARED_SERDES_1_REFRESAE13RSV_018AE15
SHARED_SERDES_0_REFRESAE17RSV017AF20
SHARED_SERDES_1_TXN1 AG15SHARED_SERDES_1_TXP1 AG16
SHARED_SERDES_0_TXN1 AG18SHARED_SERDES_0_TXP1 AG19
SHARED_SERDES_1_TXN0 AH14SHARED_SERDES_1_TXP0 AH15
SHARED_SERDES_0_TXN0 AH17SHARED_SERDES_0_TXP0 AH18
SHARED_SERDES_1_RXP0AJ15
SHARED_SERDES_1_RXN0AJ16
SHARED_SERDES_0_RXP0AJ18
SHARED_SERDES_1_RXP1AK16
SHARED_SERDES_1_RXN1AK17
SHARED_SERDES_0_RXP1AK19
SHARED_SERDES_0_RXN1AK20
SHARED_SERDES_0_RXN0AJ19
CSISC2_0 - AIL/JESD
CSISC2_1 - JESD
U1P
TCI6630K2L
K2L_JESD_RXP0_CAPK2L_JESD_RXN0_CAP
K2L_JESD_RXP1_CAPK2L_JESD_RXN1_CAP
K2L_JESD_TXP0K2L_JESD_TXN0
K2L_JESD_TXP1K2L_JESD_TXN1
K2L_JESD_TXP2K2L_JESD_TXN2
K2L_JESD_TXP3K2L_JESD_TXN3
DFESYSREFPAE30
DFESYNCINP1_RP1FBPAF10
DFESYNCINN1_RP1FBNAF11
DFESYSREFNAF30
DFEIO14_GPIO60AF9
DFEIO10_GPIO56AG10
DFESYNCINP0_RP1CLKPAG12
DFESYNCINN0_RP1CLKNAG13
DFEIO2_GPIO48AG7
DFEIO7_GPIO53AG8
DFEIO16_GPIO62AG9
DFESYNCOUTP1 AH11
DFESYNCOUTN1 AH12
DFEIO0AH5
DFEIO4_GPIO50AH7
DFEIO17_GPIO63AH9
DFESYNCOUTN0 AJ10
DFEIO1AJ5
DFEIO11_GPIO57AJ6
DFEIO6_GPIO52AJ7
DFESYNCOUTP0 AJ9
DFEIO12_GPIO58AK10
DFEIO15_GPIO61AK11
DFEIO3_GPIO49AK5
DFEIO5_GPIO51AK6
DFEIO9_GPIO55AK7DFEIO8_GPIO54AK8
DFEIO13_GPIO59AK9
Digital Radio Front-End
U1S
TCI6630K2L
3.0k
R41
GND
3.0k
R42
GND
DFE JESD204B SERDES
K2L_SERDES1_REF
K2L_SERDES0_REF
0.1µFC272
0.1µFC2730.1µFC274
0.1µFC275
0.1µFC276
0.1µFC2770.1µFC278
0.1µFC279
K2L_JESD_RXP0K2L_JESD_RXN0
K2L_JESD_RXP1K2L_JESD_RXN1
K2L_JESD_RXP2K2L_JESD_RXN2
K2L_JESD_RXP3K2L_JESD_RXN3
K2L_JESD_RXP2_CAPK2L_JESD_RXN2_CAP
K2L_JESD_RXP3_CAPK2L_JESD_RXN3_CAP
K2L_DFESYSREFPK2L_DFESYSREFN
K2L_DFEIO00K2L_DFEIO01K2L_DFEIO02K2L_DFEIO03K2L_DFEIO04K2L_DFEIO05K2L_DFEIO06K2L_DFEIO07K2L_DFEIO08K2L_DFEIO09K2L_DFEIO10K2L_DFEIO11K2L_DFEIO12K2L_DFEIO13K2L_DFEIO14K2L_DFEIO15K2L_DFEIO16K2L_DFEIO17
K2L_JESD_RXP0K2L_JESD_RXN0
K2L_JESD_RXP1K2L_JESD_RXN1
K2L_JESD_RXP2K2L_JESD_RXN2
K2L_JESD_RXP3K2L_JESD_RXN3
K2L_JESD_TXP0K2L_JESD_TXN0
K2L_JESD_TXP1K2L_JESD_TXN1
K2L_JESD_TXP2K2L_JESD_TXN2
K2L_JESD_TXP3K2L_JESD_TXN3
K2L_DFESYSREFNK2L_DFESYSREFP
K2L_DFEIO[17..00] K2L_DFEIO[17..00]
DFE JESD204B SYSREF, SYNCIN/OUT and DFE I/O
DAC_SYNCBPDAC_SYNCBN
K2L_DFESYNCIN_N1K2L_DFESYNCIN_P1
K2L_DFESYNCOUT_P0K2L_DFESYNCOUT_N0
K2L_DFESYNCOUT_P1K2L_DFESYNCOUT_N1
K2L_DFESYNCOUT_P0K2L_DFESYNCOUT_N0
DAC_SYNCBP1DAC_SYNCBN1
K2L_DFESYSREFPK2L_DFESYSREFN
DAC_SYNCBPDAC_SYNCBN
TI 66AK2L06 Product Page
Keystone2 Hardware Design Guide (SPRAVB0)
Keystone2 SERDES User Guide (SPRUHO3)
JESDTX[3:0] Output to DACJESDRX[3:0] input from ADC
JESD204B SYSREF and SYNC shall be utilized according to DFE User Guide (SPRUHX8) and routed according to Keystone 2 Hardware Design Guide (SPRAVB0) DFE peripheral section.
JESD204B SERDES shall be routed according to routing rules specified in the Keystone 2 SERDES User Guide (SPRUH03)
K2L DFESYNCIN0 driven by DAC SYNC output
K2L DFESYNCOUT0 drives ADC SYNC input
K2L SYSREF driven by LMK04828
For schematic and layout recommendations and requirements see the K2L product page linked below.
PIC27201PIC27202COC272
PIC27301PIC27302COC273
PIC27401PIC27402COC274
PIC27501PIC27502COC275
PIC27601PIC27602COC276
PIC27701PIC27702COC277
PIC27801PIC27802COC278
PIC27901PIC27902COC279
PIDAC0SYNCBN101CODAC0SYNCBN1
PIDAC0SYNCBP101CODAC0SYNCBP1
PIK2L0DFESYSREFN01COK2L0DFESYSREFN
PIK2L0DFESYSREFP01COK2L0DFESYSREFP
PIR4101 PIR4102COR41
PIR4201 PIR4202COR42
PIU10AE13
PIU10AE15
PIU10AE17
PIU10AF20
PIU10AG15
PIU10AG16
PIU10AG18
PIU10AG19
PIU10AH14
PIU10AH15
PIU10AH17
PIU10AH18
PIU10AJ15
PIU10AJ16
PIU10AJ18
PIU10AJ19
PIU10AK16
PIU10AK17
PIU10AK19
PIU10AK20
COU1P
PIU10AE30
PIU10AF9
PIU10AF10
PIU10AF11
PIU10AF30
PIU10AG7
PIU10AG8
PIU10AG9
PIU10AG10
PIU10AG12
PIU10AG13
PIU10AH5
PIU10AH7
PIU10AH9
PIU10AH11
PIU10AH12
PIU10AJ5
PIU10AJ6
PIU10AJ7
PIU10AJ9
PIU10AJ10
PIU10AK5
PIU10AK6
PIU10AK7
PIU10AK8
PIU10AK9
PIU10AK10
PIU10AK11
COU1S
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
25 35
4/14/2015
adc12j4000_01.SchDoc
Sheet Title:
Size:
Mod. Date:
File:Sheet: of
B http://www.ti.comContact: http://www.ti.com/support
TI 66AK2L06 JESD Attach to Wideband ADCs and DACsProject Title:Designed for: Public Release
Assembly Variant: [No Variations]
© Texas Instruments 2015Drawn By:Engineer: a0271760
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Version control disabledSVN Rev:TIDEP0034Number: Rev: E1
TID #: TIDEP0034Orderable: EVM_orderable
VADC_1V9
10µFC346
VADC_1V2
0.1µF
C343
0.1µF
C344
0.1µF
C345
1µFC348
1µFC347
VA126
VA1211
VA1214
VA1217
VA1218
VA1221
VA1265
VD12 28
VD12 31
VD12 34
VD12 37
VD12 40
VD12 43
VD12 46
VD12 49
VD12 52VA194
VA197
VA1910
VA1913
VA1924
VA1927
VA1960
VA1962
VD12 55
GND PAD 69
U3B
ADC12J4000NKE
0.1µF
C336
0.1µF
C337
0.1µF
C338
0.1µF
C339
0.1µF
C340
0.1µF
C341
0.1µF
C342
ADC Power Pins and Decoupling Capacitors
VADC_1V2
VADC_1V2
10µF
C358
0.1µF
C355
0.1µF
C356
0.1µF
C357
0.1µF
C354
1µF
C350
1µF
C349
0.1µF
C352
0.1µF
C353
0.1µF
C351120 ohm
L13
V_ADC_IO_1V2A
V_ADC_IO_1V2A
VADC_1V9
10µFC335
0.1µF
C334
1µF
C326
1µF
C325
0.1µF
C327
0.1µF
C328
0.1µF
C329
0.1µF
C330
0.1µF
C331
0.1µF
C332
0.1µF
C333
The ADC thermal pad is the only ground connection for this IC. Ensure good connection through multiple vias to the PCB ground planes.
Decoupling caps shall be placed as close to ADC power pins as possible.
PIC32501
PIC32502
COC325PIC32601
PIC32602
COC326
PIC32701
PIC32702COC327
PIC32801
PIC32802COC328
PIC32901
PIC32902COC329
PIC33001
PIC33002COC330
PIC33101
PIC33102COC331
PIC33201
PIC33202COC332
PIC33301
PIC33302COC333
PIC33401
PIC33402COC334PIC33501
PIC33502COC335
PIC33601
PIC33602COC336
PIC33701
PIC33702COC337
PIC33801
PIC33802COC338
PIC33901
PIC33902COC339
PIC34001
PIC34002COC340
PIC34101
PIC34102COC341
PIC34201
PIC34202COC342
PIC34301
PIC34302COC343
PIC34401
PIC34402COC344
PIC34501
PIC34502COC345PIC34601
PIC34602COC346PIC34701
PIC34702COC347
PIC34801
PIC34802COC348
PIC34901
PIC34902
COC349PIC35001
PIC35002
COC350
PIC35101
PIC35102COC351
PIC35201
PIC35202COC352
PIC35301
PIC35302COC353
PIC35401
PIC35402COC354
PIC35501
PIC35502COC355
PIC35601
PIC35602COC356
PIC35701
PIC35702COC357PIC35801
PIC35802COC358
PIL1301 PIL1302
COL13
PIU304
PIU306
PIU307
PIU3010
PIU3011
PIU3013
PIU3014
PIU3017
PIU3018
PIU3021
PIU3024
PIU3027
PIU3028
PIU3031
PIU3034
PIU3037
PIU3040
PIU3043
PIU3046
PIU3049
PIU3052
PIU3055
PIU3060
PIU3062
PIU3065
PIU3069
COU3B
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
26 35
4/14/2015
adc12j4000_02.SchDoc
Sheet Title:
Size:
Mod. Date:
File:Sheet: of
B http://www.ti.comContact: http://www.ti.com/support
TI 66AK2L06 JESD Attach to Wideband ADCs and DACsProject Title:Designed for: Public Release
Assembly Variant: [No Variations]
© Texas Instruments 2015Drawn By:Engineer: a0271760
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Version control disabledSVN Rev:TIDEP0034Number: Rev: E1
TID #: TIDEP0034Orderable: EVM_orderable
VIN+8
VIN-9
OR_T0 25
OR_T1 26
DS7+/NCO_2 54
DS7-/NC 53
DS6+/NCO_1 51
DS6-/NC 50
DS5+/NCO_0 48
DS5-/NC 47
DS4+ 45
DS4- 44
DS3+ 42
DS3- 41
DS2+ 39
DS2- 38
DS1+ 36
DS1- 35
DS0+ 33
DS0- 32
VNEG15
VNEG212
VNEG_OUT29
RBIAS+1
RBIAS-2
DNC67
RSV66
VBG68
VCMO3
Tdiode+ 64
Tdiode- 63
DEVCLK+15
DEVCLK-16
SYSREF+19
SYSREF-20
SYNC~+/TMST+22
SYNC~-/TMST-23
SYNC~30SCS 59
SDI 57
SCLK 58
SDO 56
RSV261
U3A
ADC12J4000NKE
ADC_VIN_PADC_VIN_N
3.30kR79
ADC_VBG1
ADC_VCMO1
ADC_DEVCLKNADC_DEVCLKP
D4_PD4_ND5_PD5_ND6_PD6_ND7_PD7_N
10.0kR76
10.0kR78
10.0kR77
ADC_SYSREFPADC_SYSREFP
ADC_RBIASP
ADC_RBIASN
0.1µF
C359
0.1µF
C360
4.7µFC361
10.0R83
K2L_SPI0CLKK2L_SPI0SIMO
K2L_SPI0SOMI_RSK2L_SPI0SCS0 K2L_SPI0SCS0K2L_SPI0SOMI
K2L_SPI0SIMOK2L_SPI0SOMI
K2L_SPI0CLK
K2L_JESD_RXP0K2L_JESD_RXN0K2L_JESD_RXP1K2L_JESD_RXN1K2L_JESD_RXP2K2L_JESD_RXN2K2L_JESD_RXP3K2L_JESD_RXN3
K2L_JESD_RXP0K2L_JESD_RXN0K2L_JESD_RXP1K2L_JESD_RXN1K2L_JESD_RXP2K2L_JESD_RXN2K2L_JESD_RXP3K2L_JESD_RXN3
ADC_VNEG1ADC_VNEG2
ADC_VNEG_OUT
ADC_DEVCLKPADC_DEVCLKN
ADC_SYSREFPADC_SYSREFP
ADC Input, JESD204B Interface, SPI and Discrete I/O Control
K2L_DFESYNCOUT_P0K2L_DFESYNCOUT_N0K2L_DFESYNCOUT_P0
K2L_DFESYNCOUT_N0
K4K5
ADC_DEVCLKP1ADC_DEVCLKN1
ADC_SYSREFP1ADC_SYSREFN1
K7K6
K9K8
K2L_DFEIO02
K2L_DFEIO[17..00]K2L_DFEIO[17..00]
K2L_DFEIO03K2L_DFEIO04
ADC_NCO_2ADC_NCO_1
ADC_NCO_3
ADC_OR_T2ADC_OR_T1
ADC_VIN_PADC_VIN_N
ADC_TDIODEPADC_TDIODEN 10.0k
R8010.0kR81
K2L_DFEIO05K2L_DFEIO06
0.1µFC363
GND8
A0 9
SMBCLK 13
D2+6 TCRIT2 11
NC 1
TCRIT1 10
D-5
NC3
TCRIT3 14
SMBDAT 12
NC4
VDD2
D1+7
DAP15
U4
LM95233CISD/NOPB
10µFC362
10.0kR90
10.0kR91
10.0kR92100pF
C364
100pFC366
100pFC365
TCRIT3
TCRIT2
TCRIT1 TCRIT3
TCRIT1
1.3kR88
1.3kR89
RedADC TEMP1
750R93
ADC_TDIODEPADC_TDIODEN
K2L_SCL1K2L_SDA1 K2L_SCL1
K2L_SDA1
ADC Temperature Sensor
1.00kR95
4.75kR94
VSYS_DVDD3V3
VSYS_3V3D
VSYS_DVDD3V3
K2L_DFEIO08
3
1
2
Q1CSD17483F4T
RedOR_T1
K2L_DFEIO06
49.9R86
3
1
2
Q2CSD17483F4T
RedOR_T2
K2L_DFEIO05
49.9R87
VSYS_DVDD3V3 VSYS_DVDD3V3
0R84
0R85
VSYS_1V9D 10.0kR82 K2L_DFEIO07
ADC_VBG
ADC_VCMO
TCRIT2
ADC_SYNC~1
TI ADC12J4000 Product Page
ADC input signal signal conditioning (bal-un, op-amps...etc) is not shown here.
The input circuit required is application and system specific. Please see ADC12J4000 datasheet, application notes and EVM design guide for specific recommendations.
TI K2L Demo1 software shall control decimation filter through SPI registers. This is an optional usage of the discrete decimation control using available K2L DFEIO pins.
Place LM95233 close to ADCJ124000 TDIODE pins to keep ADC_TDIODE net short.
ADC_DEVCLK is a 1GHz+ signal. It needs to be specially routed, and GND isolated in a similar manner to the JESD SERDES channels.
ADC discrete input and output routed to K2L DFEIO/GPIO bus for control by K2L software.
TI K2L Demo 1 software shall utilize the differential, LVDS SYNC+/- interface. Utilizing the SYNC pin is an optional usage of the K2L DFEIO pins to source the SYNC signal to the ADC.
See ADC12J4000 datasheet for implemenation details.
TI K2L Demo 1 only utilizing ADC SERDES lane 0 and lane 1. Recommend hardware implemenations to included all lanes possible for maximum design flexibility.
ADC SYSREF driven by LMK04828
ADC DEVCLK driven by LMK04828
ADC SPI port mastered by K2L SPI_0
For schematic and layout recommendations and requirements see the ADC12J4000 product page linked below.
PIADC0DEVCLKN101COADC0DEVCLKN1
PIADC0DEVCLKP101COADC0DEVCLKP1
PIADC0NCO0101COADC0NCO01
PIADC0NCO0201COADC0NCO02
PIADC0NCO0301COADC0NCO03
PIADC0OR0T101COADC0OR0T1
PIADC0OR0T201COADC0OR0T2
PIADC0SYNC~101COADC0SYNC~1
PIADC0SYSREFN101COADC0SYSREFN1
PIADC0SYSREFP101COADC0SYSREFP1
PIADC0VBG101COADC0VBG1
PIADC0VCMO101COADC0VCMO1
PIADC TEMP101
PIADC TEMP102COADC TEMP1
PIC35901
PIC35902 COC359
PIC36001
PIC36002 COC360
PIC36101
PIC36102COC361
PIC36201
PIC36202COC362
PIC36301
PIC36302COC363
PIC36401
PIC36402COC364
PIC36501
PIC36502COC365
PIC36601
PIC36602COC366
PIK401COK4
PIK501COK5
PIK601COK6
PIK701COK7
PIK801COK8
PIK901COK9
PIOR0T101
PIOR0T102COOR0T1
PIOR0T201
PIOR0T202COOR0T2
PIQ101
PIQ102
PIQ103COQ1
PIQ201
PIQ202
PIQ203COQ2
PIR7601
PIR7602COR76
PIR7701
PIR7702COR77
PIR7801
PIR7802COR78
PIR7901 PIR7902COR79
PIR8001
PIR8002COR80
PIR8101
PIR8102COR81
PIR8201PIR8202COR82
PIR8301 PIR8302COR83
PIR8401
PIR8402COR84
PIR8501
PIR8502COR85
PIR8601
PIR8602COR86
PIR8701
PIR8702COR87
PIR8801
PIR8802COR88
PIR8901
PIR8902COR89
PIR9001
PIR9002COR90
PIR9101
PIR9102COR91
PIR9201
PIR9202COR92
PIR9301
PIR9302COR93
PIR9401
PIR9402COR94
PIR9501
PIR9502COR95
PITCRIT101
COTCRIT1
PITCRIT201
COTCRIT2PITCRIT301
COTCRIT3
PIU301
PIU302
PIU303
PIU305
PIU308
PIU309
PIU3012
PIU3015
PIU3016
PIU3019
PIU3020
PIU3022
PIU3023
PIU3025
PIU3026
PIU3029
PIU3030
PIU3032
PIU3033
PIU3035
PIU3036
PIU3038
PIU3039
PIU3041
PIU3042
PIU3044
PIU3045
PIU3047
PIU3048
PIU3050
PIU3051
PIU3053
PIU3054
PIU3056
PIU3057
PIU3058
PIU3059
PIU3061
PIU3063
PIU3064
PIU3066
PIU3067
PIU3068
COU3A
PIU401
PIU402
PIU403
PIU404
PIU405
PIU406
PIU407
PIU408
PIU409
PIU4010
PIU4011
PIU4012
PIU4013
PIU4014
PIU4015
COU4
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
27 35
4/15/2015
dac38j84_01.SchDoc
Sheet Title:
Size:
Mod. Date:
File:Sheet: of
B http://www.ti.comContact: http://www.ti.com/support
TI 66AK2L06 JESD Attach to Wideband ADCs and DACsProject Title:Designed for: Public Release
Assembly Variant: [No Variations]
© Texas Instruments 2015Drawn By:Engineer: a0271760
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Version control disabledSVN Rev:TIDEP0034Number: Rev: E1
TID #: TIDEP0034Orderable: EVM_orderable
VDDCLK09_1A8
VDDCLK09_2B8
VDDAC09_1D9
VDDAC09_2E9
VDDAC09_3F9
VDDAC09_4G9
VDDAC09_5H9
VDDAC09_6J9
VDDT09_1F3
VDDT09_2G3
VDDIG09_1D3
VDDIG09_2D4
VDDIG09_3E4
VDDIG09_4F4
VDDIG09_5G4
VDDIG09_6H4
VDDIG09_7J4
VDDIG09_8D5
VDDIG09_9J5
VDDIG09_10J6
VDDIG09_11J7
VDDIO18_1K6
VDDIO18_2K7
VDDAPLL18_1B9
VDDAPLL18_2B10
VDDR18_1F2
VDDR18_2G2
VDDS18_1C6
VDDS18_2C7
VDDADAC33_1D10
VDDADAC33_2E10
VDDADAC33_3H10
VDDADAC33_4J10
GND1 A12
GND2 F12
GND3 G12
GND4 M12
GND5 A11
GND6 B11
GND7 C11
GND8 D11
GND9 E11
GND10 F11
GND11 G11
GND12 H11
GND13 J11
GND14 K11
GND15 L11
GND16 M11
GND17 C8
GND18 D8
GND19 E8
GND20 F8
GND21 G8
GND22 H8
GND23 J8
GND24 E7
GND25 F7
GND26 G7
GND27 H7
GND28 E6
GND29 F6
GND30 G6
GND31 H6
GND32 A5
GND33 B5
GND34 E5
GND35 F5
GND36 G5
GND37 H5
GND38 A5
GND39 B4
GND40 M4VQPS18_1D6
VQPS18_2D7
VDDAREF18_1C10
VDDAREF18_2K10
GND41 B3
GND42 C3
GND43 L3
GND44 B2
GND45 C2
GND46 D2
GND47 E2
GND48 H2
GND49 J2
GND50 K2
GND51 L2
U5B
DAC38J84
VSYS_DVDD0V9
VSYS_DVDD1V8
120 ohm
L14
VSYS_DVDD0V9 VSYS_DVDD0V9
VSYS_DVDD1V8
0.01µF
C371
1µF
C372
1µF
C370
0.01µF
C369
0.1µF
C368
0.1µF
C367
10µF
C373 120 ohm
L15
0.01µF
C382
1µF
C383
1µF
C381
0.01µF
C380
0.1µF
C375
0.1µF
C374
10µF
C384
120 ohm
L16
0.01µF
C410
1µF
C411
1µF
C409
0.01µF
C408
0.1µF
C407
0.1µF
C406
10µF
C412
0.1µF
C377
0.1µF
C376
0.1µF
C379
0.1µF
C378
DAC VDDCLK09 Decoupling
DAC VDDIG09 Decoupling
DAC VDDAC09 Decoupling
VSYS_DVDD0V9DAC VDDT09 Decoupling VSYS_DVDD0V9
1µF
C400
10µF
C401
VSYS_DVDD0V9
0.1µF
C395
0.1µF
C394
0.1µF
C397
0.1µF
C396
0.1µF
C399
0.1µF
C398
0.1µF
C390
0.1µF
C389
0.1µF
C392
0.1µF
C391
0.1µF
C393
VSYS_DVDD1V8
1µF
C404
10µF
C405
0.1µF
C403
0.1µF
C402
0.1µF
C386
0.1µF
C385
10µF
C388
1µF
C387
DAC VDDIO18 Decoupling DAC VDDAPLL18 Decoupling
VDD_DAC_CLK0V9
VDDAC_DAC_0V9
VDD_DAC_CLK0V9 VDDAC_DAC_0V9
VDDAPLL_DAC_1V8
VDDAPLL_DAC_1V8
VSYS_DVDD1V8
0.01µF
C423
1µF
C424
10µF
C425
DAC VDDS18/VQPS18 DecouplingVSYS_DVDD1V8
120 ohm
L17
0.01µF
C417
1µF
C418
1µF
C416
0.01µF
C415
0.1µF
C414
0.1µF
C413
10µF
C419
DAC VDDR18 DecouplingVDDR_DAC_1V8
VDDAREF_DAC_1V8
VSYS_DVDD1V8
120 ohm
L18
0.01µF
C430
1µF
C431
1µF
C429
0.01µF
C428
0.1µF
C427
0.1µF
C426
10µF
C432
DAC VDDR18 Decoupling
VDDR_DAC_1V8
VDDAREF_DAC_1V8
0.01µF
C422
0.01µF
C421
0.01µF
C420
VDDA_DAC_3V3
VSYS_DVDD3V3
120 ohm
L19
0.01µF
C439
1µF
C440
10µF
C441
1µF
C438
0.01µF
C437
0.1µF
C436
0.1µF
C435
0.1µF
C434
0.1µF
C433
VDDA_DAC_3V3
DAC VDDADAC33 Decoupling
VSYS_DVDD1V8
PIC36701
PIC36702 COC367
PIC36801
PIC36802 COC368PIC36901
PIC36902
COC369PIC37001
PIC37002
COC370 PIC37101
PIC37102
COC371PIC37201
PIC37202
COC372PIC37301
PIC37302
COC373
PIC37401
PIC37402 COC374
PIC37501
PIC37502 COC375
PIC37601
PIC37602 COC376
PIC37701
PIC37702 COC377
PIC37801
PIC37802 COC378
PIC37901
PIC37902 COC379PIC38001
PIC38002
COC380PIC38101
PIC38102
COC381 PIC38201
PIC38202
COC382PIC38301
PIC38302
COC383PIC38401
PIC38402
COC384
PIC38501
PIC38502 COC385
PIC38601
PIC38602 COC386PIC38701
PIC38702
COC387PIC38801
PIC38802
COC388
PIC38901
PIC38902 COC389
PIC39001
PIC39002 COC390
PIC39101
PIC39102 COC391
PIC39201
PIC39202 COC392
PIC39301
PIC39302 COC393
PIC39401
PIC39402 COC394
PIC39501
PIC39502 COC395
PIC39601
PIC39602 COC396
PIC39701
PIC39702 COC397
PIC39801
PIC39802 COC398
PIC39901
PIC39902 COC399PIC40001
PIC40002
COC400PIC40101
PIC40102
COC401
PIC40201
PIC40202 COC402
PIC40301
PIC40302 COC403PIC40401
PIC40402
COC404PIC40501
PIC40502
COC405
PIC40601
PIC40602 COC406
PIC40701
PIC40702 COC407PIC40801
PIC40802
COC408PIC40901
PIC40902
COC409 PIC41001
PIC41002
COC410PIC41101
PIC41102
COC411PIC41201
PIC41202
COC412
PIC41301
PIC41302 COC413
PIC41401
PIC41402 COC414PIC41501
PIC41502
COC415PIC41601
PIC41602
COC416 PIC41701
PIC41702
COC417PIC41801
PIC41802
COC418PIC41901
PIC41902
COC419 PIC42001
PIC42002
COC420PIC42101
PIC42102
COC421PIC42201
PIC42202
COC422PIC42301
PIC42302
COC423PIC42401
PIC42402
COC424PIC42501
PIC42502
COC425
PIC42601
PIC42602 COC426
PIC42701
PIC42702 COC427PIC42801
PIC42802
COC428PIC42901
PIC42902
COC429 PIC43001
PIC43002
COC430PIC43101
PIC43102
COC431PIC43201
PIC43202
COC432
PIC43301
PIC43302 COC433
PIC43401
PIC43402 COC434
PIC43501
PIC43502 COC435
PIC43601
PIC43602 COC436 PIC43701
PIC43702
COC437PIC43801
PIC43802
COC438 PIC43901
PIC43902
COC439PIC44001
PIC44002
COC440PIC44101
PIC44102
COC441
PIL1401 PIL1402
COL14PIL1501 PIL1502
COL15
PIL1601 PIL1602COL16
PIL1701 PIL1702COL17
PIL1801 PIL1802
COL18
PIL1901 PIL1902
COL19
PIU50A5
PIU50A8
PIU50A11
PIU50A12
PIU50B2
PIU50B3
PIU50B4
PIU50B5
PIU50B8
PIU50B9
PIU50B10
PIU50B11
PIU50C2
PIU50C3
PIU50C6
PIU50C7
PIU50C8
PIU50C10
PIU50C11
PIU50D2
PIU50D3
PIU50D4
PIU50D5
PIU50D6
PIU50D7
PIU50D8
PIU50D9
PIU50D10
PIU50D11
PIU50E2
PIU50E4
PIU50E5
PIU50E6
PIU50E7
PIU50E8
PIU50E9
PIU50E10
PIU50E11
PIU50F2
PIU50F3
PIU50F4
PIU50F5
PIU50F6
PIU50F7
PIU50F8
PIU50F9
PIU50F11
PIU50F12
PIU50G2
PIU50G3
PIU50G4
PIU50G5
PIU50G6
PIU50G7
PIU50G8
PIU50G9
PIU50G11
PIU50G12
PIU50H2
PIU50H4
PIU50H5
PIU50H6
PIU50H7
PIU50H8
PIU50H9
PIU50H10
PIU50H11
PIU50J2
PIU50J4
PIU50J5
PIU50J6
PIU50J7
PIU50J8
PIU50J9
PIU50J10
PIU50J11
PIU50K2
PIU50K6
PIU50K7
PIU50K10
PIU50K11
PIU50L2
PIU50L3
PIU50L11
PIU50M4
PIU50M11
PIU50M12
COU5B
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
28 35
4/14/2015
dac38j84_02.SchDoc
Sheet Title:
Size:
Mod. Date:
File:Sheet: of
B http://www.ti.comContact: http://www.ti.com/support
TI 66AK2L06 JESD Attach to Wideband ADCs and DACsProject Title:Designed for: Public Release
Assembly Variant: [No Variations]
© Texas Instruments 2015Drawn By:Engineer: a0271760
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Version control disabledSVN Rev:TIDEP0034Number: Rev: E1
TID #: TIDEP0034Orderable: EVM_orderable
DACCLKPA10
DACCLKNA9
SYSREFPA7
SYSREFNA6
RX7PA3
RX7NA2
RX6PB1
RX6NA1
RX5PC1
RX5ND1
RX4PF1
RX4NE1
RX3PM3
RX3NM2
RX2PL1
RX2NM1
RX1PK1
RX1NJ1
RX0PG1
RX0NH1
SYNCBPB7
SYNCBNB6
AMUX0H3
AMUX1E3
LPF C9
IOUTAP B12
IOUTAN C12
IOUTBP E12
IOUTBN D12
IOUTCP H12
IOUTCN J12
IOUTDP L12
IOUTDN K12
TXENABLE K5
EXTIO F10
RBIAS G10
U5A
DAC38J84
SDIOL10
SDENBM9
SCLKL9
SDOM10
TCLKK4
TDIL5
TDOM5
TMSL4
TRSTBJ3
RESETBK8
SLEEPM8
IFORCE C5
VSENSE C4
ATEST K9
ALARM L8
TESTMODE K3
NC4 M7NC3 M6
SYNC_N_CD L7SYNC_N_AB L6
U5C
DAC38J84
0.1µFC448
0.1µFC4490.1µFC450
0.1µFC4510.1µFC452
0.1µFC4530.1µFC454
0.1µFC455
K2L_JESD_TXP0K2L_JESD_TXN0K2L_JESD_TXP0
K2L_JESD_TXN0
K2L_JESD_TXP1K2L_JESD_TXN1K2L_JESD_TXP1
K2L_JESD_TXN1
K2L_JESD_TXP2K2L_JESD_TXN2K2L_JESD_TXN2
K2L_JESD_TXP2
K2L_JESD_TXP3K2L_JESD_TXN3K2L_JESD_TXN3
K2L_JESD_TXP3 K2L_JESD_TXP3_CSK2L_JESD_TXN3_CS
K2L_JESD_TXP0_CSK2L_JESD_TXN0_CS
K2L_JESD_TXP1_CSK2L_JESD_TXN1_CS
K2L_JESD_TXP2_CSK2L_JESD_TXN2_CS
DAC_SYNCBPDAC_SYNCBN
DAC_AMUX0DAC_AMUX1
K2L_DFEIO09
0R97
1000pFC442
0.1µFC444
GND
1.00kR96
0.1µFC456
GND
DAC_EXTIO
DAC_RBIAS
DAC_EXTIO1
1.91kR99
GND
DAC_AMUX1DAC_AMUX2
DAC_SYNCBPDAC_SYNCBN
DAC_IOUTAPDAC_IOUTAN
DAC_IOUTBPDAC_IOUTBN
DAC_IOUTCPDAC_IOUTCN
DAC_IOUTDPDAC_IOUTDN
DAC_IOUTAPDAC_IOUTAN
DAC_IOUTBPDAC_IOUTBN
DAC_IOUTCPDAC_IOUTCN
DAC_IOUTDPDAC_IOUTDN
DAC_ALARM1
DAC_DACCLKPDAC_DACCLKN
DAC_SYSREFPDAC_SYSREFN
DAC_DACCLKNDAC_DACCLKP
DAC_SYSREFNDAC_SYSREFP
0.1µFC443
0.1µFC4450.1µFC446
0.1µFC447
DAC_DACCLKP_CSDAC_DACCLKN_CS
DAC_SYSREFP_CSDAC_SYSREFN_CS
DAC_IFORCE1DAC_VSENSE1DAC_ATEST1
DAC_TESTMODE1
DAC_IFORCEDAC_VSENSEDAC_ATEST
DAC_ALARMDAC_TESTMODE
K2L_DFEIO10
K2L_DFEIO11
0R103
GND
K2L_SPI1CLKK2L_SPI1SCS0
K2L_SPI1SOMI
K2L_SPI1SIMO
K2L_DAC_SPI1CLK10.0R100
K2L_DAC_SPI1SCS0K2L_DAC_SPI1SIMO
K2L_DAC_SPI1SOMI K2L_DAC_SPI1SOMI_RS
K10K11K12K13
DAC_RESET1
DAC_SLEEP1
K2L_DFEIO[17..00]K2L_DFEIO[17..00]
DAC_TXENABLE1
10.0kR98
GND
10.0kR101
GND
10.0kR102
GND
DAC Output, JESD204B Interface, SPI and Discrete I/O Control
TI DAC38J84 Product PageOptional external low-pass filter element. Shall be placed as close as possible to DAC BGA.
Please see DAC38J84 datasheet, application notes and EVM design guide for specific recommendations.
Rbias controls the full-scale current output according to datasheet equation:
IOUTFS = (coarse_dac + 1) /16 x IBIAS x 64 = (coarse_dac + 1) /16 x VEXTIO / RBIAS x 64
JTAG interface not utilized. JTAG subsystem held in reset per datasheet insuctions by TRSTB tied to GND.
TI K2L Demo 1 software shall utilize the differential, LVDS SYNCBP/N interface. Utilizing the SYNC_AB and SYNC_CD pins is an optional usage of the K2L DFEIO pins to recieve the SYNC signal from the DAC.
See DAC38J84 datasheet for implemenation details.
DAC output signal signal conditioning (bal-un, op-amps...etc) is not shown here. The output circuit required is application and system specific. Please see DAC38J84 datasheet, application notes and EVM design guide for specific recommendations.
DAC discrete input and output routed to K2L DFEIO/GPIO bus for control by K2L software.
TI K2L Demo 1 only utilizing DAC SERDES lane 0 and lane 1. Recommend hardware implemenations to included all lanes possible for maximum design flexibility.
DAC SYSREF driven by LMK04828 LVPECL source.
DAC DACCLK driven by LMK04828 LVPECL source.
DAC SPI port mastered by K2L SPI_1
For schematic and layout recommendations and requirements see the DAC38J84 product page linked below.
PIC44201PIC44202COC442
PIC44301PIC44302COC443
PIC44401PIC44402COC444
PIC44501PIC44502COC445
PIC44601PIC44602COC446
PIC44701PIC44702COC447
PIC44801PIC44802COC448
PIC44901PIC44902COC449
PIC45001PIC45002COC450
PIC45101PIC45102COC451
PIC45201PIC45202COC452
PIC45301PIC45302COC453
PIC45401PIC45402COC454
PIC45501PIC45502COC455
PIC45601PIC45602COC456
PIDAC0ALARM101CODAC0ALARM1
PIDAC0AMUX101CODAC0AMUX1
PIDAC0AMUX201CODAC0AMUX2
PIDAC0ATEST101CODAC0ATEST1
PIDAC0EXTIO101CODAC0EXTIO1
PIDAC0IFORCE101CODAC0IFORCE1
PIDAC0RESET101CODAC0RESET1
PIDAC0SLEEP101CODAC0SLEEP1
PIDAC0TESTMODE101 CODAC0TESTMODE1
PIDAC0TXENABLE101CODAC0TXENABLE1
PIDAC0VSENSE101CODAC0VSENSE1
PIK1001COK10
PIK1101COK11
PIK1201COK12
PIK1301COK13
PIR9601 PIR9602COR96
PIR9701 PIR9702COR97
PIR9801
PIR9802
COR98
PIR9901
PIR9902COR99
PIR10001 PIR10002COR100
PIR10101
PIR10102
COR101PIR10201
PIR10202
COR102
PIR10301
PIR10302COR103
PIU50A1
PIU50A2
PIU50A3
PIU50A6
PIU50A7
PIU50A9
PIU50A10
PIU50B1
PIU50B6
PIU50B7
PIU50B12
PIU50C1
PIU50C9
PIU50C12
PIU50D1
PIU50D12
PIU50E1
PIU50E3
PIU50E12
PIU50F1
PIU50F10
PIU50G1
PIU50G10
PIU50H1
PIU50H3
PIU50H12
PIU50J1
PIU50J12
PIU50K1
PIU50K5
PIU50K12
PIU50L1 PIU50L12
PIU50M1
PIU50M2
PIU50M3
COU5A
PIU50C4
PIU50C5
PIU50J3
PIU50K3PIU50K4
PIU50K8
PIU50K9
PIU50L4
PIU50L5
PIU50L6
PIU50L7
PIU50L8
PIU50L9
PIU50L10
PIU50M5
PIU50M6
PIU50M7
PIU50M8
PIU50M9
PIU50M10
COU5C
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
29 35
4/14/2015
lmk04828_01.SchDoc
Sheet Title:
Size:
Mod. Date:
File:Sheet: of
B http://www.ti.comContact: http://www.ti.com/support
TI 66AK2L06 JESD Attach to Wideband ADCs and DACsProject Title:Designed for: Public Release
Assembly Variant: [No Variations]
© Texas Instruments 2015Drawn By:Engineer: a0271760
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Version control disabledSVN Rev:TIDEP0034Number: Rev: E1
TID #: TIDEP0034Orderable: EVM_orderable
VSYS_DVDD3V3
0.1µFC513
0.01µFC518
0.1µFC514
0.1µFC515
0.1µFC516
0.1µFC517
1µFC512
GND
0.1µFC521
330 ohm
L21
VSYS_DVDD3V3 LMK_VCC2
0.1µFC522
GND GND
LMK04828 Decoupling Capacitors
0.1µFC519
330 ohm
L20
VSYS_DVDD3V3 LMK_VCC1
0.1µFC520
GND GND
0.1µFC525
330 ohm
L23
VSYS_DVDD3V3 LMK_VCC4
0.1µFC526
GND GND
0.1µFC523
330 ohm
L22
VSYS_DVDD3V3 LMK_VCC3
0.1µFC524
GND GND
0.1µFC529
330 ohm
L25
VSYS_DVDD3V3 LMK_VCC6
0.1µFC530
GND GND
0.1µFC527
330 ohm
L24
VSYS_DVDD3V3 LMK_VCC5
0.1µFC528
GND GND
0.1µFC533
330 ohm
L27
VSYS_DVDD3V3 LMK_VCC8
0.1µFC534
GND GND
0.1µFC531
330 ohm
L26
VSYS_DVDD3V3 LMK_VCC7
0.1µFC532
GND GND
0.1µFC537
330 ohm
L29
VSYS_DVDD3V3 LMK_VCC10
0.1µFC538
GND GND
0.1µFC535
330 ohm
L28
VSYS_DVDD3V3 LMK_VCC9
0.1µFC536
GND GND
0.1µFC541
330 ohm
L31
VSYS_DVDD3V3 LMK_VCC12
0.1µFC542
GND GND
0.1µFC539
330 ohm
L30
VSYS_DVDD3V3 LMK_VCC11
0.1µFC540
GND GND
LMK04828 decoupling shall be placed as close to the IC package as possible. See LMK04828 datasheet and EVM for example decoupling layout.
PIC51201
PIC51202COC512
PIC51301
PIC51302COC513
PIC51401
PIC51402COC514
PIC51501
PIC51502COC515
PIC51601
PIC51602COC516
PIC51701
PIC51702COC517
PIC51801
PIC51802COC518
PIC51901
PIC51902COC519
PIC52001
PIC52002COC520
PIC52101
PIC52102COC521
PIC52201
PIC52202COC522
PIC52301
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4/14/2015
lmk04828_02.SchDoc
Sheet Title:
Size:
Mod. Date:
File:Sheet: of
B http://www.ti.comContact: http://www.ti.com/support
TI 66AK2L06 JESD Attach to Wideband ADCs and DACsProject Title:Designed for: Public Release
Assembly Variant: [No Variations]
© Texas Instruments 2015Drawn By:Engineer: a0271760
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Version control disabledSVN Rev:TIDEP0034Number: Rev: E1
TID #: TIDEP0034Orderable: EVM_orderable
GreenStatus1
270
R147
LMK-7
LMK-8
LMK-9
LMK_VCC1
DCLKout01
DCLKout0*2
SDCLKout1*4
SDCLKout13
RESET5
SYNC6
NC7
NC8
NC9
Vcc1_VCO10
LDObyp111
LDObyp212
SC
K19
SD
IO20
SD
CLK
out5
22
Vcc
3_SY
SR
EF
21
SD
CLK
out5
*23
DC
LKou
t424
DC
LKou
t4*
25
Vcc
4_C
G2
26
DC
LKou
t627
DC
LKou
t6*
28
SD
CLK
out7
29
SD
CLK
out7
*30
CLKin1*/Fin*/FBCLKin* 35
Vcc6_PLL1 36
CLKin0 37
CLKin0* 38
Vcc7_OSCout 39
OSCout/CLKin2 40
OSCout*/CLKin2* 41
Vcc8_OSCin 42
OSCin 43
OSCin* 44
Vcc9_CP2 45
CPout2 46
DC
LKou
t851
DC
LKou
t8*
52
Vcc1
1_C
G3
53
DC
LKou
t10
54
DC
LKou
t10*
55
SD
CLK
out1
156
SD
CLK
out1
1*57
CLK
in_S
EL0
58
CLK
in_S
EL1
59
SD
CLK
out1
360
SD
CLK
out1
3*61
DC
LKou
t12
62
PA
D65
SDCLKout313
SDCLKout3*14
DCLKout215
DCLKout2*16
Vcc
2_C
G1
17
CS*
18
Sta
tus_
LD1
31
CPo
ut1
32
Vcc5_DIG 33
CLKin1/Fin/FBCLKin 34
Vcc10_PLL2 47
Status_LD2 48
SD
CLK
out9
49
SD
CLK
out9
*50
DC
LKou
t12*
63
Vcc1
2_C
G0
64
U11LMK04828BISQ/NOPBLM
K-63
LMK-
62
LMK-
61
LMK-
60
LMK-
59
LMK-
58
LMK-
52
LMK-
51
LMK_VCC12
LMK_VCC4
GreenStatus2
270R154
LMK_VCC2
LMK-
50
LMK-
49
LMK_VCC10
LMK_VCC9
LD1
47pFC544
619R149
3900pFC543
LMK_CPOUT2
LMK_VCC8
LMK-41
LMK-40
LMK_VCC7
LMK_VCC5
LMK_VCC6
LMK-35
LMK-34
LMK_CLKIN0N_CS 0.1µFC546
LMK_CLKIN0P_CS LMK_CLKIN0P VCC 4
GND 1
OUT3
GND2
U12
IT2100F
19.2 MHz TCXOVSYS_DVDD1V8
1µFC549
10.0R1510.1µFC548 LMK_CLKIN0P_RS
LMK_SPI_CLKLMK_SPI_DATA
LMK_SPI_CS
LMK-43
LMK-44
LMK_SPI_CLKLMK_SPI_DATA
LMK_SPI_CSB
LMK_VCC11
LMK_VCC3
LD2
LMK_CPOUT1
47pFC551
619R153
3900pFC550
LMK_LDOBYP1
LMK_LDOBYP2
LMK_RESET
LMK_SYNC
LMK_LD2 LMK_LD2
2.32kR148
VSYS_DVDD3V3
1.3kR150
0.1µFC545
10µFC547
LMK_LD1LMK_LD1LM
K-57
LMK-
56
LMK-
55
LMK-
54K2L_JESD_SERDES0_REFCLKPK2L_JESD_SERDES0_REFCLKNK2L_JESD_SERDES1_REFCLKPK2L_JESD_SERDES1_REFCLKN
10.0R152 LMK_SPI_DATA_RS
LMK_RESET
LMK_SYNC
ADC_DEVCLKP
ADC_SYSREFN
ADC_SYSREFP
ADC_SYSREFN
ADC_SYSREFP
ADC_DEVCLKN
ADC_DEVCLKP
ADC_DEVCLKN
DAC_DACCLKP
DAC_DACCLKN
DAC_SYSREFP
DAC_SYSREFN
DAC_DACCLKP
DAC_DACCLKN
DAC_SYSREFP
DAC_SYSREFN
K2L_JESD_SERDES0_REFCLKPK2L_JESD_SERDES0_REFCLKNK2L_JESD_SERDES1_REFCLKPK2L_JESD_SERDES1_REFCLKN
K2L_SYSCLKPK2L_SYSCLKN
K2L_SYSCLKPK2L_SYSCLKN
K2L_DFESYSREFPK2L_DFESYSREFNK2L_DFESYSREFN
K2L_DFESYSREFP
DAC_DACCLKP
DAC_DACCLKN
DAC_SYSREFP
DAC_SYSREFN
240R157
240R158
240R155
240R156
TI LMK04828 Product Page
LMK04828 SPI port mastered by System Controller (microcontroller) not shown here.
Optional external charge-pump filter element. Shall be placed as close as possible to LMK04828.
Please see LMK04828 datasheet, application notes and EVM design guide for specific recommendations.
Optional external charge-pump filter element. Shall be placed as close as possible to LMK04828.
Please see LMK04828 datasheet, application notes and EVM design guide for specific recommendations.
LMK04828 RESET and SYNC mastered by System Controller (microcontroller) not shown here.
LMK04828 LD1 and LD2 monitored by System Controller (microcontroller) not shown here.
LMK04828 LD1 and LD2 monitored by System Controller (microcontroller) not shown here.
Special care should be taken to GND isolate CLKIN0 signal.
LMK04828 DCLKOUT0 used as the device clock for the ADC
LMK04828 SDCLKOUT0 used as the SYSREF for the ADC
For schematic and layout recommendations and requirements see the LMK04828 product page linked below.
LMK04828 DCLKOUT2 used as the device clock for the DAC
LMK04828 SDCLKOUT3 used as the SYSREF for the DAC
All unused pins shall be routed with short stubs to aid in solderability and mechanical robustness. Indicated by the LMK-xx unused pin nets names.
LMK04828 DCLKOUT4 used as the SYSCLK for the K2L
LMK04828 SDCLKOUT5 used as the SYSREF for the K2L
LMK04828 DCLKOUT6 used as the JESD0 SERDES clock for the K2L
LMK04828 SDCLKOUT7 used as the JESD1 SERDES clock for the K2L
DAC DACCLK and SYSREF are LVPECL inputs which require LVPECL source biasing and AC-coupling as described in the DAC38J84 datasheet section 7.3.25
PIC54301
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COU12
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Testing and other quality control techniques for TI components are used to the extent TIdeems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is notnecessarily performed.TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products andapplications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provideadequate design and operating safeguards.Reproduction of significant portions of TI information in TI data books, data sheets or reference designs is permissible only if reproduction iswithout alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable forsuch altered documentation. Information of third parties may be subject to additional restrictions.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirementsconcerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or supportthat may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards thatanticipate dangerous failures, monitor failures and their consequences, lessen the likelihood of dangerous failures and take appropriateremedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components inBuyer’s safety-critical applications.In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is tohelp enable customers to design and create their own end-product solutions that meet applicable functional safety standards andrequirements. Nonetheless, such components are subject to these terms.No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the partieshave executed an agreement specifically governing such use.Only those TI components that TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use inmilitary/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components thathave not been so designated is solely at Buyer's risk, and Buyer is solely responsible for compliance with all legal and regulatoryrequirements in connection with such use.TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. 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Texas Instruments Incorporated ("TI") reference designs are solely intended to assist designers (“Buyers”) who are developing systems thatincorporate TI semiconductor products (also referred to herein as “components”). Buyer understands and agrees that Buyer remainsresponsible for using its independent analysis, evaluation and judgment in designing Buyer’s systems and products.TI reference designs have been created using standard laboratory conditions and engineering practices. TI has not conducted anytesting other than that specifically described in the published documentation for a particular reference design. TI may makecorrections, enhancements, improvements and other changes to its reference designs.Buyers are authorized to use TI reference designs with the TI component(s) identified in each particular reference design and to modify thereference design in the development of their end products. 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TI MAKES NO WARRANTIES OR REPRESENTATIONS WITH REGARD TO THEREFERENCE DESIGNS OR USE OF THE REFERENCE DESIGNS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING ACCURACY ORCOMPLETENESS. TI DISCLAIMS ANY WARRANTY OF TITLE AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESSFOR A PARTICULAR PURPOSE, QUIET ENJOYMENT, QUIET POSSESSION, AND NON-INFRINGEMENT OF ANY THIRD PARTYINTELLECTUAL PROPERTY RIGHTS WITH REGARD TO TI REFERENCE DESIGNS OR USE THEREOF. TI SHALL NOT BE LIABLEFOR AND SHALL NOT DEFEND OR INDEMNIFY BUYERS AGAINST ANY THIRD PARTY INFRINGEMENT CLAIM THAT RELATES TOOR IS BASED ON A COMBINATION OF COMPONENTS PROVIDED IN A TI REFERENCE DESIGN. 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Testing and other quality control techniques for TI components are used to the extent TIdeems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is notnecessarily performed.TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products andapplications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provideadequate design and operating safeguards.Reproduction of significant portions of TI information in TI data books, data sheets or reference designs is permissible only if reproduction iswithout alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable forsuch altered documentation. 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With such components, TI’s goal is tohelp enable customers to design and create their own end-product solutions that meet applicable functional safety standards andrequirements. Nonetheless, such components are subject to these terms.No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the partieshave executed an agreement specifically governing such use.Only those TI components that TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use inmilitary/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components thathave not been so designated is solely at Buyer's risk, and Buyer is solely responsible for compliance with all legal and regulatoryrequirements in connection with such use.TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use ofnon-designated products, TI will not be responsible for any failure to meet ISO/TS16949.IMPORTANT NOTICE
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