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J.J. Shann
Chapter 6
(Synchronous) Sequential Circuits
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J.J. Shann 6-2
Contents
6-1 Sequential Circuit Definitions6-2 Latches6-3 Flip-Flops6-6 Other Flip-Flop Types6-4 (Sync.) Sequential Circuit Analysis6-5 (Sync.) Sequential Circuit Design6-7 HDL Representation for Sequential Circuits—
VHDL (×)6-8 HDL Representation for Sequential Circuits—
Verilog (×)6-9 Chapter Summary
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6-1 Sequential Circuit Definitions
Combinational circuit: no memory elements(inputs) ⇒ (outputs)
Sequential circuit:
— storage elements: devices capable of storing binary information (state)
— (inputs, present state) ⇒ (outputs, next state)
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Logic structures for storing information:— E.g.s:
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Types of Sequential Circuits
Classification:— depends on the timing of their signals.
Two main types:1. Synchronous seq ckt:
– Its behavior can be defined from the knowledge of its signals at discrete instants of time.
– Storage elements: e.g., flip-flops
2. Asynchronous seq ckt: (補充資料)– Its behavior depends upon the input signals at any instant of
time and the order in which the inputs change.– Storage elements: e.g., latches, feedback paths– Disadv.: may be unstable & difficult to design
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Synchronous Sequential Circuits
Clocked seq ckts: most commonly used sync seq ckts— is syn seq ckts that use clock pulses in the inputs of storage elements— has a master-clock generator to generate a periodic train of clock
pulsesThe clock pulses are distributed throughout the system.Storage elements are affected only w/ the arrival of each pulse.
— Adv.: seldom manifest instability problems— Storage elements: flip-flops
flip-flop: a binary cell capable of storing one bit of informationThe state of a flip-flop can change only during a clock pulse transition. ⇒ The transition from one state to the next occurs only at
predetermined time intervals dictated by the clock pulses.
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Block diagram of a clocked sequential ckt:
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6-2 Latches
Latches:— are asynchronous seq ckts— are the basic ckts from which all flip-flops are
constructed
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A. SR and SR Latches
SR latchSR latchSR latch w/ control input
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SR latch: w/ NOR gates
— Useful states: Set state: Q = 1, Q = 0Reset state: Q = 0, Q = 1
— Undefined states: Q = Q
SR Latch
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Logic simulation of SR latch behavior
S R Q + 0 0 N o ch ange (Q + = Q )0 1 R eset (Q + = 0) 1 0 S et (Q + = 1 ) 1 1 In d eterm in ate
Q +: n ext sta te o f Q
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S R Latch
S R latch: w/ NAND gates
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S R Q +
1 1 N o ch an ge (Q + = Q )1 0 R eset (Q + = 0)0 1 Set (Q + = 1)0 0 In determ in ate
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SR Latch w/ Control Input
SR latch w/ control input:
— The indeterminate condition makes this ckt difficult to manage & it is seldom used in practice.
— It is an important ckt (other latches & flip-flops are constructed from it)
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B. D Latch
D latchD latch w/ transmission gates
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D Latch
D latch (w/ control input):
Disadv. of a latch w/ control input:— The state of latch may keep changing for as long as the
control input stays in the active level.
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D latch w/ transmission gates:
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6-3 Flip-Flops
Flip-flop vs. Latch:— Latch w/ control input:
can change state in response to the inputs anytime the control input is in the active level.⇒ The latch is controlled by the “level” of its control input.
— Flip-flop:responses only to a “transition” of a triggering input called the “clock.”Positive-edge trigger: 0 → 1Negative-edge trigger: 1 → 0
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Clock response in latch & flip-flop:
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Latch → Flip-flop:1. Master-slave flip-flop: pulse-triggered f-f
Employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing.
2. Edge-triggered flip-flop:Produce a flip-flop that triggers only during a signal transition, and is disabled during the rest of the clock pulse duration.
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A. Master-Slave Flip-Flops
SR master-slave flip-flop:
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Logic simulation of an SR master-slave flip-flop:
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Master-slave D f-f
Negativeedge-triggered
D flip-flop
Positiveedge-triggered
D flip-flop
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B. Edge-Triggered Flip-Flop
Master-slave f-f → Edge-triggered f-f
Negativeedge-triggered
D flip-flop
Positiveedge-triggered
D flip-flop
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Timing
Setup time:— the minimum time for which the D input must be
maintained at a constant value prior to the occurrence of the clock transition
Hold time:— the minimum time for which the D input must not change
after the application of the positive transition of the clock
Propagation delay time:— the time interval b/t the trigger edge and the stabilization
of the output to a new state
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C. Flip-Flop Timing
Clock pulse width, twSetup time, tsHold time, thPropagation delay times, tPHL, tPLH, tpd
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D. Standard Graphics Symbols
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E. Direct Inputs
Direct inputs: asynchronous inputs— are used to force the flip-flop to a particular state
independent of the clock.When power is turned on in a digital system, the state of the flip-flops is unknown.The direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation.
— Types of direct inputs:Preset: direct set, sets the f-f to 1Clear: direct reset, sets the f-f to 0
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E.g.: D f-f w/ direct set and reset
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6-6 Other Flip-Flop Types
JK flip-flopT flip-flop
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JK flip-flop
J-K Flip-Flop
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T Flip-Flop
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Flip-Flop Logic, Characteristic Tables & Equations, and Excitation Tables
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6-4 (Sync) Sequential Circuit Analysis
Synchronous seq ckt:
— includes f-fs w/ the clock inputs driven directly or indirectly by a clock signal and the direct sets and resets are unused during the normal functioning of the ckt
— The behavior of a seq ckt is determined from the inputs, outputs, and present state of the ckt.
Analysis of a seq ckt:— obtain a suitable description that demonstrates the time
sequence of inputs, outputs, and states
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E.g. 1:
A. Analysis w/ D Flip-Flops
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1. Flip-flop input equations & Output equations:
2. Next state equation:
BXAXDA +=XADB =
XB)(AY +=
BXAXDtA A +==+ )1(X)1( ADtB B ==+
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3. State table:Next state equations:
Output equations: XBXAY +=
BXAXtA +=+ )1(X)1( AtB =+
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(One-dimensional)State table
Two-dimensionalstate table
⇓
1
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4. State diagram: X/Y
1
input/output
00 01
1110
0/0 1/0
0/1
1/00/1
1/0
0/1
1/0
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Example 2
E.g. 2:
1. Flip-Flop input equations & Output equations:DA = A⊕X⊕YZ = A
2. Next-state equation:A+ = DA = A⊕X⊕Y
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3. State table:
4. State diagram:
YXAA ⊕⊕=+
AZ =
0/0 1/1
01, 10
00, 11 00, 11
01, 10
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Example:
補充資料:Analysis w/ JK Flip-Flops
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1. Flip-flop input equations & Output equations:
JA = BKA = B x′JB = x′KB = A x′ + A′ x
= A ⊕ x2. Next state equations:
A+ = JA A′ + KA′ A = A′ B + A B′ + A xB+ = JB B′ + KB′B = B′ x′ + A B x + A′ B x′
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3. State table:A+ = A′ B + A B′ + A xB+ = B′ x′ + A B x + A′ B x′
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4. State diagram
00
01 10
11
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B. Mealy Model vs. Moore Model
Mealy model:— is a model of seq ckts in which the outputs depend on
both the inputs and the present states.
— E.g. 1:
State Register ClockState
Feedback
Combinational Logic for
Outputs and Next State
X Inputs
i Z Outputsk
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— E.g. 1:
XB)(AY +=
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Moore model:— is a model of seq ckts in which the outputs depend only
on the present states.
— E.g. 2:
Clock
state feedback
Combinational Logic for
Next State (Flip-flop Inputs)
State Register
Comb. Logic for Outputs
Z Outputs
k
X Inputs
i
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— E.g. 2:
Z = A
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Comparison:— Moore model:
The outputs of the ckt are synchronized w/ the clock.(⇐ the outputs depend on only flip-flop outputs that are
synchronized w/ the clock)
— Mealy model:The outputs may change if the inputs change during the clock cycle.
Clock
state feedback
Combinational Logic for
Next State (Flip-flop Inputs)
State Register
Comb. Logic for Outputs
Z Outputs
k
X Inputs
i
State Register ClockState
Feedback
Combinational Logic for
Outputs and Next State
X Inputs
i Z Outputsk
Moore-model Mealy-model
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C. Sequential Circuit Timing
Analysis of a seq ckt:— analyze the function of the ckt— analyze the performance of the ckt
max input-to-output delaythe max clock frequency, fmax , at which the ckt can operate
clock frequency f = 1/tp , tp: the clock periodfmax = 1/tp-min , tp-min: the min allowable clock period
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Sequential Circuit Timing Parameters
Sequential ckt timing parameters:i. f-f propagation delay: tpd,FFii. comb logic delay through the chain of gates along the
path: tpd,COMBiii. f-f setup time: ts(iv. slack time, tslack : the extra time allowed in the clock
period beyond that required by the path)
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For edge-triggered flip-flops:— determine the longest delay from the triggering edge of
the clock to the next triggering edge of the clock.
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For pulse-triggered flip-flops:
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Sequential Circuit Timing Paths
Sequential ckt timing paths:
ti: the latest time that the input changes after the positive clock edge
to: the latest time that the output is permitted to change prior to the next clock edge
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Propagation delay for a path of type PFF,FF:
)tt(ttt sCOMBpd,FFpd,slackp +++=
minp,sCOMBpd,FFpd,p max t)tt (tt =++≥
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Example 6-1: Clock Period and Frequency Calculations
Example 6-1:Suppose that all f-fs used are the same and have tpd = 0.2 ns
and ts = 0.1 ns. Then the longest path beginning and ending w/ a f-f will be the path w/ the largest tpd,COMB. Further, suppose that the largest tpd,COMB is 1.3 ns and that tp has been set to 1.5 ns.
ns 6.11.03.12.0ns 5.1 slackslack +=+++= tt
)0tion w/ (contradic ns 1.0 slackslack ≤−=⇒ tt
ns 6.1minp,p =≥⇒ ttMHZ 625ns 6.1/1max ==⇒ f
⇒ tp is too small
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Discussion
If tp is too large to meet the ckt specifications:— employ faster logic cells or— change the ckt design to reduce the problematic path
delays through the ckt
Hold time: th— does not appear in the clock period
equation.— relates to another timing constraint
equation dealing w/ one or both of 2 specific situations:
output changes arrive at the inputs of one or more f-fs too soonthe clock signals reaching one or more f-f are somehow delayed (clock skew)
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D. Simulation
Sequential ckt simulation:— The input patterns must be applied in a sequence.— There must be some means to place the ckt in a known state.— Observe the state to verify correctness.— Deal with the timing of application of inputs and observation of
outputs relative to the active clock edge.
Function simulation— Objective: determination or verification of the function of the ckt
⇒ Assumption: Ckt components has no delay or a very small delay.
Timing simulation— Objective: verification of the proper op of the ckt in terms of timing
⇒ Ckt components has realistic delays.
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Simulation timing:
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6-5 (Sync) Sequential Circuit Design
Design procedure:1. Specification: Write a specification for the ckt.2. Formulation: Obtain either a state diagram or state table
from the statement of the problem. (correctness)* State reduction: Reduce the # of states if necessary.3. State assignment: Assign binary codes to the states and
obtain the binary-coded state table. 4. Flip-flop input equation determination: Select the flip-
flop type or types. Derive the flip-flop input equations from the next-state entries in the encoded state table.
5. Output equation determination: Derive output equations from the output entries in the state table.
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6. Optimization: Optimize the flip-flop input equations and output equations.
7. Technology mapping: Draw a logic diagram of the cktusing flip-flops, ANDs, ORs, and inverters. Transform the logic diagram to a new diagram using the available flip-flop and gate technology.
8. Verification: Verify the correctness of the final design.
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Initial State
Initial state:— Async and sync reset for D flip-flops
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Example 6-2
E.g.: Sequence recognizer of “1101”— Problem description:
Recognize the occurrence of the sequence of bits 1101 on input X by making output Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1, regardless of where it occurs in a sequence. Otherwise, Z equals 0.The circuit has direct resets on its flip-flops to initialize the state of the circuit to all zeros.
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— State diagram: (cont’d)
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— State table:
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Example
State table:Present Input Next Output
state x state yS0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S0 0S2 1 S3 0S3 0 S0 1S3 1 S3 1
E.g.: Sequence detector of three or more consecutive 1’s (Moore-type)
Design a ckt that detects three or more consecutive 1’s in a string of bits coming through an input line.
State diagram
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Example 6-3
E.g.: Finding a state diagram for a BCD-to-excess-3 decoder
— Formulation: Sequence tables for code converter
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— State diagram: (cont’d)
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Flip-Flop Excitation Tables
Select the flip-flop type or types⇒ Flip-flop excitation tables: (p.6-51)
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Designing Using D Flip-Flops
Example 6-2: Sequence detectorState diagram:
State table:
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State assignment:A = 00, B = 01,C = 11, D = 10
Binary coded state table:
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F-F input eqs & output eq:
)7,6,3(),,()1( mXBADtA A Σ==+
)7,5,3,1(),,()1( mCBADtB B Σ==+
)5(),,( mXBAZ Σ=
Excitation table of D f-f
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Logic diagram:
BXABDA +=
XDB =
XBAZ =
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Designing w/ Unused States
Example:— State table:
3 unused states000110111
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— Maps for optimizing flip-flop input equations:
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— Logic diagram:
C BBXAXDA ++=
XB AX C ADB +=
XDC =
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Verification
Verification of sync seq ckts:— show that the ckt produces the original state diagram or
state tableused statesunused states
— Manual verification: for small cktsanalyze the ckt
— Verification w/ simulationrequires a sequence of input combinations and applied clocks
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Example 6-4
E.g.: Verifying the sequence recognizer— Test generation for simulation
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— Simulation