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Title VLSI回路の面積と計算時間の複雑さに関する研究
Author(s) 和田, 幸一
Citation
Issue Date
Text Version ETD
URL http://hdl.handle.net/11094/659
DOI
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Note
Osaka University Knowledge Archive : OUKAOsaka University Knowledge Archive : OUKA
https://ir.library.osaka-u.ac.jp/repo/ouka/all/
Osaka University
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VLSI回 路 の面積 と計算 時 聞 の
複 雑 さに関 す る研究
1::
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K.Wada, K.Hagihara and N.Tokura : "Area-Time Bounds for
VLSI Circuits," Proceedings 19th Annual Allerton Conference
on Communication, Control, and Computing,p.234
(September-October 1981).
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K.Wada, K.Hagihara and N.Tokura : "Area and Time
Complexities of VLSI Computations," Proceedings the 7th IBM
Symposium on Mathematical Foundations of Computer Science,
Mathematical Theory of Computations, IBM Japan,pp. 1-77 (June 1982).
K.Hagihara, K.Wada and N.Tokura : "Effects of Practical
Assumption Area Complexity in VLSI Computation,"_ to appear
in Lecture Notes in Computer Science, Springer-Verlag.
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