Lecture 19
OUTLINE
The MOSFET: • Structure and operation• Qualitative theory of operation• Field-effect mobility• Body bias effect
Reading: Pierret 17.1, 18.3.4; Hu 6.1-6.5
In 1935, a British patent was issued to Oskar Heil. A working MOSFET was not demonstrated until 1955.
Invention of the Field-Effect Transistor
Lecture 19, Slide 2EE130/230A Fall 2013
O. Heil, British Patent 439,457 (1935)
Metal Oxide SemiconductorField Effect Transistor (MOSFET)
• An electric field is applied normal to the surface of the semiconductor (by applying a voltage to an overlying electrode), to modulate the conductance of the semiconductor.
Drift current flowing between 2 doped regions (“source” & “drain”) is modulated by varying the voltage on the “gate” electrode.
Lecture 19, Slide 3EE130/230A Fall 2013 R. F. Pierret, Semiconductor Device Fundamentals, Fig. 17.1
Modern MOSFETs
4
• Current flowing between the SOURCE and DRAIN is controlled by the voltage on the GATE electrode
Substrate
Gate
Source Drain
Metal-Oxide-Semiconductor Field-Effect Transistor:
GATE LENGTH, Lg
OXIDE THICKNESS, xo
Desired characteristics:• High ON current• Low OFF current
• “N-channel” & “P-channel” MOSFETs operate in a complementary manner“CMOS” = Complementary MOS |GATE VOLTAGE|
CU
RR
ENT
VT
Intel’s 32nm CMOSFETs
Lecture 19, Slide 4EE130/230A Fall 2013
P. Packan et al., IEDM Technical Digest, pp. 659-662, 2009
N-channel vs. P-channel
• For current to flow, VGS > VT
to form n-type channel at surface
• Enhancement mode: VT > 0
• Depletion mode: VT < 0Transistor is ON when VG=0V
p-type Si
N+ poly-Si
n-type Si
P+ poly-SiNMOS PMOS
N+ N+ P+ P+
• For current to flow, VGS < VT
to form p-type channel at surface
• Enhancement mode: VT < 0
• Depletion mode: VT > 0Transistor is ON when VG=0V
Lecture 19, Slide 5EE130/230A Fall 2013
Enhancement Mode vs. Depletion Mode
Enhancement Mode Depletion Mode
Conduction between source and drain regions is enhanced by applying a gate voltage
A gate voltage must be appliedto deplete the channel region in order to turn off the transistor
Lecture 19, Slide 6EE130/230A Fall 2013
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 18.18
CMOS Devices and CircuitsCIRCUIT SYMBOLS
N-channelMOSFET
P-channelMOSFET
GND
VDD
S
S
D
D
CMOS INVERTER CIRCUIT
VIN VOUT
VOUT
VIN0 VDD
VDD
INVERTERLOGIC SYMBOL
• When VG = VDD , the NMOSFET is on and the PMOSFET is off.
• When VG = 0, the PMOSFET is on and the NMOSFET is off.
Lecture 19, Slide 7EE130/230A Fall 2013
“Pull-Down” and “Pull-Up” Devices• In CMOS logic gates, NMOSFETs are used to connect
the output to GND, whereas PMOSFETs are used to connect the output to VDD.– An NMOSFET functions as a pull-down device when it is
turned on (gate voltage = VDD)– A PMOSFET functions as a pull-up device when it is turned
on (gate voltage = GND)
F(A1, A2, …, AN)
PMOSFETs only
NMOSFETs only
……
Pull-upnetwork
Pull-downnetwork
VDD
A1
A2
AN
A1
A2
AN
input signals
Lecture 19, Slide 8EE130/230A Fall 2013
CMOS NAND GateA B F0 0 10 1 11 0 11 1 0
A
F
B
A B
VDD
Lecture 19, Slide 9EE130/230A Fall 2013
CMOS NOR Gate
A
F
B
A
B
VDD A B F0 0 10 1 01 0 01 1 0
Lecture 19, Slide 10EE130/230A Fall 2013
CMOS Pass Gate
A
X Y
A
Y = X if A
Lecture 19, Slide 11EE130/230A Fall 2013
Qualitative Theory of the NMOSFETdepletion layer
The potential barrier to electron flow from the source into the channel region is lowered by applying VGS> VT
Electrons flow from the source to the drain by drift, when VDS>0. (IDS > 0)
The channel potential varies from VS at the source end to VD at the drain end.
VGS < VT :
VGS > VT :
VDS 0
VDS > 0
Inversion-layer “channel” is formed
EE130/230A Fall 2013 Lecture 19, Slide 12 R. F. Pierret, Semiconductor Device Fundamentals, Fig. 17.2
MOSFET Linear Region of OperationFor small values of VDS (i.e. for VDS << VGVT),
where eff is the effective carrier mobility
Hence the NMOSFET can be modeled as a resistor:
L
VWQWQvWQI DS
effinveffinvinvDS
)( TGoxeeffDS
DSDS VVCW
L
I
VR
EE130/230A Fall 2013 Lecture 19, Slide 13
Field-Effect Mobility, eff
Scattering mechanisms:
• Coulombic scattering
• phonon scattering
• surface roughness scattering
EE130/230A Fall 2013 Lecture 19, Slide 14 C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 6-9
• When VD is increased to be equal to VG-VT, the inversion-layer charge density at the drain end of the channel equals 0, i.e. the channel becomes “pinched off”
• As VD is increased above VG-VT, the length L of the “pinch-off” region increases. The voltage applied across the inversion layer is always VDsat=VGS-VT, and so the current saturates.
VDS = VGS-VT
VDS > VGS-VT
VDS
MOSFET Saturation Region of Operation
DsatDS VVDSDsat II
ID
EE130/230A Fall 2013 Lecture 19, Slide 15 R. F. Pierret, Semiconductor Device Fundamentals, Figs. 17.2, 17-3
Ideal NMOSFET I-V Characteristics
EE130/230A Fall 2013 Lecture 19, Slide 16 R. F. Pierret, Semiconductor Device Fundamentals, Fig. 17.4
Channel Length Modulation• As VDS is increased above VDsat, the width L of the depletion
region between the pinch-off point and the drain increases, i.e. the inversion layer length decreases.
L
L
LLLIDsat 1
11
DsatDS VVL
DsatDS VVL
L
DsatDSDsatDsat VVII 10
IDS
VDS
If L is significant compared to L, then IDS will increase slightly with increasing VDS>VDsat, due to “channel-length modulation”
EE130/230A Fall 2013 Lecture 19, Slide 17 R. F. Pierret, Semiconductor Device Fundamentals, Figs. 17.2, 17-3
Body Bias• When a MOS device is biased into inversion, a pn junction
exists between the surface and the bulk.• If the inversion layer contacts a heavily doped region of the
same type, it is possible to apply a bias to this pn junction.
N+ poly-Si
p-type Si
-- - - --
+ + + + + +
N+
+ +
-- -SiO2
• VG is biased so that surface is inverted• n-type inversion layer is contacted by N+
region• If a bias VC is applied to the channel, a
reverse bias (VB-VC) is applied between the channel and body
EE130/230A Fall 2013 Lecture 19, Slide 18
Effect of VCB on S, W and VT
• Application of a reverse body bias non-equilibrium 2 Fermi levels (one in n-type region, one in p-type region)
are separated by qVBC S is increased by VCB
• Reverse body bias widens W, increases Qdep and hence VT
ox
CBFSiAFCBFBT C
yVqNyVVyV
))(2(22)()(
EE130/230A Fall 2013 Lecture 19, Slide 19