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Handset applications using Low Voltage, Low Ron Switches
Agenda
Product PortfolioHandset applications
Important Specs for Handset SwitchesIntroduction to CMOS switchesDesign SpecificationsDesign TradeoffsAnalog Devices switches
Package developmentsUSB Switching - optionalLevel Translators - optional
Switches for Consumer Products1.65V – 5.5V Supply range
1.65V – 3.6V1.65V – 3.6V
3V, 5V3V, 5V
Supp
ly R
ange
Supp
ly R
ange
Switch ConfigurationSwitch Configuration
ADG836
ADG779
ADG736
Ron < 1
Ron < 4
ADG801/2
ADG841/2
ADG819
ADG849
ADG839
ADG884ADG821/2/3
ADG721/2/3ADG701/2
1 x SPST 1 x SPDT 2 x SPST 2 x SPDT
ADG859
4 x SPDT
ADG788
ADG888ADG787ADG741/2
Handset Applications
Audio SwitchingSpeaker/ringerInternal/external speaker – handsfree
Data SwitchingUSBUARTRS232
Handset Audio Switching
Requirements
Configurationeg 2 x SPDT
Board areaTiny package
Minimum signal lossVery low absolute Ron
(~0.5ohms) Minimum distortion
Ron Flatness Loudness
High continuous currents
8 ohmFor ring and MP3
BasebandChip
32 ohmFor phone
Melody/voice & hands-free
Handset Data Switching
Requirements
Configurationeg 2 x SPDT
Board areaTiny package
Bandwidth Eg USB 1.1 – 12Mbps
Minimum signal lossLow absolute Ron (~2.5ohms)
Differential system-Channel matchingDelta Ron
Minimum distortionRon Flatness
Socket Connection
Dig
ital B
B
USBtransceiver
RS232TransceiverUART
USB
Important specifications in handset switches
PackageThe smaller the better!
RonAbsolute value needs to be low because the switch is in series with
the SpeakerLow Ron also means lower Ron Flatness less audio distortion
Current Handling CapabilitiesP = I2R More current through the switch means more power,
thus louder audio
Power consumptionMany products are battery-operated, therefore power consumption
is critical
Basic MOSFET structure of CMOS Analog switch The CMOS switch is a parallel combination of PMOS and NMOS,
Field effect transistors which operate in the non-saturated region. The input buffer level shifts the digital input and applies
signal to driversDrivers set the timing so that PMOS and NMOS are turned
“on” or “off”. NMOS on when gate is HI, PMOS on when gate is LO.Basic building block for multi-channel switch
Digitalinput
PMOS
NMOS
Source I/O Drain I/O
inverter
Figure 1. MOS structure of a single CMOS switch channel
Input buffer
driver
driver
Advantages of parallel structure Rail-to-Rail outputs Bi-directional operation Relatively constant On-resistance over input signal range For both NMOS and PMOS to have same Ron, PMOS is more than
twice the area of NMOS
Vsource (V)
Ron
(Ω)
Vsource (V)
Ron
(Ω)
Ron of NMOS only
Ron of CMOS
In
par
alle
l with
Vsource (V)
Ron
(Ω)
source source
Ron of PMOS only
draindrain source drain
Digital input
Rpmos
Rnmos
Absolute On-Resistance
Ron varies with input signal Ron varies with supply Ron varies with temperature
Ron flatness/Audio Distortion
Ron Flatness = Max_Ron – Min_Ron Translates directly into distortion through the switch Reduced by using back-gate switching
0
0.2
0.4
0.6
0.8
1
0 1 2 3 4 5Vd, Vs - V
ON
RES
ISTA
NC
E
VDD = 5V
Ron max
Ron min
Delta Ron - On resistance Channel Matching
On resistance matching (ΔRon): Difference in Ron between channels
Achieved by good layout techniquesDifferential switching; ensures equal propagation delay
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
Voltage
Ron
S1A S1B S2A S2B
Continuous current
Need large tracks and careful routing to handle currentTrade-off with package size
Reliability specs (current vs track width) and maximum junction temperature of silicon determine max. continuous currentExcess currents lead to electromigration over timeReflow of metal causing increase in Ron and eventually opens
ADG849400mA continuous current
Charge Injection
A measure of the glitch impulse transferred from the digital input to the analog output during switching.
Caused by stray capacitance associated with the NMOS and PMOS transistors
For both NMOS and PMOS to have same Ron, PMOS is approx three times the area of NMOS hence cap of PMOS= 3x cap of NMOS
Balanced NMOS and PMOS => low QinjAchieved by adding compensations caps
VIN (NORMALLYCLOSED SWITCH)
VOUT
VIN (NORMALLYOPEN SWI TCH)
OFF
VOUT
ON
QINJ = CL VOUT
0477
6-0-
025
IN
VOUTD
SA
VDD VSS
VDD VSS
GND
CL1nF
NCSB
VIN
VS
0.1F
Capacitance
Mainly dependent on switch areaTry to minimise during layoutUltra-Low Ron Very large Switch Area Lots of
parasitic capacitance Low bandwidth
CDCS Cchannel
When switch is on
CS(on) = CD(on) = CS+ CD + Cchannel
When switch is off
CS(off) = CSCD(off) = CD
input
CS CD
input outputoutput
Leakage Currents
Leakage increase as temp increase
Higher voltage => higher leakage
Source : ADG836 data sheet
Design tradeoffs
Ron α 1/(size of switch)Continuous current needs to be high
Both of these specs mean you need a large switch areaThis means:
Larger packageHigher parasitic capacitance – lower bandwidthHigher leakageHigher charge injections
Specification tradeoffs
PackageUltra-Low Ron Very large Switch Area (package vs Ron tradeoff)Large tracks for carrying the current needs area
Bandwidth Ultra-Low Ron Very large Switch Area Lots of parasitic
capacitance Low bandwidth
Charge injectionLarge capacitance large Charge InjectionLarge Switch/track Area no room for Qinj compensation
capacitors
ADG859: 1.3 SPDT in the smallest standard package KEY BENEFITSKEY BENEFITS Package: Tiny 6-pin device in 1.65 x
1.66 x 0.57mm package Ron: 3 at 5V operation Distortion: 0.5
-40°C – 85°CSOT6630pC70MHz0.5 3 1.8 V to 5.5 V
TempPackageQinjBandwidthRON FlatRONVRANGE
SpecificationsSpecifications
Alternative to WLCSP
ADG888 – 0.45 Dual DPDT Switch in WLCSP/LFCSP/TSSOP
KEY BENEFITSKEY BENEFITS Ultra-low RON 0.45 typ WLCSP and TSSOP packages 3V, 5V operation 400mA Continuous Current 600mA Peak current
-40°C – 85°CWLCSP; LFCSP; TSSOP
50pC3nA0.1 0.45 1.8 V to 5.5 V
TempPackageQinjLeakageRON FlatRONVRANGE
SpecificationsSpecifications
S2A
S2B
S1A
S1B
ADG888
D1
D2
SWITCHES SHOWN FOR A LOGIC "1" INPUT
IN1
S4A
S4B
S3A
S3B
IN2
D3
D4
Smallest Quad Audio Sw in the world
The World Leader in High Performance Signal Processing Solutions
Packaging AdvancesLFCSP, WLCSP, advances in std plastic packages
Packaging Innovation compliments Product InnovationStandard OfferingsTQFP SSOPTSOT SOICTSSOP SOIC-NSOT SOIC-WSC70 QSOPPDIP LCC
Three-pronged
approach
Standard
package
development
Tiny Analog Switches Lowest Ron parts
Minimum distortionExcellent for audio
Handset, PDA, Notebook
Config Generic Ron () Supply PackageSPDT ADG819 0.5 1.8-5.5V WLCSPSPDT ADG749 2.5 1.8-5.5V SC70SPDT ADG779 2.5 1.8-5.5V SC702x SPDT ADG787 2 1.8-5.5V WLCSPSPST ADG741/2 2 1.8-5.5V SC702x SPDT ADG736 4 1.8-5.5V MSOP, CSP2x SPDT ADG884 0.5 1.8-5.5V CSP,
WLCSPSPDT ADG849 0.95 1.8-5.5V SC70
Packaging Innovation compliments Product Innovation
New standard package SOT66Perfect for handset, PDA
35% less area than SC70Almost half the height! ADG3231
ADG3241
ADG859*
Smallest 1-bit translatorsSmallest audio Sw
Alternative to WLCSP
Avoid manuf issues!
*SPDT Audio SwRelease 2H04
SOT-666 Package Outline
Wafer-Level PortfolioSmallest possible PCB footprint
ADG819SPDT 0.5
Audio
ADG8842x SPDT <1
Audio
ADG7872x SPDT 4
USB1.1
ADG8884x SPDT 0.5
Audio
ADG33044-channel1.2V-5.5VTranslator
ADG33088-channel1.2V-5.5VTranslator
ADG8088x SPDT 0.5
Audio
Green: ReleasedRed: Planned
Shortlist of Recommended Handset PartsPart Number Description Samples Release 1K/Price
ADG819ADG819 0.5 CMOS 1.8 V to 5.5 V 2:1 Mux/SPDT $0.93
ADG849ADG849 1.8 V to 5.5 V, <1 SPDT in SC70 Package $0.94
ADG884ADG884 0.5 CMOS Dual 2:1 Mux/SPDT in WLCSP Oct04 TBA
ADG836ADG836 <0.8 CMOS 1.6V to 3.6V Dual SPDT/2:1 Mux $0.98
ADG779ADG779 CMOS 1.8 V to 5.5 V, 2.5 SPDT in Tiny SC70 $0.64
ADG787ADG787 2 CMOS 1.8 V to 5.5 V 2:1 Mux/SPDT USB1.1 Switch Nov04 $0.92
ADG736ADG736 Low Voltage 2.5 Dual SPDT Switch $0.90
ADG3308ADG3308 1.2V to 5.5V, 8-bit Bi-dir Logic Level Translator Nov’04 $1.60
ADG3304ADG3304 1.2V to 5.5V, 4-bit Bi-dir Logic Level Translator Nov’04 $0.96
ADG3241ADG3241 2.5 V/3.3 V, 1-Bit, 2-Port Level Translator Bus Switch $0.43
ADG3242/3ADG3242/3 2.5 V/3.3 V, 2 Bit, Level Translators $0.56
ADG3231ADG3231 Low Voltage, Single-Channel Level Translator $0.43
The World Leader in High Performance Signal Processing Solutions
USB1.1 and USB2.0 SwitchingADG7xx Series, ADG8xx Series and ADG324x series
USB 1.1 Switch requirements USB 1.1 Signal levels
3.6V max signal level, 0V min spec
ADI switches are ideal for USB1.1 All ADG7xx, most ADG8xx comply
5V supplyRail to rail operationLow power (<1uA Idd)Low Ron:
ADG7xx ~3Ω ADG8xx <1Ω Excellent flatness characteristic
ADI AdvantageLow Ron minimizes signal lossFlat Ron reduces signal distortion
USB 1.1 Switch requirements (continued)
Bandwidth > 12MHz requiredUSB1.1 is 12Mbps signal
Again ADG7xx idealSuitable configurationsSuitable bandwidth (majority
>200MHz)
Source: ADG736Bandwidth 200MHz
ADI guarantee compliance to the USB standard
Eg. ADG736 USB 1.1 eye diagram. Input = random, 3V, 12Mbps differential
signal Excellent ‘open eye’ characteristic
Eye characteristic Switch spec
No loss Low Ron
Open eye, good edge integrity
High B/W, good flatness.
Low jitter Linear with time.
Equal propagation delays
Channel to channel symmetry.
What makes a good eye diagram?What makes a good eye diagram?
New USB1.1 Compatible part: ADG787 Dual SPDT Switch (Break-Before-Make)
KEY BENEFITSKEY BENEFITS Bandwidth: 150MHz WLCSP, LFCSP & µSOIC packages 2 Ron Flatness 0.4
-40°C – 85°CWLCSP; LFCSPµSOIC
30pC150MHz0.4 2 1.8 V to 5.5 V
TempPackageQinjBandwidthRON FlatRONVRANGE
SpecificationsSpecifications
S1A
S1B
S2A
S2B
IN2
ADG787
D1
D2
IN1
ScheduleSchedule
Released
ADG787: Ron vs Supply for the 4 channels, Vdd = 4.5V
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 3.9 4.2 4.5Voltage
Ron
S1A S1B S2A S2B
Note: Channel matching very good
USB 1.1 Selection TableGeneric Config. Supply USB1.1 Package Spec’s
ADG711/2/3 Quad SPST 5V 16ld TSSOP/SOIC 2Ω Ron, >200MHz B/W
ADG781/2/3 Quad SPST 5V 20ld CSP 2Ω Ron, >200MHz B/W
ADG721/2 Dual SPST 5V 8ld uSOIC 2Ω Ron, >200MHz B/W
ADG736 Dual SPDT 5V 10ld uSOIC 2Ω Ron, >200MHz B/W
ADG774 Quad SPDT 5V 16ld SOIC 2Ω Ron, >200MHz B/W
ADG784 Quad SPDT 5V 20ld CSP 2Ω Ron, >200MHz B/W
ADG788 Quad SPDT 5V 20ld CSP 2Ω Ron, >200MHz B/W
ADG787 Dual SPDT 5V 10ld MSOPWLCSP
2Ω Ron, 150MHz B/W
ADG821/2 Dual SPST 5V 8ld uSOIC <1Ω Ron, 24MHz B/W
ADG836 Dual SPDT 3.6V 12ld LFCSP/10ld uSOIC
<1Ω Ron, 57MHz B/W
ADG709 Dual 4:1 Mux 5V 16ld TSSOP 3Ω Ron, 100MHz B/W
ADG729 Dual 4:1 Mux 5V 16ld TSSOP I²C, 3Ω Ron, 100MHz B/W
ADG739 Dual 4:1 Mux 5V 16ld TSSOP SPI, 3Ω Ron, 100MHz B/W
ADG759 Dual 4:1 Mux 5V 20ld CSP 3Ω Ron, 100MHz B/W
USB 2.0 Switch requirements
USB2.0 signal levels: +/-400mV diff signal
Bandwidth Requirements: Random 480Mbps
Low Absolute Ron and FlatnessSimilar requirements to USB1.1
Backward CompatibilityMajority of systems need to be
backward compatible with USB1.1Source: ADG774A / ADG3257
Bandwidth: 410MHz
Comparisons of eye diagrams
ADG3257 (BW = 410 MHz) ADG736 (BW = 200MHz)
Input = random, 400mV, 480Mbps differential signal
USB 2.0 & Universal USB Selection TableGeneric Config. Supply USB2.0 Package Specifications
AG3241 SPST 3.3V SC70, SOT66 2Ω Ron, >480MHz B/W
ADG3242 2x SPST 3.3V SOT23 2Ω Ron, >480MHz B/W
ADG3243 2x SPST 3.3V SOT23 2Ω Ron, >480MHz B/W
ADG3245 8x SPST 3.3V TSSOP, LFCSP 2Ω Ron, >480MHz B/W
ADG3246 10x SPST 3.3V TSSOP, LFCSP 2Ω Ron, >480MHz B/W
ADG3247 16x SPST 3.3V TSSOP, LFCSP 2Ω Ron, >480MHz B/W
ADG3248 SPDT 3.3V SC70 2Ω Ron, >480MHz B/W
ADG3249 SPDT 3.3V SOT23 <1Ω Ron, >480MHz B/W
Generic Config Supply Univ Package Specifications
ADG774A 4x SPDT 5V QSOP 2.2Ω Ron, >400MHz B/W
ADG3257 4x SPDT 5V QSOP 2.2Ω Ron, >400MHz B/W
The World Leader in High Performance Signal Processing Solutions
Digital Switches/Level TranslatorsStd translators, Wide range translators, Fully bi-
directional translators
What’s driving the need for translators? Digital voltage migration following Moore’s Law to 90nm and below
Faster operation, lower power90nm requires 1.2V supply45nm in pipelineExpect no i/o due to COST
Analog ICs, legacy ICs at 2.5V and higher, in generalPerformance reasons, S/N ratio
Need to communicate between ICs!
Level TranslationSwitch
+3.3 VLOGIC
+2.5 VLOGIC
+3.3 V BUS +2.5 V BUSVOH MIN
VOL MAX
0 V
High
Low
VIH MIN
0 V
High
Low
VIL MAX
“Oops parts”
Translators adjustCMOS/TTL for zerobit loss
Aim at first generation
2nd gen will be integrated
ADG3241 – 3.3 V/2.5 V 1-Bit, Level Translator Digital Switch Portfolio (Low-Bit)KEY BENEFITSKEY BENEFITS Selectable Level Translation
Allow direct 3.3 V to 1.8 V translation No need for discrete components
High Performance In Small Size Data Rate 1.5 Gbps
Very low 225ps propagation delay Uni-directional Level Translation, Bi-directional
signal path Tiny SC70 package
ADG3242/3 ADG3248 ADG3249 SOT23
ADG3242 is common enable ADG3243 is individual enable
Space-saving SC70 option 2:1 Mux/de-mux configuration Std level translation* only
SOT23 2:1 Mux/de-mux configuration Allows 3.3 V/1.8 V translation
*Std level translation is 3.3V/2.5V or 2.5V to 1.8V translation Exception is 3.3V 1.8V translation
Prop Delay Package Temp Data RateLevel Trans Data Trans RON Price @ 1k
225ps 6-lead SC70 -40°C – +85°C 1.5 Gb/s Uni-dir Bi-dir 4.5 $ 0.43
ADG3245 – 3.3 V/2.5 V 8-Bit, Level TranslatorDigital Switch Portfolio (High-Bit)KEY BENEFITSKEY BENEFITS Selectable Level Translation
Allow direct 3.3 V to 1.8 V translation No need for discrete components
High Performance In Small Size Data Rate 1.244 Gbps
Very low 225ps propagation delay Uni-directional Level Translation, Bi-directional
signal path TSSOP and LFCSP packages
ADG3246 ADG3247 10-Bit version 16-Bit version
Prop Delay Package Temp Data RateLevel Trans Data Trans RON Price @ 1k
225ps TSSOP, CSP -40°C – +85°C 1.244 Gb/s Uni-dir Bi-dir 4.5 $ 0.71
Exception is 3.3V 1.8V translation
Level TranslatorsKey FeaturesKey Features Wide range voltage translation
1.6 V to 3.6 V Supply UP/DOWN Level Translation, Uni-Directional Signal Path Low Current Consumption <5mA Tiny packages:
ADG3231 in 6-SOT23 and ADG3232 in 8-SOT23New option… ADG3231 in SOT666 (SC89)… 40% smaller than SC70!
Vcc1 Vcc2
In Out
ADG3231
Vcc1(3.6V)
In1In2
Vcc2(1.6V)
Out
ENADG3232
ADG330X Family- Summary Table
PartNumbe
r
Size(bits)
EN LogicLevel
A I/O state
(EN=0)
Y I/O state
(EN=0)
Package
ADG3308 8 VCCY Tri-stated Tri-stated 20 Lead TSSOP 20 Lead LFCSP20 bump WLCSP*
ADG3304 4 VCCA/VCCY Tri-stated Tri-stated 14 lead TSSOP20 lead LFCSP12 bump WLCSP*
ADG3301 1 VCCA/VCCY Tri-stated Tri-stated 6 lead SC70
ADG3300** 8 VCCA/VCCY 6K pull-down Tri-stated 20 lead TSSOP,20 bump WLCSP*
*Under development**Pin to pin compatible with MAX3000/1/2/3
ADG3308 Bidirectional Level Translator
A1 Y1
GND
VCCYVCCA
A8 Y8
A7 Y7
A6 Y6
A5 Y5
A4 Y4
A3 Y3
A2 Y2
EN
8 – Channels.
Wide 1.15 to 5.5V supply range.
Low quiescent current (<5A).
All I/O pins are tri-stated (EN=Low).
EN pin accepts only VCCY compatible levels.
Data rate >25Mbps
Packages:20 lead TSSOP20lead 4x4mm body LFCSP20 bump WLCSP (under development)
ADG3304 Bidirectional Level Translator 4 – Channels.
Wide 1.15 to 5.5V supply range.
Low quiescent current (<5A).
All I/O pins are tri-stated (EN=Low).
EN pin accepts both VCCY/VCCA compatible levels.
Data rate >25Mbps
Packages:14 lead TSSOP20lead 4x4mm body LFCSP12 bump WLCSP (under development)
A1 Y1
GND
VCCYVCCA
A4 Y4
A3 Y3
A2 Y2
EN
ADG3301 Bidirectional Level Translator1 – Channel.
Wide 1.15 to 5.5V supply range.
Low quiescent current (<5A).
All I/O pins are tri-stated (EN=Low).
EN pin accepts both VCCY/VCCA compatible levels.
Data rate >25Mbps
Packages:6 lead SC70
GND
VCCYVCCA
A Y
EN
ADG3300 Bidirectional Level Translator
A1 Y1
GND
VCCYVCCA
A8 Y8
A7 Y7
A6 Y6
A5 Y5
A4 Y4
A3 Y3
A2 Y2
EN
8 – Channels second source for MAX3000/1/2/3.
Wide 1.15 to 5.5V supply range.
Low quiescent current (<5A).
EN pin accepts VCCY/VCCA compatible levels.
Data rate >25Mbps
Packages:20 lead TSSOP20 bump WLCSP (under development)
ADG330X Family- ApplicationsMemory Address & Data Bus Level Translation
P Memory
A I/O Y I/O
ADG3300/8
A I/O Y I/O
ADG3300/8
Data bus
Address bus
ADG330X Family- ApplicationsLevel translation For Dual Full Duplex Serial Port
VCCA
A1
A2
A3
A4
EN GND
Y4
Y3
Y2
Y1
VCCY
ADG3304Microprocessor/Microcontroller/DSP
TX1
RX1
TX2
RX2
RX1
TX1
RX2
TX2
GNDGND
1.8V 3.3V
100nF
Microprocessor/Microcontroller/DSP
100nF
Designing with ADG330X Level translators
General requirements for Level translators:
Supply voltage range
Speed
Driving requirements
Loading requirements
Designing with ADG330X Level translators
Supply voltage range:
VCCA: 1.15V to 5.5V
VCCY: VCCA to 5.5V
IMPORTANT: VCCA ≤ VCCY !
Designing with ADG330X Level translators
VCCY
VCCA1.8V
(1.65V to 1.95V)2.5V
(2.3V to 2.7V)3.3V
(3.0V to 3.6V)5V
(4.5V to 5.5V)1.2V
(1.15V to 1.3V)25Mbps 30Mbps 40Mbps 40Mbps
1.8V(1.65V to 1.95V)
- 45Mbps 50Mbps 50Mbps2.5V
(2.3V to 2.7V)- - 60Mbps 50Mbps
3.3V(3.0V to 3.6V)
- - - 50Mbps5V
(4.5V to 5.5V)- - - -
* Represents the minimum guaranteed data rate for the given loading conditions in both A-Y and Y-A directions. Load capacitance: 50pF for A to Y direction, 15pF for Y to A direction.
Guaranteed Data rate
Selection Guide Available (www.switch-mux.com)
Updated every 6 months!