Bill W. Haynes
Slide 1
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
Growing # of Applications for SERDES PCI Card
Available SERDES based PLD Devices
Status of Development Cards
Status of QIE Readout Cards for Test beam
Simulation Results of TDC w/ 400ps Resolution Discussed at San Luis Potosi Workshop
Project Status
Bill W. Haynes
Slide 2
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
Applications for Serdes PCI Design
Time to Digital Converter (TDC)
Timing Distribution System (TDS)
Mesh Network for Lattice Gauge PC Farm
ReProgrammable data link like the QIE readout Card
Other Applications w/ PLD Based SERDES Devices?
Bill W. Haynes
Slide 3
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
Orca ORT82G5 from Lattice 8-channel 3.5 Gbs SERDES
In production & Cost is ~$300 20-channel 3.5 Gbs SERDES in development
Xilinx-II Pro FPGA 4-channel 3.125 Gbs SERDES
In production & Cost is ~$300 16-channel 3.125 Gbs SERDES in development
Altera Stratix FPGA EP1S25 780-pin w/ 58-channels of LVDS @ 840 Mbs
In production & Cost is ~$800 EP1S25 1020-pin w/ 78-channels of LVDS @ 840 Mbs
In production & Cost is ~$1500 EP1S40 1020-pin w/ 80-channels of LVDS @ 840 Mbs
Available next month & Cost is ~$UNK Cypress Programmable Serial Interface (PSI)
CPLD w/ a dual channel 2.5Gbs SERDES device Discontinued
Available SERDES Based PLD Devices
Bill W. Haynes
Slide 4
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
From Detector
156 MHzRef Clk
Serdes Control
16bit Data
FPGASerial
Receiver
General I/O
General I/O
PC
I B
us
ORCA/XilinxFPGA
TDC Based on a SERDES PLD Devices
Optical or CML
Simplified TDC Block Diagram
Notes: 1.)The SERDES receiver must be capable of locking to the reference clock.2.) The 8b10b encoder of the receiver must be capable of being by-passed.
Bill W. Haynes
Slide 5
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
8 channel Orca ORT82G5 w/ 3.5 Gbs SERDES Resolution is ~285ps Status: In final stages of artwork layout
80 channel 840 Mbs links (LVDS), Altera Stratix EPS25 or EPS40 Resolution is ~1.2ns Status: Artwork layout will start in earily September, 2002
4 channel Xilinx XC2VP4 Virtex-II Pro w/ 3.125 Gbs SERDES Resolution is ~320ps Status: will start layout when Orca layout is complete
PCI Cards with TDC functionality
Bill W. Haynes
Slide 6
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
8-Channel ORT82G5 TDC
Bill W. Haynes
Slide 7
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
Our First Serdes Based Design
PCI Card w/ two 2.5Gbs TI Serial Links (CoLink) One Differential Copper Link One Optical Link Designed May 30, 2000
Bill W. Haynes
Slide 8
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
QIE Readout Card
QIE Readout Card is a Modified CoLink Card
Bill W. Haynes
Slide 9
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
QIE Readout Card (QIElink) One Optical Link @ 700 Mbs Input circular buffer (2K x 16bit)
Stores up to the last 2K words of QIE data prior to a NIM stop Nim Stop Input
Inhibits additional circular buffer writing of QIE data Sets CSR register bit for PCI readout of QIE data
Current Status for Fall Test Beam Four cards assembled and tested Cards were tested in pairs
One to generate QIE data and a NIM stop The other to store the QIE data and trigger a PCI readout
PCI driver for Windows and Linux is complete See Dave Slimmer for details
QIE Readout Card
Bill W. Haynes
Slide 10
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
TDC w/ 400ps Resolution Input Pulse Width = FFFF F800 0000-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns Reference Counter Time = T Ref = 105.6ns
T Ref Offset = # of 0 bits from T Ref x 400ps = 0 x 400ps = 0ps
Input Prop. Delay = 29.200075ns + T Ref Offset = 29.200075ns 105.6ns
FFFF
Bill W. Haynes
Slide 11
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
TDC w/ 400ps Resolution Input Pulse Width = 7FFF FC00 0000-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns Reference Counter Time = T Ref = 105.6ns
T Ref Offset = # of 0 bits from T Ref x 400ps = 1 x 400ps = 400ps
Input Prop. Delay = 28.800075ns + T Ref Offset = 28.800075ns +400ps =
7FFF
29.200075ns
105.6ns
Bill W. Haynes
Slide 12
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
TDC w/ 400ps Resolution Input Pulse Width = 3FFF FE00 0000-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns Reference Counter Time = T Ref = 105.6ns
T Ref Offset = # of 0 bits from T Ref x 400ps = 2 x 400ps = 800ps
Input Prop. Delay = 28.400075ns + T Ref Offset = 28.400075ns +800ps =
3FFF
29.200075ns
105.6ns
Bill W. Haynes
Slide 13
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
TDC w/ 400ps Resolution Input Pulse Width = 0FFF FF80 0000-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns Reference Counter Time = T Ref = 105.6ns
T Ref Offset = # of 0 bits from T Ref x 400ps = 4 x 400ps = 1600ps
Input Prop. Delay = 27.600075ns + T Ref Offset = 27.600075ns +1600ps =
0FFF
29.200075ns
105.6ns
Bill W. Haynes
Slide 14
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
TDC w/ 400ps Resolution Input Pulse Width = 0001 FFFF F000-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns Reference Counter Time = T Ref = 105.6ns
T Ref Offset = # of 0 bits from T Ref x 400ps = 15 x 400ps = 6000ps
Input Prop. Delay = 23.200075ns + T Ref Offset = 23.200075ns +6000ps =
0001
29.200075ns
105.6ns
Bill W. Haynes
Slide 15
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
TDC w/ 400ps Resolution Input Pulse Width = 0000 FFFF F800-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns Reference Counter Time = T Ref = 105.6ns + 6.4ns = 112.0 ns
T Ref Offset = # of 0 bits from T Ref x 400ps = 0 x 400ps = 0ps
Input Prop. Delay = 29.200075ns + T Ref Offset = 29.200075ns +0ps =
FFFF
29.200075ns
112.0ns
Bill W. Haynes
Slide 16
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
TDC w/ 400ps Resolution Input Pulse Width = 0000 0FFE 0000-> 11bits x 6.4ns/16 = 11 x 400ps = 4.4ns +/-200ps Reference Counter Time = T Ref = 105.6ns + 0ns = 105.6 ns
T Ref Offset = # of 0 bits from T Ref x 400ps = 4 x 400ps = 1600ps
Input Prop. Delay = 27.600075ns + T Ref Offset = 27.600075ns +1600ps =
0FFE
29.200075ns
105.6ns
Bill W. Haynes
Slide 17
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
TDC w/ 400ps Resolution Input Pulse Width = 0000 0E00 0000-> 3bits x 6.4ns/16 = 3 x 400ps = 1.2ns +/-200ps Reference Counter Time = T Ref = 105.6ns + 0ns = 105.6 ns
T Ref Offset = # of 0 bits from T Ref x 400ps = 4 x 400ps = 1600ps
Input Prop. Delay = 27.600075ns + T Ref Offset = 27.600075ns +1600ps =
0E00
29.200075ns
105.6ns
1.0ns
Bill W. Haynes
Slide 18
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
TDC w/ 400ps Resolution Input Pulse Width = 0000 0800 0000-> 1bits x 6.4ns/16 = 1 x 400ps = 400ps +/-200ps Reference Counter Time = T Ref = 105.6ns + 0ns = 105.6 ns
T Ref Offset = # of 0 bits from T Ref x 400ps = 4 x 400ps = 1600ps
Input Prop. Delay = 27.600075ns + T Ref Offset = 27.600075ns +1600ps =
0800
29.200075ns
105.6ns
400ps
Bill W. Haynes
Slide 19
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
Timing (or Clock) Distribution System (TDS) The Far-End of the Cable is a Common Reference for all Receivers Reference can be Determined by: T = (Round Trip Time)/2 Or The Time from Incident Wave to the Reflected Wave Divided by Two
I-Wave
R-Wave
Round Trip Time = 2T
I-WaveR-Wave
TfarEnd= (TI-Wave – TR-Wave)/2
I-Wave
R-Wave
TfarEnd= (TI-Wave – TR-Wave)/2
TfarEnd= (TI-Wave – TR-Wave)/2
Bill W. Haynes
Slide 20
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
TDS Simpified Block Diagram
Bill W. Haynes
Slide 21
August 22, 2002
CKM Precision Timing
CKM Workshop at Fermilab, Illinois
Altera FPGA