© 20011
General Presentationon IMEC’s
Thematic Design Activities
Ivo Bolsens, Hugo De Man+ 125 [email protected]
© 20012
IMEC organizationCEO: Gilbert Declerck
DivisionsDESICS: design technologyIvo Bolsens
SPT: process technologyLuc van den Hove
STDI: silicon techn. & device integrationHerman Maes
MCP: microsystems & packagingRobert Mertens
INVOMEC: trainingEtienne Bourdeaud’hui
© 20013
Mission
Design of
Architectures, Methods and Tools
for the Implementation of
Multimedia
Internet Terminals
© 20014
How
• Study requirements of embedded IT systems
• Identify and solve RELEVANT design challenges
- build application demonstrators• Work out systematic design methods and supporting tools
- build tools for real-life design support• Develop re-usable, parameterized, white-box IP
• Train and educate
- industry
- university
© 20015
Measures of success
• scientific impact
• cooperation with universities in complementary fields
• international network of cooperation with most of the important industrial performers in our field
• portfolio of protected intellectual property
• transfer of technologies to existing companies
• creation of new spin-off companies
• attracting foreign investments in the field of microelectronics and ICT
• turn-over of well trained researchers to industry
© 20016
Bridge the gap between systems and silicon
200 M Transistors
Physics Hell
5 million lines of VHDL
Systems Heaven
0.1µm=1/300 Hair
aJAVA, CORBA, JINI
Power/ cm**2 ~ V**33T_intercon ~ *l**
© 20017
Intelligent Home
ReconfigurableAccess
Terminal
155Mb/s WLAN
5GHz
<1 Watt10Gop/s
MPEG 4>100 Gop/s 5 Gtr/s 5 Watt
WWW
© 20018
DESICS organization
DIMA: design of integrated multimedia applications• MICS: multimedia image compression systems
• EMSYS: embedded systems design
• SEMP: system exploration for memory & power
DISTA: design of integrated systems for telecom applications
• MIRA: mixed signal & RF applications
• WISE: wireless systems
• DBATE: digital broadband terminals
© 20019
Head End
ServiceServer
Homegateway
routerstorage
basestation
IPv6HFC
Configurable Home Terminal
Internethome
Appliance
CSL
modem
IP Home network
User premises
© 200110
Embedded connectivity
Hardware Hardwaresignals
packetsOS OS
Middleware Middleware RPC
Distributed Application
250 W,700 MHz,128 MByte
2 W,30 MHz,256 KbytePLUG&PLAY
VCR
© 200111
Reconfigurable Software
Hardware
Front
End
Tx/Rx
DSP
CFIL/CB
CTL MON
RTOS
Agent
TCP/IP
VM
AgentAgent
To I/O
Challenges
user
data
software
agents
parameters
& synchroAnalog
Digital
© 200112
Challenges in Dynamic Reconfiguration
Run-time FPGA management
• dynamical creation and deletion of HW processes
• dynamical creation of the related HW/SW interfaces
• dynamical extension of the instruction set- downloading of FPGA configuration for additional instruction
Fast HW compilation
Novel FPGA architectures optimized for partial runtime configuration
Performance Estimation (dynamic, configuration time)
© 200113
Networked re-configurable computing
Hardware Platform
Real-TimeOperating System
Middleware Layer
Native DeviceDriver
Java NativeInterface
FPGA API
Application Layer (Java applet +FPGA bitstream)
LocalBus
VirtualBus
FPGA Controller
FPGA
Software Hardware
© 200114
The first demonstrator: FPGA based NetCam
• first FPGA-based “thin-server” Internet Appliance (vs. Dedicated, Linux or uC based) • low power (FPGA ~ 0.7 W)• throughput scales up to 80 Mb/s
Netscape
10 Base T
HTTP
IP layers
GIF Engine
10 Base T
Ibis CMOSsensor
TCP/IP layers
FPGA
InternetClient
network
Reconfiguration
ATMELEEPROM
request
image
© 200115
World’s first 80 MB/sec WLAN technology
wired backbone
Base station155Mb/smulti-user rxantenna diversity
Multi-path fading
• Orthogonal Frequency Division Multiplexing (OFDM) • Turbo-coding• Spatial Division Multiple Access (SDMA)• Hiperlan-2/ IEEE 802.11 compatible
© 200116
Single-package transceiver
BiCMOS:RF
circuitry
MCM: interconnect
inductors, capacitors, resistors,
filters, baluns
CMOS: IF and digital
circuitry
MEMS: switches, varactor,
resonators
Antenna
© 200117
Multimedia : MPEG-4 member SCtee
- Diversity : 3D, Facial and Body Animation, Video- Scalability : time, space, SNR- Interactivity : behaviour = f (input bits, user)
© 200118
Focus
• Graceful degradation, QOS
• Encode once/ decode everywhere
• Reduces the terminal cost (“soft” conformance with
pathological cases)
• Man-Machine Interface : Facial Animation
• Real-time SOFTWARE video-coding of CIF images
• Application Specific Processor for Wavelet coding
Demo
© 200119
Software specification: more than 200 000 lines Chundreds of fileswritten by approx. 80 teams
Challenges
Huge requirements: > 2 GOP/s > 6 GB/s> 10 MB storage
Multimedia: MPEG 4 JPEG2000Nowadays implementations:small images (QCIF: 176x144)decoding onlynot real-timeseveral W
Wanted features:large images (TV)encoding and decodingreal-time100 mW (mobile)
Several orders of magnitude in performance and power dissipation
need to be gained
Drastic reduction of designcomplexity required
© 200120
World’s first MPEG-4 compliant silicon
Max 30 fps CIF (352x288)
Scalable architecture
© 200121
C/C++ system refinement + exploration
Algorithms Data Structures+
ARM
IP1 IP2
RAM ROM
Architecture
Processor architecture
RAMRAM
ROM
MMU
custom logic
DSP
ROM microprocessor
© 200122
Deeply embedded system
All of this fits in one, cheap, package
Viterbi
Equal.
Demodandsync
phone
book keypadintfc
protocolcontrol
de-intl&
decoder
RPE-LTP
speechdecoder
speech
qualityenhancement
voice
recognition
phone
bookDMA
S/P
Multi-DSP core
RAM & ROM
Dedicated logic
A
D
digitaldownconv
InterfacesP coreDedicated logic
• accelerator synthesis
multi-DSP core
• retargetable ASIP compiler
Memory/MMUInterfaces
• system integration
Analog
© 200123
P core
• system layer compiler
Dedicated logic
multi-DSP core
memory/MMU
• dynamic + static mem mngnt + addr expr.
Interfaces
Analog
• A/D + RF
Deeply embedded system
All of this fits in one, cheap, package
Viterbi
Equal.
Demodandsync
phone
book keypadintfc
protocolcontrol
de-intl&
decoder
RPE-LTP
speechdecoder
speech
qualityenhancement
voice
recognition
phone
bookDMA
S/P
P core
RAM & ROM
Memory/MMU
A
D
digitaldownconv
Analog
© 200124
• System Specification and System-level Refinement with Exploration Support (algorithm design level, concurrent task level, system timing simulation)
• Data Transfer and Storage Exploration for Massive Real Time Data Manipulation (dynamic memory mngntstatic transfer and storage, address generation)
• Co-Design for Heterogenous Implementation Paradigms (refinement from unified HW/SW model,RTOS modeling, complete system simulation)
• RF front-end exploration (fast mixed-signal co-simulation, chip-package co-design, noise coupling)
Current challenges and solutions
Tipsy, Matisse-TCM
Matisse-DMM, Atomium/Acropolis, Adopt
Ocapi-2, SoCos
Fast
© 200125
SoC or …---… (S.O.S.)
Design productivity gap grows !
• Complexity increase 40 % per year
• Design productivity increase 15 %per year
250
200
150
100
50
1995 1998 2001 2004 2007
[ 106 T/chip ]
[ SIA roadmap ]
© 200126
System-level design
Solution
• Paradigm shift
- Higher abstraction level
- Executable specs
- Object-oriented design
- Multi-paradigm modeling
- Behavioral IP re-use
- Incremental refinement to RT-HDL (HW) and C/C++ (SW)
© 200127
System design issues in IT-Application domain
Network layer protocols (ATM, IP, …)Multi-media algorithms with dynamic character (MPEG4, MPEG7)Wireless and wired terminals (Internet, WLAN, ADSL, …)
E.g.:
IN622 Mb/s
OUT
OUT
622 Mb/s
622 Mb/s
53 cycles Stringent real-time constraints
Embedded system
Complex data sets• Large and irregular dynamically allocated data• Huge memory accesses
RoutingRecord
PacketRecord
FIFO
200 accesses
data in
ISR
time
data outrouting reply
out
Processes• Dynamic and concurrent processes• Global/local control• Little arithmetic/ logic processing
© 200128
Global concurrency management design flow for dynamic concurrent tasks with data-dominated behaviour
Dynamic memory mgmtDynamic memory mgmt
Task concurrency mgmtTask concurrency mgmt
Physical memory mgmtPhysical memory mgmt
Address optimizationAddress optimization
SWSWdesigndesignflowflow
HWHWdesigndesignflowflow
Concurrent OO specConcurrent OO spec
Task scheduleAllocate/assign
Transform
System control
HW-Ctrl uCtrl
Memory organ.
uProcDSPHWUnified modelPartitionRefine/compile
SW/HW co-designSW/HW co-design
Task1 Task2
Task3
© 200129
TCM steps aim at removing the bottlenecks for better performance
Optimized system specification
Task-level system architecture
Inter-task DTSE
Task concurrency mngnt
Task1 Task2
Task3
Inter-task interface refinementTask to processor assignment
1 Task/thread scheduling
1 23
2 Task conc. Extraction/trafo
Array-processor allocation
VirtualProc1
VirtualProc2
2 Proc
© 200130
The gray box approach focuses on the most relevant TCM issues
C++ Specification
Improved Gray-box<10%
Black-box TCG1%
White-box TCG 100%
Initial TCG 50%
task concurrencyextraction & improvement
Initial gray-box TCG 10%
High LevelSpecification
Simplify the model
Reduce complexityCreate freedom
© 200131
Task Level DTSE and TCM
Task levelDTSE
concurrencyextraction/
improvement
static scheduling(partial ordering)
grey-box
model specification
dynamic scheduling
© 200132
Results on IM1 playerMemorySizePre
MemorySizePost
MemoryEnergyPre
MemoryEnergyPost
OtherEnergy
Gain
1HW 86.9kB 14 .8kB 0.78mJ 0.16mJ 2.58mJ 19%
2HW 193kB 19.41kB 1.54mJ 0.19mJ 4mJ 25%
Cost
Time-Budget (MA cycle budget)
x
x
© 200133
The 2-processor approach (scheduling + assignment)
ARM
Processor
1Vdd=1V Vdd=3.3V
ARM
Processor
2
Taskn
Task2
Task1
© 200134
Comparison of scheduling the original and transformed graphs
original
Transformed
© 200135
Combination of static and dynamic scheduler
12
3
th read fram e 1
A B
th read fram e 2
1 3 2
Static Scheduling
Static Scheduling
A BDynamic
Scheduling
1 A B 3 2
Static scheduling: done at compiling time, exploring all the optimization possibility
Dynamic scheduling: done at run time, providing flexibility and dynamic control at low cost
© 200136
Dynamic Scheduling result
0
10
20
30
40
50
60
1 2 4 6 8
Two Proc.(vlow = 1V, vhigh = 5V)
One Proc.(v = 5V)
node number in timer threads
total energy
39%32% 32%
24% 20%
© 200137
SoC refinement and exploration
SoC appl. + timing
Processmgmt
constr.
Memorymgmt
constr.
• System requirements
- Abstract functionality
- Real-time constraints
- Target platform constr.
• Implementation
- Final hardware
- Appl. software
- OS services optimized for application
Target platform Final platform (Silicon)
Processmgmtimpl.
(HW/SW)
Memorymgmtimpl.
(HW/SW)
Applicationimplementation
(HW/SW)
REQUIREMENT
REAL
© 200138
Refinement and explorationMemory mgmt
• Dynamic memory
- alloc / free (C)
- new / delete (C++)
- abstract data type refinement
- virtual memory mgmt
• Static memory- platform-independent
code transformations
- real-time cost-optimal physical memory organisation
• Address optimisation
Process mgmt
• Task level concurrency mgmt (platform indep.)
- transformations
- static/dynamic scheduling
- resource allocation
• Instruction-level concurrency mgmt
- refinement from unified HW/SW model
- RTOS modeling/simulation including timing
- traditional HW/SW co-design and compilers
© 200139
Refinement - OCAPI / MATISSE
SoC appl. + arch.
Processmgmt
Memorymgmt
OSAPI
• Virtual prototype
- Soft implementationusing host OS and host hardware
• Implementation
- Target hardware
- OS services optimized for application
Host HW (HP/PC) Target HW (Silicon)
Processmgmtimpl.
(HW/SW)
Memorymgmtimpl.
(HW/SW)
Applicationimplementation
(HW/SW)VIRTUAL
REAL
© 200140
Unified Modeling and Refinement of HW and SW
OCAPI-xlOCAPI-xlC++ Class LibC++ Class Lib
High LevelHigh LevelSystem ModelSystem Model
Flexible Primitives expressFlexible Primitives express• ConcurrencyConcurrency• CommunicationCommunication• Interface design/reuseInterface design/reuse
RefinedRefinedModelModel
Built-in Code Generators createBuilt-in Code Generators create• VHDL/Verilog/CVHDL/Verilog/C• TestbenchesTestbenches
unified HW/SW model
© 200141
SoC++ design flow
C++ System Model
HDL/SystemC C
Code Generation
System Link & Interface Synthesis
FSMD OSAPI
HW SW
© 200142
System Model
HDL/SystemC C
Code Generation
System Link & Interface Synthesis
FSMD OSAPI
HW SW
© 200143
Global data management design flow for dynamic concurrent tasks with data-dominated behaviour
Dynamic memory mgmtDynamic memory mgmt
Task concurrency mgmtTask concurrency mgmt
Physical memory mgmtPhysical memory mgmt
Address optimizationAddress optimization
SWSWdesigndesignflowflow
HWHWdesigndesignflowflow
Concurrent OO specConcurrent OO spec
MgmtUnit
Memory
controller
ASU ASU
processor
memmemmem
MemoryAllocationAssignment
SW/HW co-designSW/HW co-design
Virtual
MgmtMemory
AbstractDataTypes
keydata
keydata
Binary Tree (BT)
keydata
Sub-pool per size
Free Blocks
© 200144
Data Management Flow
Dynamic
Memory
Mngnt.
Physical
Memory
Mngnt.
VirtualMemory
Segments
ConcreteData types
PhysicalMemories
ADT Abstract Data Type (ADT) Refinement
Virtual memory mgmt (VMM) Refinement
Physical memory mgmt(PMM) Refinement
© 200145
ATM_cell * Data_In;Association_Table * Routing_Table;
Routing_Table = new Association_Table();Data_In = new ATM_cell();
if ( Routing_Table->Lookup(Data_In) ) ...
Matisse: ADT refinement
Impl. alternatives
10 4
10 3
10 2
10 1
10 0
Power function Area function
10 4
10 3
10 2
10 1
10 0
Array (AR)
data
data
data
data
Array * Routing_Table;
Array ();
keydata
keydata
keydata
Linked List (LL)
keydata
Linked_List * Routing_Table;
Linked_List ();
Binary_Tree * Routing_Table;
Binary_Tree ();key
data
key
data
Binary Tree (BT)
key
data
© 200146
ADT refinement results
Select best DT impl. for each ADT
1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132100
101
102
103
104
Different data types
Pow
er
cost
fu
nct
ion PA(B)
LL(A)PA(B)BT(A)
PA(A)AR(B)
LL(A)LL(B)
© 200147
VM size for ATM MUX in network 1
1 VMSSize = 133 mm2
Power = 110 mW
PA(9)PA(5)
AR(4)
PA(5)
PA(5)
AR(4)
AR(4)
3225
6
3 VMSSize = 137 mm2
Power = 37 mW
PA(9)
PA(5)
AR(4)
PA(5)
PA(5)
AR(4)
AR(4)
256
32
2 VMSSize = 137 mm2
Power = 49 mW
PA(9)PA(5)
AR(4)
PA(5)
PA(5)
AR(4)
AR(4)
256
322 VMSSize = 137 mm2
Power = 68 mW
PA(9)
PA(5)
AR(4)
PA(5)
PA(5)
AR(4)
AR(4)
256
32
© 200148
Memory = CPU Performance Bottleneck
µProc:60%/year.
CPU
DRAM:7%/yearDRAM
1
10
100
1000
1980 1985 1990 1995 2000
Processor-MemoryPerformance Gap:(grows 50% / year)
Performance
Time
“Moore’s Law”
[Patterson]
© 200149
Data-transfer and data-storage bottlenecks: SDRAM access
ClientMain
Memory
Client
data
128 - 1024bit bus
LocalLatch
LocalSelectbank1
LocalLatch
LocalSelectbankN
Cacheand
Bankcomb.
GlobalBankSelectControl addr
ctrl
Wide word Burst mode
© 200150
Data-transfer and data-storage bottlenecks: cache misses
ClientMain
Memory
MainMemory
Processors
Data-paths regf
16kBN-portSRAM
L1 cache
1MB1/2-portSRAM
L2 cache 256 MB (S)DRAM
Many cache missesPage Loading
© 200151
Data-transfer and data-storage bottlenecks: system bus load
MainMemoryL2 cache
Datapaths
L1 cache
System chip
Harddisk
OtherSystem
Resources
OtherSystem
Resources
Diskaccess
bus
Mainsystem
bus
L2bus
© 200152
Memory = Power Bottleneck
PROC
DP
SRAM
Embedded
DRAM
SR
AM
MMU
EXTERNALMEMORY
P(Ext. Access) = typ. 30 x P(Arithmetic Operations)
P(Int. Memory) = typ. 40 % - 60 % P(Chip)
EXTERNALMEMORY
© 200153
Multi-processor System Design
Image Proc System
Standardsubsystem :
detailed solutionlocally optimized
by expert
Subsystemresembles a
standard solutionbut needs small
adaptations
Newcomplex
subsystem
E.g.: 2D convolution E.g.: DCT for specific coderE.g.: quadtree coder
Locally optimized
Globally optimized => exploration!
Buffer Buffer
© 200154
Platform design requires change
Multi-media platform city
Traditionalarchitecture city
Traditional compiler boulevard
Power volcano (multi-media)
processor trend= Application engineer
Cobblestone bypassroad (requires paving)
© 200155
Data Transfer & Storage Principles
Processor Data Paths
L1Cache
L2Cache
Chip
Cache & BankRecombine
Local Latch 1 +Bank 1
Off-chip SDRAM
Local Latch N +Bank N
4 Avoid N-port Memories 3 Exploit memory hierarchy
1 Reduce redundant transfers2 Introduce Locality
6 Exploit limited life-timeand data layout freedom 5 Meet real-time constraints
© 200156
Pareto curves allow task trade-off decision: DAB illustration
TASK-1 TASK-2 TASK-3
0 10000 20000 30000 40000
Execution time
0
4
8
12
0 50000 100000
Execution time
0
5
10
15
0.0 2.0 4.0 6.0
Execution time
0
500
1000
En
erg
y
Source: Digital Audio Broadcast
Mapped on two processors
© 200157
Pareto curves allowtask trade-off decision
0 10000 20000 30000 400000
4
8
12
0 50000 1000000
5
10
15
0.0 2.0 4.0 6.00
500
1000
Source: Digital Audio Broadcast
Single proc.Large mem. overhead
TASK-1 TASK-2 TASK-3
En
erg
y
Execution time Execution timeExecution time
© 200158
Pareto curves allowtask trade-off decision
0 10000 20000 30000 400000
4
8
12
0 50000 1000000
5
10
15
0.0 2.0 4.0 6.00
500
1000
Source: Digital Audio Broadcast
TASK-1 TASK-2 TASK-3
En
erg
y
Execution time Execution timeExecution time
© 200159
Cavity Detection Algorithm on Intel Pentium-MMX (+execution time)
0
5
10
15
20
25
30
35
# A
cces
ses
& E
xec
Tim
e
Con
vent
iona
l
Con
v +
Ado
pt
Dat
a F
low
Trf
Loop
Trf
D r
euse
(lin
e bu
ffer)
D r
euse
(pi
xel b
uffe
r)
Inpl
ace
Mem
dat
a la
yout
Mod
ulo
red
(ado
pt)
Oth
er A
dopt
Main Memory Accesses Local Memory Accesses Execution Time (sec)
© 200160
Resource limited software
0
10
20
30
40
50
6070
80
90
100
Per
cen
tag
e (%
)
Exec Time Power Bus Load
Initial Algorithm DTSE Transformed
TRIMEDIA processor
Factor 12 bus load reduction
Factor 5 power reduction
Factor 3.5 performance increase
© 200161
512w256w128w96w64w
1
2
Cache Power
Main memory Power
032w
Cache Size[ words ]
Relativepower
Voice coder (SW cache): full power summary
Gain in power of additional factor 6 comparedto optimized (platform independent code)
© 200162
VOP memories
MPEG - 4 Motion Estimation
Resulting Power Reduction = 8
Optimizations steps
RelativePower
0.0
1.0
0.5
Total Memory Power
Search Area memories
Processor Level DTSETask Level DTSE
© 200163
Consistent Speed Up on Different Platforms for MPEG4 video decoder
Performance of PI MPEG-4 Video Decoder on Different Platforms
0.0
20.0
40.0
60.0
80.0
100.0
120.0
M & D CIF 120 kbps30 fps
Foreman CIF 450kbps 25 fps
Cal & Mob CIF 2Mbps 30 fps
Fra
mer
ate
(fra
mes
/sec
on
d)
Pentium II 350 MHz
HP PA RISC 180 MHz
TriMedia 100 MHz
© 200164
Power Reduced with Factor 21 to 48
Assesment Memory Power Reduction (Proprietory Architecture)
0.00.51.01.52.02.53.03.54.04.55.0
M & D CIF 120kbps 30 fps
Foreman CIF 450kbps 25 fps
Cal & Mob CIF 2Mbps 30 fps
Rem
ain
g P
ow
er (
%)
© 200165
Turbo coding principle
Decoder
C 2
C 1
D 2
D 1
-1
Encoder
UC Y
Û
© 200166
Original:
bit-rate: 0.07 Mbit/s power: 1.07 J/bit
latency: 5900 s area: 3.5 mm2
optimizations
bit-rate: 36 Mbit/s power: 1.85 W (0.05 J/bit)
latency: 10 s area: 15 mm2
Results
© 200168
Crisis in current (RT) design flowCrisis in current (RT) design flow
EFFORTOk?
Logic synthesis
Full spec
RTL
COST
Problems
Explore
© 200169
ObjectivesObjectives
• Drastically shorten design time (months to weeks!) raise the abstraction level
• Meet timing constraints as soon as possible expose timing bottlenecks at higher level
• Low implementation cost systematic methodology to control cost
© 200170
(Re)Using High-Level Synthesis(Re)Using High-Level Synthesis
ADOPT+HLS
Less muxes/registers using ACUs (NOT conventional High-Level Synthesis)
Conventional HLS
ACU
ACUACU
ACU
© 200171
Disabling the Disabling the time-bombtime-bomb for logic for logic synthesis synthesis
Logic synthesis
Scheduling0
40
80
120
160
Synthesis time (minutes)
HLS
ADOPT + HLS
© 200172
Exploration@High-level avoids Exploration@High-level avoids complexity explosioncomplexity explosion
(V)HDL lines (x 103)
HLS
ADOPT + HLS0
2
4
6
8
Behavior RT Gate
© 200173
Efficient use of high-level Efficient use of high-level synthesis (I): reduced costsynthesis (I): reduced cost
Gates (x 103)
0
1
2
3
4
5
6
7
HLS ADOPT + HLS
Comb.logic
Registers
Muxes
After logicsynthesis !
© 200174
Critical path
HLS ADOPT+HLS
Efficient use of high-level synthesis Efficient use of high-level synthesis (II): improved delay(II): improved delay
After logicsynthesis !
© 200175
Results for programmable Results for programmable processors: cavity detectionprocessors: cavity detection
GCC -O3
aCC +O3
Performance (seconds)
0
24681012
1416
+Adopt Initial +DTSE +DTSE +Adopt
(Glb.Trf.)
+DTSE +Adopt
(Loc.Trf.)
IMAGE: 1280x1000 pixelsHP 9000/777 256 MB RAM
© 200176
Analog-Digital Co-Design : FAST
ADC
LO Chippartitioning
LNA
Digital channelfiltering
Noise coupling in mixed-signal Ics -> tools &
methods
MCM vs. on-chip passives
Chip-package co-design -> architectures
Analog/digitalpartitioning
Mixed-signal front-end architecture
exploration -> tools
Demonstrator: 5 GHz WLAN terminal
© 200178
The Desics pipeline
D6 RESEARCH PROGRAMME
D6/ INDUSTRY TRANSFER PROJECTS
Industry product development
AlcatelNationalPhilipsEricssonIntelESA
© 200179
Strategic Research Cooperation
Wireless Local Area Network
MPEG-4
System-on-Chip Design Technology
© 200180
IMEC is part of a closed loop
‘Closed Loop’ approach:
You cannot make an economic engine running without a ‘closed belt’.
Only the right combination of ALL elements can foster a successful industrial development, based upon an increasingly knowledge based society.
Knowledge creation
State-of-the-artscience parks
Venturecapital
Entrepreneurship
Permanent training initiatives
© 200181
Conclusions
- requirements for future embedded system applications learned from IIAP’s by:
- building demonstrators
- systematic design flows and methods
- white box IP re-use
- design automation
- transfer through education & training
http://www.imec.be/ocapi
http://www.imec.be/3/3.6.html
© 200182
Ivo BolsensVice President
Hugo De ManSenior Fellow
Paul SixAssociate VP
Jean RoggenManager Strategic
Programmes
Niek Van DierdonckDST
DSP Technology Support
Annemie StasAdministration
Ivo BolsensVice President
Marc EngelsDepartment Director
Francky CatthoorSEMP
System Exloration for Memory and Power
Didi VerkestEMSYS
Embedded Systems
Jan BormansMICS
Multi-mediaImage Compression
Systems
Stėphane DonnayMIRA
Mixed Signal and RFApplications
Bert GyselinckxWISE
Wireless Systems
Serge VernaldeDBATE
Digital Broadband Terminals