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EE141EECS141 1Lecture #25
EE141-Fall 2012Digital Integrated Circuits
Lecture 25Clock Distribution
EE141EECS141 2Lecture #25
Announcements Homework #8 due tomorrow
Project phase 3 schedule Now: poster Nov. 28th, report Dec. 3rd
Proposal: poster Dec. 3rd, report Dec. 7th
Lectures next week: Tues. lecture will be “taped ahead” Thurs. lecture will be held “live” on Tues. Dec.
4th
HKN surveys will likely be held on the 4th as well
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EE141EECS141 3Lecture #25
Class Material
Last lecture Timing
Today’s lecture Clock Distribution
Reading Chapter 10
EE141EECS141 4Lecture #25
Clock Distribution
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EE141EECS141 5Lecture #25
Clock Distribution
Single clock generally used to synchronize all logic on the same chip Need to distribute clock over the entire die
While maintaining low skew/jitter
(And without burning too much power)
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Clock Distribution
What’s wrong with just routing wires to every point that needs a clock?
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EE141EECS141 7Lecture #25
H-Tree
CLK
Equal wire length/number of buffers to get to every location
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More realistic H-tree
[Restle98]
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EE141EECS141 9Lecture #25
Clock Grid
Driver
Driver
Dri
ver
Driv
er
GCLK GCLK
GCLK
GCLK
•No RC matching•But huge power
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Example: DEC Alpha 21164 (1995) 2 phase single wire clock,
distributed globally
2 distributed driver channels Reduced RC delay/skew
Improved thermal distribution
3.75nF clock load, 20W power
58 cm final driver width
Local inverters for latching
Conditional clocks in caches to reduce power
More complex race checking
Device variation
trise = 0.35ns tskew = 150ps
tcycle= 3.3ns
Clock waveform
Location of clockdriver on die
pre-driver
final drivers
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EE141EECS141 11Lecture #25
Clock Drivers
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Clock Skew in Alpha Processor
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EE141EECS141 13Lecture #25
2 Phase, with multiple conditional buffered clocks 2.8 nF clock load
40 cm final driver width
Local clocks can be gated “off” to save power
Reduced load/skew
Reduced thermal issues
Multiple clocks complicate race checking
trise = 0.35ns tskew = 50ps
tcycle= 1.67ns
EV6 (Alpha 21264) Clocking600 MHz – 0.35 micron CMOS
Global clock waveform
PLL
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21264 Clocking
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EV6 Clock Results
GCLK Skew(at Vdd/2 Crossings)
ps5101520253035404550
ps300305310315320325330335340345
GCLK Rise Times(20% to 80% Extrapolated to 0% to 100%)
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EV7 Clock Hierarchy (2002)
GCLK(CPU Core)L
2L
_C
LK
(L2
Cac
he)
L2
R_
CL
K(L
2 C
ache
)
NCLK(Mem Ctrl)
DLL
PL
L
SYSCLK
DL
L
DL
L
+ widely dispersed drivers
+ DLLs compensate static and low-frequency variation
+ divides design and verification effort
- DLL design and verification is added work
+ tailored clocks
Active Skew Management and Multiple Clock Domains
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Clock AnimationsBy Phillip Restle (IBM)http://www.research.ibm.com/people/r/restle/Animations
/DAC01top.html
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Next Lecture
Power distribution, I/O