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ECE520 – Lecture 9 Slide: 1University of New Mexico
Office: ECE Bldg. 230BOffice hours: Wednesday 2:00-3:00PM or by appointment
E-mail: [email protected]
Payman Zarkesh-Ha
ECE520 – VLSI Design
Lecture 9: Design Rules
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ECE520 – Lecture 9 Slide: 2University of New Mexico
Review of Last Lecture Interconnect Manufacturing Process
● Back-end Process (Conventional)● Back-end Process (Modern – Dual Damascene)
Interconnect Modeling● Parasitic Capacitance● Parasitic Resistance● Parasitic Inductance● Delay Estimation Techniques
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ECE520 – Lecture 9 Slide: 3University of New Mexico
Today’s Lecture Review of output resistance of an inverter
Overview of Design Rules● What are design rules?● Why have design rules?● Typical design rules
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ECE520 – Lecture 9 Slide: 4University of New Mexico
Interface between the circuit designer and process engineer
Guidelines for constructing process masks
Unit dimension: minimum feature size (transistor gate length)● scalable design rules: lambda parameter● absolute dimensions: micron rules
Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur
A complete set includes● set of layers● intra-layer: relations between objects in the same layer● inter-layer: relations between objects on different layers
What Are Design Rules?
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ECE520 – Lecture 9 Slide: 5University of New Mexico
To be able to tolerate some level of fabrication errors such as● Mask misalignment● Dust● Process parameters (e.g., lateral diffusion)● Rough surfaces
Why Have Design Rules?
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ECE520 – Lecture 9 Slide: 6University of New Mexico
Points:● N-well process p-type wafer (no p-well)● Active area determines where transistors
may go● Poly overlapping with active = transistor● Select is where n+ and p+ ion
implantation occurs; it can be used to place an opposite type region (e.g., put p+ select within n-well to create a p+ well plug, more later)
● All contacts/vias are the same size (eases processing)
● Advanced technology is more complex and has more layers (e.g. Thick Oxide, Thin Oxide, VT_high, VT_low, LI, etc.)
Layers:
N-Well
Active Area
Select (n+,p+)
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Typical CMOS Process Layers
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ECE520 – Lecture 9 Slide: 7University of New Mexico
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
RedBlue
MagentaBlack
BlackBlack
Select (p+,n+) Green
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
RedBlue
MagentaBlack
BlackBlack
Select (p+,n+) Green
CMOS Process Layers in Layout Tools
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ECE520 – Lecture 9 Slide: 8University of New Mexico
Intra-Layer Design Rule Origins Minimum dimensions (e.g., widths) of objects on each layer to
maintain that object after fab● minimum line width is set by the resolution of the patterning process
(photolithography)
Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab
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ECE520 – Lecture 9 Slide: 9University of New Mexico
Intra-Layer Design Rules
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ECE520 – Lecture 9 Slide: 10University of New Mexico
Inter-Layer Design Rule Origins Transistor rules – transistor formed by overlap of diffusion (also
called active) and poly layers
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ECE520 – Lecture 9 Slide: 11University of New Mexico
Transistor Layout We will almost always use minimum L device
1
2
5
3
Tran
sist
or
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ECE520 – Lecture 9 Slide: 12University of New Mexico
Inter-Layer Design Rule Origins
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ECE520 – Lecture 9 Slide: 13University of New Mexico
Vias and Contacts Design Rules
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ECE520 – Lecture 9 Slide: 14University of New Mexico
n+ or p+ Select Design Rules
1
3 3
2
2
2
WellSubstrate
Select3
5
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ECE520 – Lecture 9 Slide: 15University of New Mexico
A A’
np-substrate Field
Oxidep+n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A’
A A’
Example: CMOS Inverter Layout
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ECE520 – Lecture 9 Slide: 16University of New Mexico
1
3
In Out
VDD
GND
Stick diagram of inverter
CMOS Inverter Layout Sticks Diagram
Dimensionless layout entities
Only topology is important
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ECE520 – Lecture 9 Slide: 17University of New Mexico
Design Rules Note The book’s process is NOT exactly the same as the one we will
be using
In general the numbers in previous slides are not the numbers you will use, they are simply representative of what Design Rules are like