Calhoun: The NPS Institutional Archive
Theses and Dissertations Thesis Collection
2000-12-01
Design of a phase sampled interferometry antenna
using the robust symmetrical number system
York, Nathan S.
Monterey, California. Naval Postgraduate School
http://hdl.handle.net/10945/7669
RY>E SCHOOL
1943-51 •
NAVAL POSTGRADUATE SCHOOL
Monterey, California
THESIS
DESIGN OF A PHASE SAMPLED INTERFEROMETRYANTENNA USING THE ROBUST SYMMETRICAL
NUMBER SYSTEM
by
Nathan S. York
December 2000
Thesis Advisor:
Co-advisor:
Phillip E. Pace
D. Scott Davis
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1. AGENCY USE ONLY (Leave blank) 2. REPORT DATEDecember 2000
3. REPORT TYPE AND DATES COVEREDMaster's Thesis
4. TITLE AND SUBTITLEDesign of a Phase Sampled Interferometry Antenna Using the Robust Symmetrical Number System
6. AUTHOR(S)York, Nathan S.
5. FUNDING NUMBERS
7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES)Center for Joint Services Electronic Warfare
Naval Postgraduate School
Monterey, CA 93943-5000
8. PERFORMINGORGANIZATION REPORTNUMBER
9. SPONSORING / MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSORING/MONITORINGAGENCY REPORT NUMBER
11. SUPPLEMENTARY NOTES
The views expressed in this thesis are those of the author and do not reflect the official policy or position of the Department of Defense or the U.S. Government.
12a. DISTRIBUTION / AVAILABILITY STATEMENTApproved for public release; distribution unlimited.
12b. DISTRIBUTION CODEA
1 3. ABSTRACT (maximum 200 words)
This research has examined the benefits of using the Robust Symmetrical Number System (RSNS) to resolve ambiguities in phase sampling interferometry. A
compact, high resolution direction finding antenna architecture based on the RSNS was developed to demonstrate experimentally the elimination of phase errors
using a minimum amount of hardware. Previous work has determined that phase errors in the system will degrade the system performance. Several improvements
were made to the original RSNS prototype antenna to provide enhanced performance. Adding isolators and supplementing the ground plane with copper tape
(between the antenna elements), a reduction in the mutual coupling effects was accomplished. Mounting the microwave components on a brass plate also reduced
errors contributed by vibrations and temperature. Tailor cutting all semi-rigid coaxial lines also helped reduce the number of connectors required to assemble the
microwave circuit, also a source of phase errors. Matching the front-end amplifiers in each amplification stage rather than matching the characteristics of two
cascaded amplifiers in each signal line has reduced relative phase errors between channels as well as matching the power outputs of the amplifiers. Two printed
circuit boards were designed and built for the RSNS signal processor. The printed circuit boards provide a decrease in the electrical noise floor over the original
design (assembled on breadboards). The new design has reduced the phase errors that were present in the first prototype system. The RSNS signal processing
technique is able to provide a high-resolution phase sampled direction finding capability with an angular resolution of 1.9 degrees by using only three receiving
elements (two interferometers).
14. SUBJECT TERMSRobust symmetrical number system; Optimum symmetrical number system; Phase sampling interferometry; Direction finding. Ambiguity
resolution.
15. NUMBER OFPAGES144
16. PRICE CODE
17. SECURITY CLASSIFICATION OFREPORTUnclassified
18. SECURITY CLASSIFICATION OFTHIS PAGEUnclassified
19. SECURITY CLASSIFI- CATIONOF ABSTRACTUnclassified
20. LIMITATIONOF ABSTRACT
UL
N 7540-01-280-5500 Standard Form 298 (Rev. 2-89)
Prescribed by ANSI Std. 239-18
11
Approved for public release; distribution is unlimited
DESIGN OF A PHASE SAMPLED INTERFEROMETRY ANTENNA USINGTHE ROBUST SYMMETRICAL NUMBER SYSTEM
Nathan S. York
Lieutenant, United States NavyB.S., Worcester Polytechnic Institute, 1994
Submitted in partial fulfillment of the
Requirements for the degree of
MASTER OF SCIENCE IN APPLIED PHYSICS
from the
NAVAL POSTGRADUATE SCHOOLDecember 2000
ABSTRACT
RYre school
This research has examined the benefits of using the Robust Symmetrical Number
System (RSNS) to resolve ambiguities in phase sampling interferometry. A compact,
high resolution direction finding antenna architecture based on the RSNS was developed
to demonstrate experimentally the elimination of phase errors using a minimum amount
of hardware. Previous work has determined that phase errors in the system will degrade
the system performance. Several improvements were made to the original RSNS
prototype antenna to provide enhanced performance. Adding isolators and supplementing
the ground plane with copper tape (between the antenna elements), a reduction in the
mutual coupling effects was accomplished. Mounting the microwave components on a
brass plate also reduced errors contributed by vibrations and temperature. Tailor cutting
all semi-rigid coaxial lines also helped reduce the number of connectors required to
assemble the microwave circuit, also a source of phase errors. Matching the front-end
amplifiers in each amplification stage rather than matching the characteristics of two
cascaded amplifiers in each signal line has reduced relative phase errors between
channels as well as matching the power outputs of the amplifiers. Two printed circuit
boards were designed and built for the RSNS signal processor. The printed circuit boards
provide a decrease in the electrical noise floor over the original design (assembled on
breadboards). The new design has reduced the phase errors that were present in the first
prototype system. The RSNS signal processing technique is able to provide a high-
resolution phase sampled direction finding capability with an angular resolution of 1.9
degrees by using only three receiving elements (two interferometers).
VI
TABLE OF CONTENTS
I. Introduction 1
A. Direction Finding Antennas 1
B. Principal Contributions 3
C. Thesis Outline 3
II. Phase Sampled Inteferometry 5
HI. Optimum Symmetrical Number System Direction Finding Antenna 1
1
A. Optimum Symmetrical Number System 1
1
B. OSNS Prototype DF Antenna 12
C. Experimental Results 14
IV. Robust Symmetrical NUMBER System Direction Finding Antenna 19
A. Robust Symmetrical Numbering System 19
B. RSNS Prototype Antenna 22
C. Experimental Results 27
V. Improved RSNS RF System Design 35
A. Antenna Elements 36
B. Isolators , 39
C. Amplifiers 40
D. Filters 41
E. Mixers 42
F. Miscellaneous Components 44
G. Overall Design 45
VI. RSNS Signal Processing Circuit 49
A. Level and Bias Amplifier 50
B. Comparator Network 53
C. Latching the Comparator Outputs 59
D. RSNS-to-Binary Converter 61
E. Circuit Simulation 64
F. Printed Circuit Board Construction 66
vii
VII. Test and Evaluation of Prototype Hardware 71
A. Test Procedures 71
B. Results 75
Vm Conclusions 79
A. Conclusions 79
B. Future Work 83
C. Concluding Remarks 83
Appendix A. VHDL Code 85
Appendix B. MATLAB Simulation and Data Evaluation Code 95
Appendix C. Printed Circuit Board Construction 1 15
List of References 121
Initial Distribution List 123
vm
LIST OF FIGURES
Figure 2.1 Two Element Interferometry 5
Figure 2.2 Mixer Output Voltage Versus Phase Difference, d=X/2 7
Figure 2.3 Mixer Output Voltage Versus Angle of Incidence, d=A/2 7
Figure 2.4 Mixer Output Voltage Versus Angle of Arrival, d=7.5A. 8
Figure 3.1 Folding Waveforms and Integer Values within Moduli mi=5 and m2=6
for the OSNS 12
Figure 3.2 Optimum Symmetrical Number System Antenna Architecture 13
Figure 3.3 Measured Mixer Output Voltages for OSNS Array 16
Figure 3.4 Simulated Transfer Function Using the OSNS Measured Mixer Output.. 16
Figure 3.5 Measured Transfer Function of OSNS Prototype Antenna 17
Figure 4.1 Folding Waveforms and Integer Values within Moduli mi=5 and m2=6
fortheRSNS 21
Figure 4.2 Block Diagram of the Unsealed RSNS Antenna 22
Figure 4.3 RSNS Logic Block 23
Figure 4.4 Simulated Transfer Function with No Phase Errors in Either Channel .... 26
Figure 4.5 Modulus 17 Channel with 3° Phase Error Introduced 26
Figure 4.6 Modulus 17 Channel with 3° Phase Error Introduced 27
Figure 4.7 Normalized Mixer Output and Simulation Waveforms for the RSNS
Array with mi=8 29
Figure 4.8 Normalized Mixer Output and Simulation Waveforms for the RSNS
Array with m2=17 30
Figure 4.9 Measured Folding Waveform Outputs from the Shift and Bias
Amplifiers 30
Figure 4.10 Predicted RSNS Transfer Function 31
Figure 4.11 Measured RSNS Transfer Function 31
Figure 4.12 Predicted RSNS Transfer Function for Scale Factor \ = -Jill 32
Figure 4.13 Measured RSNS Transfer Function for Scale Factor £, = V3/2 33
Figure 5.1 RF Circuit Block Diagram 36
ix
Figure 5.2 Micro-strip Dipole Antenna Element 37
Figure 5.3 Stripline Antenna Array 38
Figure 5.4 Phase Difference Between Modulus and Reference Signals 38
Figure 5.5 Power MEASURED AT THE mixer Inputs 39
Figure 5.6 Power Curves for DBS Amplifiers 40
Figure 5.7 Power Curves for Avantek Amplifiers 41
Figure 5.8 Mixer Phase Response 43
Figure 5.9 Folding Waveforms from Saturated Anaren Balanced Mixer 44
Figure 5.10 Front View of RSNS Prototype 46
Figure 5.11 Bottom View of Microwave Circuit 46
Figure 5.12 Top View of Microwave Circuit 47
Figure 6.1 Block Diagram of RSNS Processor 49
Figure 6.2 Weighted Summing Amplifier 52
Figure 6.3 Inverting Amplifier 53
Figure 6.4 Comparator Schematic and Pin-out Diagram 54
Figure 6.5 Voltage Divider Circuit 57
Figure 6.6 Comparator Characteristic with Hysteresis 58
Figure 6.7 74HC273N Octal D-Type Flip-flop 60
Figure 6.8 555 Timer Circuit 61
Figure 6.9 Schematic Diagram of Mod 17 Comparator Output to EEPROM#2
Input 63
Figure 6.10 Schematic Diagram of Mod 8 Comparator to DIO Board Wiring 63
Figure 6.11 Modulus 17 Printed Circuit Board 69
Figure 6.12 Modulus 8 Printed Circuit Board 70
Figure 7.1 Anechoic Chamber Setup 72
Figure 7.2 Anechoic Chamber Control and Recording Equipment 74
Figure 7.3 Modulus 8 Normalized Mixer Output 75
Figure 7.4 Modulus 17 Normalized Mixer Output 76
Figure 7.5 Simulated RSNS Antenna Transfer Function Using Measured
Mixer Outputs 76
x
Figure 7.6 Level and Bias Amplifiers Outputs 77
Figure 7.7 RSNS Antenna Transfer Function 77
Figure 8.1 Measured Mixer Output Through Simulated RSNS Processor,
First Prototype 80
Figure 8.2 Measured Mixer Output Through Simulated RSNS Processor,
Second Prototype 81
Figure 8.3 Ideal Transfer Function 81
Figure 8.4 Measured Antenna Transfer Function 82
XI
Xll
LIST OF TABLES
Table 5.1 Isolator Specifications 39
Table 5.2 Mixer Specifications 43
Table 6.1 Voltage Divider Calculations 56
Table 6.2 Comparator Threshold Settings 59
Table 6.3: RSNS Encoding Scheme 62
Table 6.4 Bill of Materials for Modulus 8 PCB 67
Table 6.5 Bill of Materials for Modulus 17 PCB 68
xiu
XIV
LIST OF ABBREVIATIONS, ACRONYMS, AND SYMBOLS
ADC Analog to Digital Converter
AOA Angle of Arrival
BW Bin Width
di Element Spacing for Element i
d' Element Spacing for Scaled Array
a Forced Phase Difference
CAM Computer Aided Manufacturing
DC Direct Current
DF Direction Finding
DIO Digital Input-Output card
EEPROM Electrically Erasable Programmable Read Only Memory
f Frequency
FM Frequency Modulated
Broadside Phase Difference
g Discrete state of RSNS vector
gpib General Purpose Interface Bus (synonymous with HPIB)
HPIB Hewlett-Packard Interface Bus (synonymous with GPIB)
Ij Current through Voltage Divider Resistance ofj-th Comparator
IF Intermediate Frequency
k Wave NumberA,
k Bin Number
L Comparator Output Voltage
LNA Low Noise Amplifier
LPF Low Pass Filter
X Wavelength
M,M Dynamic Range for OSNS, RSNS
m,rrii Modulus
XV
N Number of Channels
n; Number of Folds
r) Normalized Phase Detector Output
OSNS Optimum Symmetrical Number System
PFrsns Fundamental Period
PRP Pairwise Relatively Prime
PSI Phase Sampled Interferometry
PCB Printed Circuit Board
<t>Wave Function of Free Space Wave
Rj Resistance
Tk Resolution of Bin k
RDF Radio Direction Finding
RSNS Robust Symmetrical Number System
S; Channel Sequence Shift Value
SNS Symmetrical Number System
Angle of Arrival
9 Reported Angle of Arrival (Output of SNS system)
0' Angle of Arrival for Scaled Array
0mm Maximum Mapable Aperture
V Voltage
V. Threshold Voltage for j-th Comparator and i-th Modulus
Vout Output of Amplifier Stage
Vthresh Comparator Threshold Voltage
VHDL VHSIC Hardware Description Language
VNA Vector Network Analyzer
£ Scale Factor
\\f Wave function at a receiving element
xvi
XV11
ACKNOWLEDGEMENTS
First of all, I would like to thank Professor Phillip Pace for allowing me to
continue work on this project. His guidance, enthusiasm and patience made this an
enjoyable experience. Next I would like to thank Professor Scott Davis, for his careful
review of this thesis and thoughtful comments. This thesis would not have progressed if
it were not for the guidance of Professor David Jenn, the Microwave Laboratory Director.
I need to also thank Don Snyder for his help with the printed circuit board manufacturing
and Bob Vitale for his efforts to help me understand the test equipment in the anechoic
chamber. To David Styer, thank you for your hard work laying the foundation on which
this thesis is built and to David Wickersham who built the first RSNS prototype antenna
and introduced me to this thesis. Finally, I need to thank my wife, Vickie, and my
children, Garrett and Margaret, for their support and understanding through this whole
period.
This research was supported in part by the Naval Postgraduate School Center for Joint
Services Electronic Warfare.
xvin
L INTRODUCTION
A. DIRECTION FINDING ANTENNAS
Direction Finding (DF) antennas are used by many people. Law enforcement,
military, wildlife managers and telecommunications personnel use DF systems for
locating and tracking different types of emitters. A wide variety of techniques are used to
accomplish the DF task. Spinning DF, time difference of arrival (TDOA), and phase
sampled interferometry are just a few examples that are commonly used. All these
systems are passive; meaning they do not generate their own signal to locate a target.
Therefore most of these systems will only return a line of bearing to a transmission.
Phase sampled interferometry is a very attractive technique since a direction of
arrival can be obtained by the phase information stored in a plane wave. Amplitude
information is not required. Within the phase sampled interferometry field of direction
finding, several new techniques have been investigated.
The ESPIRIT-based two-dimensional arrival estimation scheme achieves aperture
extension (interferometry baseline extension) using a sparse uniform rectangular array of
electromagnetic vector sensors spaced much farther apart than a half-wavelength [1]. An
electromagnetic vector sensor is composed of six spatially co-located, orthogonally
orientated, diversely polarized antennas, distinctly measuring all six electromagnetic-field
components of an incident multisource wavefield. The direction of arrival from each
incident source is estimated from the source's electromagnetic-field vector component
and serves as a course reference to remove the cyclic phase ambiguities in ESPIRITs
eigenvalues when the intervector sensor spacing exceeds a half-wavelength.
A polynomial rooting approach to super-resolution array design is concerned
with the design of an array that satisfies prespecified performance levels, such as
detection-resolution thresholds and Cramer-Rao bounds on error variance [2]. The sensor
placement problem is formulated in the framework of subspace-based DF techniques and
a novel polynomial rooting approach to the design problem, based on the new concept of
1
the "sensor locator polynomial." This polynomial is constructed using prespecified
performance levels, and its roots yield the sensor locations of the desired array. The
distinguishing feature of this technique is that it hinges on the properties of the array
manifold.
The extended phase interferometry technique [3] incorporates both calibrated
phase and amplitude response data from the antenna arrays. This technique appropriately
weights the square of the baseline phase differences with the antenna gains. The
incorporation of amplitude data provides significant performance improvement over
phase-only interferometry; however, it requires a modest increase in computational
complexity.
This thesis research improves on a phase sampling interferometer approach that
can be easily incorporated into the established techniques to provide a high-resolution,
small baseline array with fewer number of phase sampling comparators [4]. The approach
is based on preprocessing the received signal using the robust symmetrical number
system (RSNS). The RSNS preprocessing is used to decompose the spatial filtering
operation into a number of parallel sub-operations (moduli) that are of smaller
computational complexity. Each sub-operation is a separately configured interferometer
that symmetrically folds the detected phase difference with folding period equal to 2Nmj
where N is the number of interferometers that are used within the linear array. A small
comparator ladder mid-level quantizes each folded phase response. Consequently, each
sub-operation only requires a precision in accordance with that modulus. A much higher
DF spatial resolution is achieved after the N different moduli are used and the results of
these low precision sub-operations are recombined. By incorporating RSNS
preprocessing concept, the field of view of a specific configuration of interferometers and
phase sampling comparator arrangements can be analyzed exactly. Experimental results
for an improved 6-bit RSNS array are presented.
B. PRINCIPAL CONTRIBUTIONS
The focus of this thesis research has been to improve the design and performance
of a previous RSNS direction finding array. Microwave component performance was re-
evaluated and new features were introduced. A new RSNS DF system was fabricated
and tested.
Initial design efforts focused on the microwave receiver. The previous
prototype's performance was marginal. Its design injected distortions into the folding
waveforms, causing angle of arrival reporting errors. The existing component
performances were re-examined and a new design was constructed.
The previous RSNS digital processing circuit was designed and constructed
without its performance ever being validated. Computer simulations of the new circuit
were conducted to evaluate the current design. During the simulations, it was discovered
that by adding a timing circuit to clock in comparator outputs to the RSNS encoders, the
performance of the system could be improved.
The new RSNS processing circuit was laid out for construction on a printed
circuit board. The circuit board was milled on campus in the Physics department
electronics workshop.
The improved prototype was tested. Data collection was conducted by collecting
mixer output voltages and RSNS processor outputs. The measured patterns were used to
study the effects of the new design features on mutual coupling, amplifier harmonics,
temperature, vibrations and power levels.
C. THESIS OUTLINE
This thesis presents the theoretical background and design equations needed to
construct a phase sampled interferometer, as well as previous test arrays that have been
built and tested. A new array was designed to eliminate phase errors that were present in
the preceding systems.
Chapter II is a review of phase sampled interferometry and the prototype antenna
design elements. Chapter III introduces the Optimum Symmetrical Number System
(OSNS), taken from the work of Thomas Hatziathanasiou [4]. It presents the design of a
DF system based on the OSNS. Chapter IV, taken from the work of David Wickersham
[5], gives an overview of previous work done with the Robust Symmetrical Numbering
Systems and its application in DF antenna systems. Chapter V presents my design data
for the antenna and RF receiver components. Chapter VI is a detailed description of my
RSNS signal processing design. Chapter VII is an explanation of the testing procedures
for the antenna and a presentation of the experimental results. Chapter VIQ gives some
concluding remarks and summarizes the next step that is needed.
II. PHASE SAMPLED INTEFEROMETRY
A two-element linear interferometer is shown in Figure 2.1. The two antenna
elements are spaced a distance d apart and the incident plane wave arrives with bearing
angle 6 B [5]. In this phase monopulse configuration the angle B is measured from the
perpendicular to the baseline axis and can take on values 7i/2 > B > -n/2 . The phase
difference between the two elements is
A\|/ = \j/, -y 2=— dsin(G B ) (2.1)
where d is the element spacing and X is the wavelength, and is a function of the incidence
angle of the wave.
INCIDENTWAVEFRONT
LPF
'out
SIGNALPROCESSOR
1AOA,
e
Element 1
Phase detector
Figure 2. 1 : Two Element Interferometry.
5
The signals received by the antenna elements are mixed (multiplied together and
lowpass filtered) resulting in an output signal whose frequency is the difference of the
two input signal frequencies. Because the signals have the same frequency, the mixer
output voltage is a value proportional to the difference between signal phases \|/, and
\j/ 2. This difference is not purely Ay because of the time delays due to the different
transmission line lengths, 4>i, from each antenna element. However, these line lengths are
known and can be compensated for in the angle estimate. Let the signals from the two
antenna elements be
v,(t) = Vcos[27rft + (()1(t)] (2.2)
and
v 2 (t)= Vcos[2flft + <|>2 (t)], (2.3)
where V is the maximum value of the voltage at the antenna elements, t is time and f is
frequency. Let \|/ be the phase difference between the transmission lines to the two
elements. The lowpass mixer output voltage is
V 2 V 2
=— cos(A(|>) =— cos27td . .. ,— sin(8 B ) + \K (2.4)
which contains the plane wave angle of arrival (AOA) information. For values of
d = X/2 and \|/ =0, A<J> = 7tsin(9 B ). As the AOA 6B varies from -7t/2 to n/2, the
phase difference A(J> varies from -n to n as shown in Figure 2.2. The output voltage
from the phase detector is also a function of the phase difference and is a symmetrical
folding periodic waveform. Together these relationships give the phase detector output
voltage as a symmetrical function of the AOA as shown in Figure 2.3 for d = XI 2 [6].
6
100
COoCD
c3)CD
"cc>
CO
o
D)c<
-100
Phase difference (degrees)
200
Figure 2.2: Mixer Output Voltage Versus Phase Difference, d= A 12 [from 6].
300
-100 -80 -60 -40 -20 20 40Angle of incidence (degrees)
80 100
Figure 2.3: Mixer Output Voltage Versus Angle of Incidence, d= X 12 [from 6].
Ambiguities are generated for baselines where d>A,/2. That is, the phase
detector output voltage is highly ambiguous with a single phase corresponding to many
angles of arrival. The number of folding periods n that occur within an AOA of 7t radians
is
n =2d
X(2.5)
For example, with d = 1.5X , n=15 folds are available as shown in Figure 2.4. The folding
period is not constant but grows larger in proportion to the angle off of broadside because
of the sin(9 B ) dependence in (2.4).
300
200.
o>£CDcn<d
o>OQ
-200.
-300-20 C) 20 40
Angle of arrival (degrees)
TOO
Figure 2.4: Mixer Output Voltage Versus Angle of Arrival for d = 7.5A, [from 6].
The ambiguities within the symmetrical folding waveforms represent the phase difference
between the elements and can be resolved by using additional interferometers in the
linear array. Typically, each interferometer in the linear array symmetrically folds the
phase response with the folding period between interferometers being a successive factor
of two, or d 4=2d
3=4d
2=8d,, where dk represents the element spacing. High-speed
binary comparators are used to produce a digital output. The folding waveforms are
shifted appropriately using a phase shifter in each channel to achieve a Gray code result.
The folded output from each phase detector is then quantized with a single comparator
with a normalized threshold level T=0.5. Together, the comparator outputs directly
encode the signal's AOA in the Gray code format. This approach makes use of the
periodic dependence of the interferometer's phase response on the applied plane wave's
AOA and the distance between the elements of each interferometer. One of the major
8
limitations associated with this approach is the achievable resolution. For the folding
periods to be a successive factor of 2, the distance between the elements must also be
doubled. That is, an 8-bit DF antenna using the previous scheme would require element
spacings A,/4,X/2,^.,2X,4A....,32A, with a total baseline length of 32X. This distance-
doubling of the element spacings requires complex analog hardware, adversely affects the
physical implementation of the DF architecture and ultimately constrains the achievable
resolution.
THIS PAGE INTENTIONALLY LEFT BLANK
10
III. OPTIMUM SYMMETRICAL NUMBER SYSTEM DIRECTION
FINDING ANTENNA
A. OPTIMUM SYMMETRICAL NUMBER SYSTEM
Chapter HI summarizes Thomas Hatziathanasiou's work in symmetrical number
systems [4]. The optimum symmetrical number system (OSNS) is composed of a
number of pairwise relatively prime (PRP) moduli mi
. The integers within each OSNS
modulus are representative of a symmetrically folded waveform with the period of the
waveform equal to twice the modulus, i.e., 2mj . For m given, the integer values within
twice the modulus are given by the row vector [6, 7]
x m = [04,---,m-l,m-l, •••,1,0] form=mj i=l, 2, ... (3.1)
Figure 3.1 shows part of the OSNS folding waveforms and the integer values within the
modulus for mi=5 and m2=6. The horizontal axis represents the normalized input. The
vertical lines represent folding waveform reference levels. The numbers at the top of the
figure represent the number of reference levels that are crossed by the folding waveform
for a given input value. The period of one complete fold is equal to 2mj = 10 and
2m 2=12.
11
T= 1
T = 2
T = 3
T = 4
T= 1
t = :
T = 3
T = 4
T = 5
«
1234432 100 12- M =
3 4
30
4 321001 2344321 1 1
s s Sl\
//
1 2 3 4 5 5 4 3 2 1 1 2 3 5 5 4 4 3 2 1 1 2 3 4 5 5 4 3•—
'
y •N y - ..-' s' \ / \ /
/ \ '-
r
^ S s s -•—«
—
/'
m, =5
I 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 3.1: Folding Waveforms and Integer Values Within Moduli m, = 5 and m : = 6 for
the OSNS [from 5].
Due to the presence of ambiguities, the integers within the vector derived by equation
(3.1) do not form a complete system of length 2m by themselves. The ambiguities that
arise within the modulus are resolved by considering the paired values from all channels
together. If N pairwise relatively prime moduli are used, the dynamic range (the number
of unambiguous vectors) of this scheme is
M=nm,
(3.2)
i=l
This dynamic range is also the position of the first repetitive moduli vector. As shown in
Figure 3.1, the dynamic range for the m, = 5 and m2= 6 case is M=30. That is, no set
appears twice for a normalized input in the range (0,29) [6, 7].
B. OSNS PROTOTYPE DF ANTENNA
Figure 3.2 shows the schematic diagram of a N=2 channel OSNS DF antenna.
The array consists of three elements, with all channels sharing a common element. With
12
the proper distances between elements, each interferometer folds the phase response at
2m;. The phase response from each channel is quantized using m;-l comparators. The
integers shown in Figure 3.1 represent the number of comparators ON due to the phase
voltage exceeding the comparator matching threshold voltage.
~T~X~ {"!\ ' V"V"V '"V*
Power
Sp litter
4-Bit
Thermometer
to
Graycode
Encoder
M =] Jm
l
= 66
_,MA
a. =
3 -Bit
Thermometer
to
Graycode
Encoder
OSNSto
Decimal
Algorithm
Am. 6 t
Figure 3.2: Optimum Symmetrical Number System Antenna Architecture [from 4, 8].
The distance between each pair of elements is a function of the modulus, m;. The phase
response must have the correct number of folds to cover the dynamic range. For a given
modulus mj, the number of folds within the dynamic range is
n ; =M/2m ; (3.3)
13
Since each fold of the array corresponds to a change in phase of n for d = X/2, the
required spacing between the reference element and the respective element of channel i is
given by [5]
X MXd
;
=n— =' 2 4m
:
(3.4)
The bin widths are uniform in size in sin(0 B ) space with a width 2/M. Therefore, the
spatial resolution is given by
rk=arcsm
(„ 2k-M + 2 ^
M/
- arcsin2k -MM (3.4)
where k€ {0,1,- -M-l} and k=0 is the bin that starts at B =-7t/2. The variable^ is a
scale factor that can be used to compress the encoded field of view symmetrically about
broadside. The phase waveforms are not ideal over 180 degrees because of the element
pattern degradation at wide angles. Since the waveforms at wide angles are not usable,
the SNS can be remapped to the usable portion of the waveform to increase resolution.
The scale factor is defined to be
- _ d sin(0)
d7 ~
since')
'
(3.5)
where corresponds to phase angle for the unsealed configuration, and 0' is the desired
phase angle for the compressed configuration. Note that the spatial resolution is not
uniform over the range of -nil to nil. The resolution is finer than r at broadside (0 = 0°)
and increases with angle off broadside, because of the sin(0 B ) dependence in (2.4).
C. EXPERIMENTAL RESULTS
14
A linear array based on the moduli mi = 6 and iri2 = 1 1 was designed, fabricated
and tested at a frequency 8.5 GHz [4, 6]. The radiating elements are open-ended
waveguides as shown in Figure 3.2. For moduli mi = 6 and n\2 = 11, di=3.82 in and
d2=2.08 in. With M=66, the number of folding periods is ni=5.5 and n 2=3. To provide an
adequate signal-to-noise ratio, a low-noise amplifier is included at the output of each
interferometer element. Since the common element splits the signal into N paths, an
attenuator is placed in the other branches to balance the amplitudes. The amplifiers
operate in saturation so that the mixer input signal levels are independent of the angle of
incidence. A fixed phase shifter is also included in one branch of each interferometer so
that the symmetrically folded phase response waveforms from each mixer may be
aligned. This alignment insures that the comparators in the digital processor properly
sample the phase waveform and encode it in the OSNS.
The anechoic chamber facility at the Naval Postgraduate School was used for the
antenna pattern measurements for each pair of elements. The measured mixer outputs are
shown in Figure 3.3 [4, 8]. Since the array is not useful in the endfire regions, the phase
response from each channel was minimized at an input AOA of -50°. This is the point
where the digital code starts. The locations of the voltage minima are controlled by
introducing the appropriate phase shifts to the signals at a point between the elements and
the mixer. A simulation of the transfer function for the OSNS array is shown in Figure
3.4 for £ = 1 . The measured transfer function (output of digital hardware) is shown in
Figure 3.5 [4, 8].
15
Figure 3.3: Measured Mixer Output Voltages for OSNS Array [from 4, 8].
Simulation60
40
—
-
O
^-40
w-60
-80
!I
1
1
1
1
1
1
1
ril
j|4j.-i
jT^Wl
j^i
i
50 50
Angle of Arrival (degrees)
Figure 3. 4: Simulated Transfer Function Using the OSNS Measured Mixer Output
[from 4, 8].
16
60
40
|20
oS
31-20
^»0
n
...r.
i
! 1 1 1 i i
INIn i
;
nrr 1
K
i
J
:
;J
;
U '
!
1
1
Is-
11
i
i I
30 -to -30 -20 -10 10
Angle of Arrival (degrees)
20 30 40 50
Figure 3. 5: Measured Transfer Function of OSNS Prototype Antenna [from 4, 8].
The spikes in the transfer function are AOA encoding errors. The phase waveforms must
cross the comparator thresholds (code transitions) at the same time for all channels. The
OSNS can present a problem at each of these specific AOAs. When some comparators, at
positions of change, do change, while others do not, the recovered amplitude will have a
large error. Encoding errors can also occur due to imperfections in the transmission line
phases. These errors however, can be isolated with additional comparators and corrected
using interpolation circuits as described in [6]. An alternate approach, however, is to
develop a symmetrical number system that eliminates the possibility of this type of
encoding error. That is, a symmetrical number system is needed where only one
comparator threshold is crossed at any one particular code transition.
17
THIS PAGE INTENTIONALLY LEFT BLANK
18
IV. ROBUST SYMMETRICAL NUMBER SYSTEM
DIRECTION FINDING ANTENNA
A. ROBUST SYMMETRICAL NUMBERING SYSTEM
Chapter IV summarizes David Wickersham's work in symmetrical number
systems [5]. In the RSNS, N different periodic symmetrical waveforms are used with
pairwise relatively prime integers mi, m2, ..., mN . The RSNS is based on the following
sequence
x^ = [0, 1, 2, •••, m-1, m, m-1, •••, 2, l], (4.1)
where x^ is a row vector and m is a positive integer (m > 0) [9]. In an N-channel
thRSNS, where N > 2, the basic sequence for the i channel (modulus m) is
x^ = [0, 0, •, 0, 0, 1, 1, .... 1, 1, •-,m, m,--,m, m, •••, 1, !,•••, 1, l]. (4.2)
In this sequence each value in the x^ row vector is put N times in succession. This
sequence is repeated in both directions, forming a periodic sequence with the period
Prsns = 2mN. (4.3)
Considering a single channel, the discrete states of the robust symmetrical number system
can be expressed as [9]
n-S:L
, S; <n < Nm;+ s, +1
Ng = i :„ J
.(4-4)
2Nmj +N-n + s;
-1
N, Nm
s
+ Sj + 2 < n < 2Nmj + S; -
1
19
where g is the n* term of channel i, nij is the channel modulus, Sj is a corresponding
sequence shift Sj = 0, 1, 2,..., N-l (mod N) and N > 2 is the number of channels in the
system. The values {si, S2,..., Sn} must form a complete residue system modulo N.
Because of the relative property of the shifts, one of the shift values will be set equal to 0.
The index n corresponds to the input value. The discrete states of the RSNS are indexed
using the s;
= row vector with the index starting from the first zero. Note that the
largest integer within each periodic sequence is the modulus m.
An N-channel RSNS is formed of vectors by picking N moduli mj, and N shift
values Sj, 1 < i < N. Since the fundamental period for channel i is 2Nm;, it follows that
the period for the RSNS vectors must be a multiple of 2Nnv Therefore the fundamental
period for the RSNS is [9]
PFrsns = [2m,N, 2m2N,..., 2mNN], (4.5)
where [ai, a2 , ..., a^ is the least common multiple of ai, a2 , ..., aN. From number theory
PFrsns = 2N[mi,m2,...,mN]. (4.6)
To illustrate the RSNS, Figure 4.1 shows the folding waveform and integer values within
each modulus for mi=5 (shift Si=0) m2=6 (shift s2=l). Note the Gray-code properties
from one code transition to the next. The thresholds shown on the vertical axis represent
the integer values within each RSNS modulus. The integer values occur N=2 times in
succession.
20
T =S
T=4
T = 3
T : I
T=6T=5
M =27
2 1 1112 2 3 3 4 4 5 5 4 4 3 3 2 112 2 3 3 4 4 5 5 4
—-"=;
\s^
1 1 1 2 2 3 3 4 4 5 5 6 6 5 5 4 4 3 3 2 2 1 1 1 1 2 2 3 3
1 vX s-^
^^
m, = 5
S, =
m 2 = 6
s 2 = 1
I : 3 4 5 t 1 G S 10 II 13 13 14 IS 16 II IB 19 30 31 31 33 34 3S 3b 37 3B 39 3D 31 33
Figure 4.1 : Folding Waveforms and Integer Values Within Moduli m, = 5 and m:= 6 for
the RSNS.
The system dynamic range (m^^) of the RSNS is the maximum number of
distinct vectors without a redundancy. The selection of the shift and the permutations
among the 2 moduli has no effect on M RSNS . However, the point indices corresponding
to M RSNS (beginning point and ending point) are different. When the channel moduli are
of the form m, =2 k - 1, m 2=2 k ,m
3=2 k
+ 1 , the closed-form expression for M RSNS is
conjectured to be
\/i 3 t 15M rsns =— m- +— m, +7 (4.7)
where mi > 3 [9]. For two channels, with the moduli separated by 3 or more.
M RSNS =4m, +2m2-2. (4.8)
Checking against computer results when mi=8 and m2=17, M = 64, which fits (4.8). It
can be verified that M RSNS = 27 < M = 30 (3.2) for the two channel example shown in
Figure 4.1.
21
B. RSNS PROTOTYPE ANTENNA
To demonstrate the efficiency of the RSNS preprocessing, the design of a 6-bit
antenna using mi = 8 and m2 = 17 is considered [5]. A schematic diagram of the RSNS
antenna is shown in Figure 4.2 for shifts of si=0, S2=l resolution bins.
Power
Splitter
Comparators
Figure 4.2: Block Diagram of the Unsealed RSNS Antenna [from 5].
The number of folds within each modulus is
B
n. =M M
Prsns 2m,
N(4.9)
or n i=2 and n2=0.94. The required distance between antenna elements is
22
X MXd- =n. — =
' 2 4m,N£(4.10)
With a scale factor of £, = V3/2 , di=1.70 in and d2=0.80 in. For a normalized folding
waveform amplitude (-1 to 1), the threshold for the jth comparator for the modulus m*
channel is [5]
Vj,m, =C0d
( 1 ^m
. -J + T-%
m,(4.11)
The input signal is applied in parallel to both interferometers. The output from each phase
detecting mixer is amplitude analyzed using mi comparators. For this design, there are a
total of 25 comparators with a maximum of 17 loaded in parallel. An RSNS-to-binary
logic block translates the RSNS residues (number of comparators ON in each
thermometer code) to a more convenient representation. The logic block and
corresponding bin number are shown in Figure 4.3.
23
Vector Mod 8 Mod 17 Bin Vector Mod8 Mod 17 Bin Vector Mod 8 Mod 17 Bin
1 o « ipl .-46: "jgfgSj ~, f$3(j$$ipap - a }£^pgs
2 1"
IIIHIS
^.-47'y fe^ ^v^85-S : -
'
2\.\
- ' \- | :;-47
1
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4
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1
2
2
1
1
2
V.-16- >
16
15J
•17-5
69 |
vS70.;
'; i
..0 s ^48«-
6 3 2s ^g: | ESpl! j^p; E >-»? •..-.72-:
;
: W- 1
7 3 3 ^.*l%r1^1 7."15-§f
| 14 ~y:';-14---"
;\4&7
J'
:: "24-^
1v73j-
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;v:74- |': -7^-:H
in | x. 2*Jr52
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i'^'j*^^Ǥ &i-53-
v -3.' -
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--54
8
9
4
4
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10 5 4;
-433. jgipj jj 43 ::?22f4 - 26-.. W&M11
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fe:5 :
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13 6 6:
14 7 6
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•49*. •r-*.'.; :. ip -;-
ll$28§. J
,-'82 1 7 •
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8 50- ':-!-":, fv-ic^.'-- ;k.29-I p*^^ 7 i^I^l'j 62-.
18 7 8 |l|§£: ,7 J&,:-.--' ri30j;.' i2;:%^i^Ml Sija&yi g^63?|
19 7 9 P&^H \ f& 1.
I-&X
'
:
>M-i 85 6 8
20 6 9
I £4 :'
5 :
.•8 ""7
._* .
:
•'-32 :^
r":33^v
I 34. '-
86
87
5
5
8
9
-^22?^:
v^O,> .->-.o-_.-
,1- ; 88 4 9
ilil 't'5,J • JM | ' ''2 ^3 7^56--.;:
-4-.
7 :| pes 89 4 10
\24" ^457-7 •v4- v,
-.3:.
.6;:7
; 6 : ^fpfl 90
91
3 10
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,'28,;-.-
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1 337-"'.
"' :3;3,3 |
i" 2 '£
i o.>
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333 |ISfetl*$$&. -
15-
, '16
18 -
-1
:?'-.:
: 10: |
I 59- :
;;7£%
61
'.-•65' ;
.73"-.':
7.2--
:.-;2 ''
4• O; |1 i;
1:
5- -J
7/5;.$- :4../.>
-•4-:- :-3
' i 1/^^2 ; |
-' v2^
i.38.r;
1^40;"
§ 45'''
92 2 11
93' "2
12
94 "1
"12 "
95 1 13"
96'
6"13
96
97
98
1
1
14
14
15
Figure 4.3: RSNS Logic Block [from 5].
A consequence of quantizing the angle of arrival into a bin is that the RSNS
system reports any signal that falls within a bin as if it arrived at the bin center, Gk
. That
is to say, for one angle within each bin, the estimation is exact, but for the remaining
angles a reporting error exists. The AOA resolution or bin width in 9-space for the kth
bin is
rk = arcsin2k -M + 2
M- arcsin
2k-M^M
(4.12)
24
Another advantage of the RSNS is that small phase errors can be tolerated without
a serious error to a reported AOA. These phase errors cause the folded waveform from
the mixer to shift, thus changing the timing of the comparator state changes. Because the
waveforms from the mixers are quantized, the bin width or rk provides some free-play in
the antenna circuitry and limits AOA reporting errors to the adjacent quantization levels
(bins). However, there is a limit to this feature. If the phase error becomes too great, the
comparators will not change state in the correct sequence, which may or may not
correspond to a code that is mapped in the dynamic range. These errors are similar to the
errors that the OSNS experiences when the comparators of both channels do not change
state at the same time. For the system designed, a theoretical phase error of 6° can be
tolerated in the modulus 17 channel and a phase error of 12° in the modulus 8 channel.
Figures 4.4, 4.5 and 4.6 show the simulated transfer function. Figure 4.4 is the transfer
function with no phase error in both channels. Figures 4.5 and 4.6 are the modulus 8
channel with zero degrees of phase error and 3° and 6° phase error in the modulus 17
channel. Note how the transfer function becomes jagged and erratic as the phase error is
increased until it becomes discontinuous at 6°.
25
so
60
£ 40
20
< -20
1-40
a.
-60
-80
• ». L -jJ-1 i L 1 J
1 "r^^ r T ' ' r T 1
' _-_._i_____._l . _ _ .__j__-._._i_.._...i.....-_i---.-.j.-_
-80 -60 -40 -20 20 40
Angle of Arrival (degrees)
60 80
Figure 4.4: Simulated Transfer Function with No Phase Errors in Either Channel
[from 5].
80
60
£ 40
75 20
< -20D
E.-40
a.
-60
-80
1 r r i -i -fj£-~• r r * "
i— ""
----:i- i-
\....y^cC....\ .4 \ \—
> *... L__ yJZ _ . I. » L 1. -J
1 -f=r-
i t T (__.-.-- r r -____- n ___
U_L . I L J I ___.. L......A.......J..—
-80 -60 -40 -20 20 40
Angle of Arrival (degrees)
60 80
Figure 4.5: Modulus 17 Channel with 3° Phase Error Introduced [from 5].
26
CD
£
oCLa>
80
60
40
20
-20
-40
-60
-80
•1 1 -I 1 ]
11 1
I. [.....in
!
i
'
i : i i
r"71
"
.....ir.... :
.
i ; i im \
1i j j—i ,
..L..JKJ j L [ !... j
L
....
J
.
....
J
—
1
i i i i ! 1 ! !
-80 -60 -40 -20 20 40 60
Angle of Arrival (degrees)
80
Figure 4.6: Modulus 17 Channel with 6° Phase Error Introduced [from 5].
C. EXPERIMENTAL RESULTS
A RSNS array based on the moduli mi = 8 and m2 = 17 was designed, fabricated
and tested at a frequency of 8.0 GHz [5]. The schematic diagram of the two-channel
array is shown in Figure 4.2. The radiating elements are printed circuit dipoles. For
moduli mi = 8 and iri2 = 17, the unsealed distances, \ = 1 , are di=1.48 in. and d2=0.70 in.
With M = 64 , the number of folding periods m=2 and n2=0.94. To provide an adequate
signal-to-noise ratio, a low-noise amplifier is included at the output of each
interferometer element. Also included in the RSNS array is a lowpass filter in each
channel to eliminate the amplifier harmonics that are present. Since the common element
splits the signal into N paths, an attenuator is placed in the other branches to balance the
amplitudes. A fixed phase shifter is also included in one branch of each interferometer so
that the symmetrically folded phase response waveforms from each mixer may be
aligned. This alignment insures that the comparators in the digital processor properly
27
sample the phase waveform and encode it in the RSNS. For the mi = 8 channel, 8
comparators are required. For the n\2 = 17 channel 17 comparators are required. The
EEPROM that was used accommodates 15 inputs. The modulus 17 channel processing is
conducted in two stages. In the first stage, the 4-bit thermometer to binary encoder maps
the 15 least significant codes out of the 17 comparators (ones with the smallest
threshold). The remaining two comparators are mapped on the second EEPROM along
with the 4 bit binary encoder output and all modulus 8 comparators. The digital processor
puts out a bin number k corresponding to the estimated AOA 6 . The estimated AOA for
bin Ic is given as
k =sin-'(^-O. (4.13)
Broadside incidence for the RSNS antenna corresponds to the transition between Bins 31
and 32. For the modulus 17 channel at slightly negative angles (bin 31), the ninth
comparator is ON and for slightly positive angles (bin 32), the ninth comparator is OFF.
That is, the phase value at 6 B = corresponds exactly to the threshold of the ninth
comparator. From (4.11) the phase corresponding to the threshold value V179 is 7t/2.
This is the phase value required for the modulus 17 channel at B =0and is obtained
using the phase adjuster shown in Figure 8. In the modulus 8 channel, 9 B =0 occurs
midway between comparator 7 and 6 thresholds. Since V87 =cos-1
(f^) and
^8.6= cos ~'
(if). me required phase value is^f- = 7 and is also obtained using the modulus
8 phase adjuster.
The normalized mixer folding waveform outputs are shown with the simulated
waveforms in Figures 4.7 for the mi=8 channel and 4.8 for m2=17 channel for£ = 1.0.
The basic features correspond to predicted curves. The measured folding outputs from
the shift and bias amplifiers in both channels are shown in Figure 4.9. The digital circuit
maps the phase difference at the mixer output into an estimated angle of arrival. The
predicted output of the unsealed prototype array is reproduced as Figure 4.10. The
28
measured mixer output contains phase errors, which result in differences between the
simulated and predicted data. These phase errors cause the thermometer code to
incorrectly map the incident wave to the proper angle of arrival. The measured transfer
function of the unsealed prototype antenna is shown in Figure 4.1 1.
-20 20
Angle of Arrival
Figure 4.7: Normalized Mixer Output and Simulation Waveforms for RSNS Array with
m,=8 [from 5].
29
-40 -20 20 40
Angle of Arrival (degrees)
Figure 4.8: Normalized Mixer Output and Simulation Waveforms for RSNS Array with
m,=17 [from 5].
-80 -60 -40 -20 20 40 60 80
Angle of Arrival (degrees)
Figure 4.9: Measured Folding Waveform Outputs from the Shift and Bias Amplifiers
[from 5].
30
80
60 -
40
5 20 -
o -
< -20 -
ro -40Q.<B
DC
-60
-80
-80 -60 -40 -20 20 40 60
Angle of Arrival (degrees)
80
Figure 4.10: Predicted RSNS Transfer Function [from 5].
80 -
60
o 40
« 20
<D
« -20E
-40
-60
-80
v: r| r
.
L,
/'!-
n
y| :
--
111i-
nr^lfl'
II-
\
|
-80 -60 -40 -20 20 40
Angle of Arrival (degrees)
60 80
Figure 4.11: Measured RSNS Transfer Function [from 5].
The large discontinuities in the transfer function are due to phase and amplitude
errors, which arise from several sources. Mutual coupling is a common cause of phase
31
front distortion in small arrays of closely spaced elements. In order to increase the
distance between elements and thus reduce the mutual coupling, a scale factor E, can be
introduced. The scale factor is the ratio of the element spacings of the scaled and
unsealed arrays. Reducing the scale factor narrows the mapable field of view of the
antenna and increases the resolution within the mapable field of view. For a scale factor
of ^ = V3/2, the maximum mapable aperture (0mm) is 60°. The predicted transfer
function for the scaled array is shown in Figure 4.12. The corresponding measured
transfer function is reproduced as Figure 4.13. The mixer outputs contain significant
phase errors, and the increased resolution of the antenna limits the ability to process the
errors. The steeper slope of the scaled transfer function is clearly visible when
comparing 4.10 and 4.12.
80
60
2 40at
X3
7S 20
i •
£ -20
"O<D
o -40
-60
-80 -
-80 -60 -40 -20 20 40
Angle of Arrival (degrees)
60 80
Figure 4. 12: Predicted RSNS Transfer Function for Scale Factor % = V3 / 2 [from 5].
32
-40 -20 20 40
Angle of Arrival (degrees)
60 80
Figure 4.13: Measured RSNS Transfer Function for Scale Factor % = V3/2 [from 5].
The transfer function for the scaled array of dipoles does not show any significant
improvement due to the reduction of mutual coupling. To verify this, a second array
comprised of open-ended waveguide elements was constructed and tested. These
waveguide elements have significantly less H-plane mutual coupling than the dipoles, but
the transfer function showed no improvement over with printed circuit (dipole) elements.
This indicates that mutual coupling is not the primary cause of the phase errors. The
microwave circuit has three likely sources of errors: (1) the low noise amplifiers, (2)
coaxial cables and phase adjusters, and (3) the rigid connectors. The prototype uses two
cascaded LNAs operating in saturation in each channel. Harmonics generated by the first
amplifier are amplified by the second amplifier. The second amplifier also introduces its
own harmonics. Filters were used to suppress harmonics.
The coaxial cables and phase adjusters are another source of error within microwave
circuits. The rigid coaxial cables are coarsely trimmed at 8.0 GHz, and the phase shifters
are used for fine trimming. The cable lengths are long and subject to thermal expansion
and contraction, particularly in the vicinity of the amplifiers. Finally, all of the devices in
33
the circuit are joined with SMA type connectors. The circuit was repeatedly assembled
and disassembled for troubleshooting, and consequently the quality of the connections
were degraded. Phase errors of ± 2° can easily be introduced at each connection. Thus it
appears that many small errors accumulate in a manner such that the 6° and 12° error
thresholds are exceeded, which results in a degraded transfer function.
34
V. IMPROVED RSNS RF SYSTEM DESIGN
Previous research has introduced the Optimal Symmetrical Number System and
the Robust Symmetrical Number System and shown that they are able to efficiently
resolve ambiguities in phase sampling interferometry. The prototype arrays that were
built, however, both showed that significant errors are introduced due to the nature of the
components and construction of the system. Non-linear components, poor connections
and mutual coupling are prime contributors to the phase errors present in the folding
waveforms. This thesis research takes a step forward to validate the RSNS design and to
eliminate the phase errors in the system.
The RF circuit shown in Figure 5.1 receives a transmitted signal with a set of
micro-strip antennas (see Figure 4.2). The signal is passed through a set of isolators and
then to the first amplification stage. Band-pass filters are used to remove harmonics and
the signal is then sent to the second amplification stage. Low-pass filters are used to
remove harmonics from the second stage amplifiers. A power splitter is used to divide
the reference signal that is passed on to the RF side of the balanced mixers. The signals
from each channel are passed through phase shifters and then to the local oscillator (LO)
side of the mixers. Since the frequency at the RF and LO inputs are the same, the mixer
output is a DC value that is a function of the AOA. This DC function is referred to as the
folding waveform that is amplitude analyzed by the RSNS signal processor in order to
determine the AOA.
35
8Ghz Signal
Ground Plane
Stripline Antennas
Modulus 17 Channel
^--{25—v^-®- Totfcpljl
Ccai;b
9^—0—
i1
Power
SplitterLPF
Modulus 8 Channel
^ x
Figure 5.1: RF Circuit Block Diagram.
A. ANTENNA ELEMENTS
The open-ended waveguide antennas that were used in the OSNS design are too
wide to be used in the RSNS array. Since the element spacing for the RSNS array is
small, micro-strip antennas were developed to replace the open-ended waveguide
antennas. The stripline antennas are half-wave dipoles designed to resonate at 8.0 GHz.
A schematic diagram of a micro-strip dipole antenna is shown in Figure 5.2. The width
of each element is only 60 mils. The elements are placed into a linear array with the
spacings set at 0.80" between the reference and modulus 17 elements and 1.70" between
the reference and the modulus 8 elements as shown in Figure 5.3. These spacings were
chosen over the original design spacings of 0.70" and 1.48", since the folding waveform
36
becomes distorted at angles greater than 60° from broadside. By compressing the RSNS
dynamic range into the reduced field of view a higher angular resolution is obtained. An
additional benefit of the increased spacing is that any possible mutual coupling effect is
decreased. Antenna pattern measurements were taken of this array one element at a time;
both phase and power were recorded. Figures 5.4 and 5.5 show the results respectively.
H 0.60 in
\GROUND PLANE
EDGE
DIELECTRICSUBSTRATE
MICROSTRJPTRANSMISSIONLINE (TOP SIDEOF SUBSTRATE)
DIPOLE ARMS
GROUND PLANE(BOTTOM SIDEOF SUBSTRATE)
CONNECTOR
Figure 5.2: Micro-strip Dipole Antenna Element [from 5].
37
60 mils
SUBSTRATE
Figure 5.3: Stripline Antenna Array [from 5].
<D
iri
ooS4)Oc0)
a>
gam
Phase Difference Seen at Mixer
250
200
-200
-250
Angle of Arrival (deg)
>100
Mod 17 Channel
Mod 8 Channel
Figure 5.4: Phase Difference Between Modulus and Reference Signals.
38
ECO
33,
i_
o5oQ.
-100
Power Supplied to Mixers
15
44t5-
4+"T3^
13
42t€-
12
11.5
44-
10.5
40-
-50 50
Angle of Arrival (cleg)
100
Mod 8 Line
Ref Line
Mod 17 line
Figure 5.5: Power Measured at the Mixer Inputs.
B. ISOLATORS
M2 Global S70124 isolators were used to further reduce mutual coupling effects.
They are placed between the antenna elements and the first amplification stage. The
specifications for the isolators are shown in Table 5.1.
Frequency
Range
(GHz)
Isolation
(dB) Minimum
Insertion
Loss
(dB) Maximum
VSWRMaximum
Temperature
Range (°C)
Connector
Available
Package
Size (in)
7.0-12.4 20 0.5 1.25 -20 to +60 SMA .75 x .90 x .50
Table 5.1: Isolator Specifications.
After testing the isolators on the network analyzer they were found to meet all the
specifications that were supplied.
39
C. AMPLIFIERS
The system was first designed with only one stage of amplifiers. The one
amplifier design was introduced to try and eliminate sources of phase errors that were
present in the first prototype. The DBS DWT 18636 amplifiers were used. The goal of
the amplification stage is to gain a constant power output to send to the mixers since any
mismatch in power at the mixer inputs will produce phase errors. These microwave
amplifiers have two operating regions: linear and saturation. The preferred region for
this system is the saturated region. By operating in saturation, the output power of the
amplifiers is independent of the input power. Figure 5.6 shows the power curves for the
DBS amplifiers.
30 i
~ 20 -
E
§. 10
8 °
1 -10"6
o°- -20 -
-30
Power In vs. Power Out
)
——Power Out - Ref
Power Out - 8
Power Out- 17-40 -20 (
Power In (dBm)
Figure 5.6: Power Curves for DBS Amplifiers.
In order for the system to work well the input power needs to be at least -15 dBm. The
initial transmitter distance was 19 feet. The input power for the amplifiers at this distance
was not enough to drive the amplifiers into saturation. A stand was constructed to move
the transmitter closer to the antenna elements. However, even with the transmitter at 6'
from the elements, the power input to the amplifiers was only -17 dBm. This level was
barely enough to saturate the amplifiers, so a two-stage amplifier design was utilized.
The DBS amplifiers are used in the second stage of amplification because the
power output levels are well matched and the three were phase matched to within 10°.
40
The first stage amplifiers were chosen based on their power curves. The two primary
considerations were maximum gain and how well the power curves matched. Figure 5.7
shows the power curves for the three Avantek amplifiers that were chosen.
Power In vs. Power Out
? 25
mS 20
fl6HOa> 10
oa 5
SA-84 SN:FO3105
SA-84 SN:FO0553
SWL87 SN:F01342
-40 -30 -20 -10
Power Input (dBm)
Figure 5.7: Power Curves for Avantek Amplifiers.
Phase matching for this amplification stage is not as important as the second
stage. The purpose for the first stage is to drive the second stage amplifiers into
saturation. The gain for these amplifiers is approximately 40 dB in the linear region,
which is more than enough to saturate the second stage amplifiers at a received power of
-50 dBm. The overall effect of the two stages is that the signal output from the second
amplification stage remains a constant regardless of the received power by the antenna
elements.
D. FILTERS
The amplifiers used in this system produce harmonics. The harmonic levels are
20 dB lower than the fundamental, but introduce phase errors in the system in excess of
20°. In order to eliminate these errors, filters are used after each stage of amplification.
AIRTRON band-pass filters, with a pass band of 4-8 GHz, are used after the first stage
amplifiers and MICROLAB/FXR LA-90N low-pass filters are used after the second stage
41
amplifiers. Each filter has an attenuation of 55 dB or greater in the stopband, which
effectively eliminates all signals except the fundamental.
E. MIXERS
A mixer is a common microwave component that is used to convert a higher RF
into an intermediate frequency (IF). Typically, the RF signal is combined with a second
signal, referred to as the local oscillator (LO), at a non-linear diode. The resulting IF is
approximated by (% = (% - (0i [10]. The (% + o>io and other product terms that are
generated in the mixer are removed by filtering. For the RSNS antenna, the mixers are
used as phase detectors. The RF and LO inputs are the same frequency, therefore, the IF
output is a DC value.
IF = A, cos[(w10- co
rf > -(<J> te
- <{> rf )]+ A, cos[(coIO+ co
rf > -((f> l0
-(J) rf )]
+ [higher frequency terms]
.
Since (O^ = colo ,
(5.1)
IF = A, cos(<(>rf-
(|> l0 )+ A 2cos(2u)t)+ (higher frequency terms). (5.2)
With proper filtering the 2u)t and higher frequency terms can be eliminated. The
remaining DC term depends solely on the phase difference (<j> rf-
(j)lo ),
IF = AIcos(())
rf-(|)
10 ). (5.3)
Two mixers were considered for this system, the Mini-Circuits ZMX-10G mixer
and the Anaren 70540 balanced mixer. Table 5.3 lists the specifications for each mixer.
42
ModelFrequency EF Frequency Conversion Loss LO-RF Isolation
GHz MHz dBMax dBMin
Mini-Circuits 3.7-10.0 DC-2000 8.5 20.0
Anaren 5.2-10.4 DC- 1100 7.5 6.0
Table 5.2: Mixer Specifications.
For this application, the important specification is the IF frequency range. By having the
range set below 2w it effectively filters the output of the mixer.
The next important parameter that needs to be examined is the phase response of
the mixer. Figure 5.8 shows the phase response of both mixers when connected to the
network analyzer.
Mixer Output Voltage
>E
3a3oa>x
200
-200
-250
•Anaren Balanced
Mixer
Mini-Circuits Mixer
Phase Difference
Figure 5.8: Mixer Phase Response.
By comparing the curves, the Anaren balanced mixer was chosen since the Anaren
mixer's response has a more symmetrical shape about the 0° axis and has its maximum
and minimum values at ± 90°. Also noticeable is a DC offset of approximately -40 mV.
This offset can be compensated in the level and bias circuits at the input of the signal
processing circuit. One drawback that was discovered during testing is the Anaren mixer
43
has a low saturation level. Figure 5.9 shows the first set of folding waveforms with the
power level to the inputs at 14 dBm.
Mixer Output Voltage
0.6
-0.6
Modulus 8
• Modulus 17
Angle of Arrival (deg)
Figure 5.9: Folding Waveforms from Saturated Mixers.
The maximum and minimum regions of the folding waveforms appear to be broadened,
indicating that the mixer is saturated. Attenuators were added at the mixer inputs until
the regions regained their predicted shape.
F. MISCELLANEOUS COMPONENTS
The phase difference between the reference signal and the channel signal is the
basis for AOA estimations. The phase difference at broadside defines the relationship of
the folding waveforms. In order to set the phase angles in each of the channels, the
lengths of the semi-rigid coaxial cable were precisely cut. Because predicting how the
phase of the signal is affected by the amplifiers and other components is difficult, phase
adjusters were added. The phase adjusters are variable length coaxial cables that contain
no dielectric medium. At 8.0 GHz, one turn of the barrel will change the phase of the
signal by 5° giving the phase adjuster a range of approximately 60°.
Attenuators are also added to each signal line. The purpose of the first set of
attenuators is to balance the power between the reference signal and the modulus signal at
44
the output of the second amplification stage. A second set of attenuators is added to
reduce the power input to the mixers, since the 20 dBm output of the second stage
amplifiers saturates the mixers, causing phase errors.
G. OVERALL DESIGN
The system is assembled on a 1/4" brass plate measuring 13 in. by 13in. The
plate serves two purposes. The first is structural: by attaching the components to the
plate any vibrational errors that might be introduced are eliminated. The second function
of the brass plate is as a heat sink. The amplifiers will operate at a high temperature,
which may introduce phase errors into the system. The brass plate keeps the entire
system at a constant temperature that is only slightly above room temperature, thus
minimizing errors. All coaxial cables are cut to length. These custom fit lines minimize
bends in the cables and the number of connectors that are needed to assemble the system.
Figures 5.10 through 5.12 show the front, bottom, and top of the antenna system.
45
Figure 5.10: Front View of RSNS Antenna.
Figure 5.1 1: Bottom View of RSNS Antenna.
46
Figure 5.12: Top View of RSNS Antenna.
47
THIS PAGE INTENTIONALLY LEFT BLANK
48
VI. RSNS SIGNAL PROCESSING CIRCUIT
The second half of the DF system is the RSNS signal processing circuit. This
circuit is responsible for converting the folding waveforms into angles of arrival. The
circuit consists of 4 basic parts: level and bias amplifiers, comparator network, RSNS-to-
binary converters and the timing circuit. Figure 6.1 is a block diagram of the entire
circuit.
Modulus 8
Analog Input
Modulus 17
Analog Input
oa<Bc
OOOroo
Figure 6.1: Block Diagram of RSNS Processor.
The circuit gets its input from the balanced mixers and the folding waveform is
sent through the level and bias amplifiers. This part of the system converts the folding
waveforms (phase response from each channel) from a ±320 millivolt signal to a 1 to 13
volt signal. The signal is then sent to a comparator network. The comparator network
operates like a thermometer, the higher the voltage of the signal, the more comparators
that are turned on. The next portion of the system to receive the signal is the timing
49
circuit. This circuit is responsible for latching the comparator outputs to the EEPROMS
to perform the RSNS-to-binary conversion. The conversion is simply a matter of
comparing the number of comparators that are turned on in each of the channels with the
RSNS code, generating a binary number between and 63 that corresponds to an angle of
arrival.
The improvements made to the first prototype signal processing design include
the addition of a timing circuit to latch the signal inputs to the EEPROMs (RSNS-to-
binary converter) and constructing the preprocessing circuit on a printed circuit board
(PCB). These modifications were added to increase the reliability of the system.
A. LEVEL AND BIAS AMPLIFIER
In order for the comparator network to function efficiently the ± 320 millivolt
signal needs to be conditioned. The first item to consider is that the signal takes on both
positive and negative values. This changing polarity of the signal requires that the
comparators have multiple power sources. To avoid multiple power sources a 7.0 volt
bias is introduced. The second item to consider is that the range of the signal is only 640
millivolts. For this case, the comparator voltage references would require very tight
tolerances and very accurate comparators. This problem is alleviated by amplifying the
signal so that its range is now 12 volts centered about a 7 volt bias.
A weighted summing amplifier with an inverter is used to condition the signal.
Figure 6.2 is a diagram of the weighted summing amplifier. The amplifier is a National
Instruments LM-741CN Operational Amplifier. This amplifier has two inputs: the mixer
output (Mod Signal) and V2 that acts as a bias voltage. R2 determines the amount of bias
V 2 provides. R\ determines the influence generated by the mixer input. R3 sets the gain.
The equation that governs the amplifier operation is the summing amplifier gain
equation:
50
V0Bt=-R
3
v,.v,
VR,
+R
(6.1)
With an +18 volt source, V2 is 18 volts and R3 is set to 10k£2. The two remaining
resistance values are determined by matching the mixer output maximum and minimum
values to the desired outputs of 1-13 volts. The negative sign on the right side of
Equation (6.1) indicates that this is an inverting amplifier. The mixer output has a DC
bias of -40 millivolts; however, when a 7 volt bias is introduced it becomes insignificant
and is ignored. A phase detector output of zero maps to the middle of the shift and bias
band: -7 volts. When Vi=0, (6.1) reduces to
V 18VR 2 =-R 3
—^- = -10k£ = 25.1kQ.V„... - 7V
(6.2)
The value of Ri is determined from the maximum value of the mixer output. For the
modulus 8 and 17 channels, the maximum mixer output is measured as 320 millivolts and
the output is -13 volts. R\ is determined as follows:
a,-.-v, -0.320V -0.320V
V.+
R, R
(-13V 18V > -600nA= 533Q (6.3)
iok& :
Here R\ is a 1 kQ variable resistor set to 533 Q and R2 is a 24 k£2 resistor in series with
a 1.6 kQ resistor.
51
Mixer Output
v, ^wR
R2
Schematic
Vout
18V
GND—
v2
-A/W-1
R
GND—
|
-18 V-
LM741CN
NC
+18 V
NC
Pin-Out
Figure 6.2: Weighted Summing Amplifier [from 5].
The output of the weighted summing amplifier must be inverted before
transmission to the comparators. The inverter shown in Figure 6.3 performs this. No
amplification is required in the inverting stage because the gain of the summing amplifier
is correct . The equation that governs the output of an inverting amplifier is
V =-out
R,V, (6.4)
To obtain unity gain with inversion, Ri=R2, 20kQ resistors are used. The output of the
inverter is +1 to +13 volts as desired. This signal is provided to the comparator network
to determine the level of each signal [5].
52
Summing AmpOutput
Schematic
Vout
18 V
Summing AmpOutput
Pin-Out
Figure 6. 3: Inverting Amplifier [from 5].
B. COMPARATOR NETWORK
The comparator networks have 8 and 17 comparators in parallel. The circuit for
each comparator is shown in Figure 6.4.
53
Comparator Circuits18V
Shift and Bias
OutputV
out Schematic
R4
+18V_AW
GND
—
Shift and Bias
Output
Pin-Out-18 V
LM311N
+5V+18 V
— NC
— NC
^Ar^
-H-
Figure 6.4: Comparator Schematic and Pin-out Diagram.
The shift and bias circuit output is the input to the non-inverting terminal. The second
input is a reference voltage generated in the voltage divider network shown in Figure 6.5.
Since the 18-volt power supply is available as the power supply for the comparator, it is
used as the source for the voltage divider. The thresholds for the comparators, as
explained in the previous section, range from 1 to 13 volts, so the conversion from the
normalized thresholds to the actual thresholds is Vact
= 6Vnorm+ 7 . The normalized and
actual threshold values are shown in columns two and three of Table 6.1. Applying
Ohm's law between the source and inverting terminal of the comparator, Equation 6.4
shows the relationship between I2 and R4 :
18V- Vt _ x ° Y Y
thresholdl-> —
R<(6.4)
54
The comparators (National Semiconductor LM311N) have a maximum input bias and
offset current of 100 nA. This current is I2 in Figure 6.5. In order to limit the input offset
and bias currents to less than 1% of the current in the voltage divider, the total resistance
of the network must not exceed 1.5M& . However, the resistance values must be large
enough such that the current required by the system remains small. For these reasons, R4
is chosen to be 100k Q. . The total current for the voltage dividers is 27.5mA as shown in
the lower left corner of Table 6.1. Kirchhoff s Current Law applied at the node above R2
yields I = I , -I2
The only variables that remain are R5 and Rf,. Ohm's law across these
resistors dictates:
R 4 +R 5=^L. (6.5)
As an initial value, R5 is chosen to be 5% of R6. Once initial values are determined,
standard resistor values are chosen and R5 is made a variable resistor. The voltage
divider sub-circuit is complete and provides a precise threshold voltage to the inverting
terminal of the comparator [5].
55
Simulation Thresholds Given R4=100k and 12=100 nAMod 8 Channel Resistance Values
Normalized Comparator R4 R5 Use Var Res R6 Jse Resistor
11= -0.98079 1.11528 811 1 OOOE+05 812 314723 1K 813 6294 455 56Kt2= -0.83147 201116 821 1 0O0E+O5 822 5.994E+02 1K 823 1 199E+04 12K
13= -0.55557 3 66655 831 1 000E+O5 832 1.219E+03 5K 833 2.438E+04 22K
t4= -019509 5.82943 841 1 OOOE+05 842 2.283E+03 2K 843 4.565E+04 47Kt5= 019509 8 17052 851 1 OOOE+05 852 3962E+03 10K 853 79245.061 75K
t6= 0.55557 10.33341 861 1 OOOE+05 862 6427E+03 20K 863 1.285E+05 120K
t7= 083147 11 98881 871 1 OOOE+05 872 9.513E+03 20K 873 1.903E+O5 180K
t8= 098079 1288471 881 1 OOOE+05 882 1.202E+O4 50K 883 2404E+O5 220K
Mod 17 Channel
11 = -0.99573 102559 711 1 .OOOE+05 712 2.879E+02 1K 713 5.758E+03 5.6K
12= -0 96183 1.22905 721 1 OOOE+05 722 3492E+02 1K 723 6.984E+03 68Kt3= -0 89516 1 62902 731 1 OOOE+05 732 4.741 E+02 2K 733 9.483E+03 91K14= -0 79802 2 21190 741 1 OOOE+05 742 6676E+02 5K 743 1 335E+04 12K
t5= -0.67370 295782 751 1 OOOE+05 752 9370E+O2 5K 753 1.874E+04 18K
t6= -0.52643 3 84141 761 1 OOOE+05 762 1.293E+03 10K 763 2.586E+04 22K17= -0.36124 483255 771 1 OOOE+05 772 1 749E+03 10K 773 3498E+04 33K18= -0 18375 5 89750 781 1 OOOE+05 782 2.322E+03 5K 783 4645E+04 47K19= 0.00000 7 00000 791 1 OO0E+O5 792 3033E+O3 10K 793 6066E+O4 56Kt10= 018375 8 10250 7A1 1 0O0E+O5 7A2 3.902E+O3 10K 7A3 7.804E+O4 75K111 = 036124 9 16745 7B1 1 OOOE+05 7B2 4948E+03 5K 7B3 9896E+04 100K
112= 0.52643 1015859 7C1 1 OOOE+05 7C2 6.177E+03 20K 7C3 1 235E+05 120K
113= 067370 1104217 7D1 1 OOOE+05 7D2 7.568E+03 20K 7D3 1.514E+05 150K114= 079802 11 78810 7E1 1 OO0E+O5 7E2 9.051E+O3 20K 7E3 1 810E+05 150K
115= 0.89516 12 37098 7F1 1.OOOE+05 7F2 1 048E+O4 50K 7F3 2.097E+05 200K
116= 0.96183 1277095 7G1 1 000E+O5 7G2 1 165E+04 50K 7G3 2.330E+O5 300K117= 099573 12 97441 7H1 1 OOOE+05 7H2 1.232E+04 50*- 7H3 2464E+05 300K
Current Values Input Bias Current 1 OOE-07
11 12 13
811 1 688E-04 812 1 OOE-07 813 1.687E-04
821 1 599E-04 822 1 OOE-07 823 1.598E-04
831 1.433E-04 832 1 OOE-07 833 1.432E-04
841 1.217E-04 842 1 OOE-07 843 1.216E-04
851 9 829E-05 852 1 OOE-07 853 9.819E-05
861 7667E-05 862 1 OOE-07 863 7.657E-05
871 B.011E-05 872 1 OOE-07 873 6.001 E-05
881 5 115E-05 882 1 OOE-07 883 5.105E-05
711 1 697E-04 712 1 OOE-07 713 1.696E-04
721 1 677E-04 722 1 OOE-07 723 1 676E-04
731 1 637E-04 732 1 OOE-07 733 1.636E-04
741 1.579E-04 742 1 OOE-07 743 1 578E-04
751 1 504E-04 752 1 OOE-07 753 1.503E-04
761 1 416E-04 762 1 OOE-07 763 1 415E-04
771 1.317E-04 772 1 OOE-07 773 1.316E-04
781 1.210E-04 782 1 OOE-07 783 1.209E-04
791 1 100E-04 792 1 OOE-07 793 1 099E-04
7A1 9898E-05 7A2 1 OOE-07 7A3 9.888E-05
7B1 8.833E-05 7B2 1 OOE-07 7B3 8.823E-05
7C1 7 841E-05 7C2 1 OOE-07 7C3 7.831 E-05
7D1 6958E-05 7D2 1 OOE-07 7D3 6.948E-05
7E1 6.212E-05 7E2 1 OOE-07 7E3 6.202E-05
7F1 5.629E-05 7F2 1 OOE-07 7F3 5.619E-05
7G1 5229E-05 7G2 1 OOE-07 7G3 5.219E-05
7H1 5026E-05 7H2 1 OOE-07 7H3 5016E-05
A=10
B=11
C=12
D=13
E=14
F=15
G=16H=17
Table 6. 1 : Voltage Divider Calculations.
56
+isv —AAAa-
Figure 6.5: Voltage Divider Circuit [from 5].
To improve the comparator's performance a Schmitt trigger is added. R7 is
introduced to add hysteresis to the comparator characteristics. This gives the comparator
two threshold values: Vtl and Vth- Figure 6.6 shows the transfer characteristic of the
comparator circuit. V^sti is set by the voltage divider and L is the comparator output
signal. Vtl and Vjh can be found by equations
V = V -Lv TL vthresh ^<
R 4 +R 5+R
6
R4(R
5+R
6 )
R7
(6.6)
and
V = V -Lv TH vthresh -
R 4 +R 5+R
(
R 4 (R 5+R
6 )
R7
(6.7)
The power supply of the LM311 comparator sets the output signal, L=VCc, in this case
the L+ = 1 8 volts and L. = - 1 8 volts.
57
V.
VTL
tluesh
'TH
Vsignal
Hysteresis
Figure 6.6: Comparator Characteristic with Hysteresis.
A small capacitor, C, is added across the feedback resistor to ensure fast transitions and
to prevent multiple pulses as the signal passes though the threshold voltages. The value
of 10 MQ is selected for R4 and 100 pF for C [11, 12]. Table 6.2 lists the threshold
values for each comparator.
58
L= 18 V R7 = 10M
Comparator Vn Vth
1.11528 1.11528 1 11528
201116 2.01116 201116
3 65655 3.66655 366655
5 82943 5.82943 582943
8 17052 8 17052 8 17052
10 33341 10.33341 10.33341
11 98881 11 98881 11.98881
1288471 12 88471 12.88471
102559 1.02559 1 .02559
122905 1.22905 1.22905
162902 1 62902 1.62902
221190 221190 2.21190
2 95782 2.95782 295782
384141 3.84141 3.84141
4.83255 4.83255 483255
589750 5.89750 5.89750
700000 700000 7.00000
810250 8.10250 810250
9 16745 9 16745 9 16745
10 15859 10 15859 10.15859
11.04217 11 04217 11.04217
11 78810 11 78810 11.78810
12.37098 12 37098 12.37098
12 77095 1277095 12 77095
12 97441 12 97441 12 97441
Table 6.2: Comparator Threshold Settings.
When the shift and bias signal is larger than Vth, the comparator is ON and
remains on until the signal falls below Vtl. In ON state, no current is accepted at the
output, so the 5 volt signal above the output resistor has no voltage drop. The 5 volts is
impressed on the output. This voltage is passed to the input of the latch. If the reference
voltage exceeds the shift and bias signal, the comparator is OFF. In this state, the output
sinks current, and the 5 volts are dropped across the output resistor. The output of the
comparator is shorted to ground through the opamp and passed to the input of the latch.
C. LATCHING THE COMPARATOR OUTPUTS
A D flip-flop is added to the prototype design to latch the data to the EEPROMs.
A set of latches is placed on the inputs for each of the two EEPROMs. A total of 39
latches are required for the design. Six 74HC273N octal D type flip-flops are used as
latches. Figure 6.7 shows the pinout for the 74HC273 chips.
59
CLR ^r^ Vcc
— IQ 8Q
— ID 8D
— 2D 7D
— 2Q 7Q
3Q 6Q
— 3D 6D
— 4D 5D
4Q 5Q
GND CLK
Figure 6.7: 74HC273N Octal D-type Flip-flop.
The Vcc and CLR pins are set to 5 volts, D pins are the inputs, Q pins are the outputs and
the CLK pin receives a signal from a 555 astable multivibrator. This pinout simply stores
the input value on the D pin for one clock cycle. By latching the value for one clock
cycle the inputs to the EEPROMs are stabilized.
The clock signal is generated by 555 timer circuit shown in Figure 6.8. RA , Rb,
and C control the period and duty cycle. The design equations governing this circuit are
and
Period = 0.69C(R A +2R B )
Duty Cycle =R A +2R B
(6.8)
(6.9)
To select a clock signal of 1 kHz and a duty cycle of 50%, RA , Rb, and C are set to 1.3
k£2, 6.2 k£2, and 100 nF respectively [12].
60
+5V
8 A
RA ,
7555
Timer
3 ,
5IC
RB 2
.
2
C -1
TTL output
GND— ^ — Vcc
Trigger
LM555CNDischarge
Output— Threshold
Reset— Control Voltage
Figure 6.8: 555 Timer Circuit.
D. RSNS-TO-BINARY CONVERTER
The 25 comparator states must be processed into a 6-bit angle of arrival. The
EEPROM performs this mapping function. An ATMEL Model AT28C256 is used. The
EEPROM is a small logic block that converts 15 input bits to an 8-bit output via its
internal programming. Because of the 15 input limit, two EEPROM are used to process
all 25 comparators. The 'Thermometer Code" programmed into the EEPROM is shown
in Table 6.3. The thermometer code is the string of instructions for the EEPROM that
maps input to output. With two EEPROMs, the thermometer code has two stages as
shown on the circuit diagrams of Figure 6.9 and Figure 6.10.
61
RSNS Encod.'ng Scheme
XJCOR#!:10 LSE ofMod17Chanr e! XICOR ?2:7 VISE ofMod 17 Charni e!
Bin
Channel
17
C-!ann-w Kpts
XKOR21Hex .npul
XICOR #1 XICOR SI
hex Oia
XSCCRS1rip „-.
XJCOF#2 x;cos<-2
Output
XC0RS2HexCuX1CCR#2
C 10
1011
655
000 0011 1111 1111
000 0011 1111 1111
000 011* 1111 1111
03FF
03FF
07FF10
11
A
D000 0111 110C101C000 0111 11GC1C11
OFCA07CAC7ce
C
2
00
01
C2
4
5
11
1212
443
000 0111 1111 1111
0001111 1111 1111
0001111 1111 1111
07FF
OFFFOFFF
11
1212
BCc
000 0011 11001011
000 0011 110C1100OOC 0001 11001100
03CB03CC01cc
3
4S
0304
05S
7
s
131314
2
001 1111 1111 1111
001 "111 1111 1111
011 111* 1111 1111
1FFF
1FFF3FFF
1314
DD
3CC0001 11001101
300 COOC HOC 11 01
3CC COOC HOC 1110
C1CCoocc00CE
6
e
CS
07
089
10
11
14
1515
1
1
011 1111 111111111111111 1111 1111
1111111 11111111
3FFF
7FFF
7FFF
14
1515
Ec
F
000 0000 01OC 1110
000 0000 0100 1111
OOC 0000 OOO0 1111
004E004FOOOF
91011
09
OAOB
12
13
14
15
1517
c
1
1
111 1111 1111 1*11
111 1111 1111 1111
111111111111111
7FFF
TFFr
7FF?
-s
15
15\,
3CC OOOO OOC 1111
0000000 0101 1111
OOC COOC 0111 '111
CC1F
CCSF
0C7F
12
1314
OC
XCE
15'
16
17
17
1816
223
111 1111 1111 1111
111 1111 1111 1111
111 1111 1111 1111
7FFF
7FFF
7FFF
1515
15
00000001111 1111
000 00001101 1111
000 0001 1101 1111
OOFFOODf01 Df
15
16
17
OF
1011
IS
3D
15
1514
3 111 1111 1111 1111
111 1111 1111 1111
011 1111 1111 1*11
7FFF
7FFF
3FFF
15
15-4
r 300 0001 HOC 1111
300 0011 110C111130C001* 110C111C
01 CFC3CF
18
1S
2C
1
3
1
4
21
2223
141313
556
011 1111 11111111001 1111 1111 1111
001 1111 11111111
3FFF
1FFF
1FFF
14
13
13DD
0000111 11001110000 0111 110011010001111 110C1101
07CE07CDOFCO
21
22
23
-
fs—
1617
24
25
26
272829
12
1211
6
700C111* 1111 1111
0001111 1111 1111
30CC11" 1111 1111
OFFF
OFFF
OTF^
12
12
C
cE
3001111 11X11XMl 1111 HOC HOC
OFCC1FCC1FCE
24
25
26
18
19"A
11
10
10
8
87
000 0111 1111 1111
000 0011 1111 1111
000 0011 11111111
07FF
03FF
03FF
11
1010
6AA
011 1111 11X1011011 1111 110C1010001 1111 110C1010
3FC83FCA1FCA
—-27
-
2829
1B1C1D
3C
31
3334
35
9
9
766
00CC001 1111 1111
30CC001 1111 1111
00CC0OC1111 1111
01 FF
01 FF
OOFF
9
9
8
S
s
30CH11 11001000
1FC9OFCSOFCS
3C
31
32 2Q~"8 ~
7
7
554
000 00001111 1111
000 0000 0111111100C 0000 01 11 1111
3OCO0OCC011 1111
DOC 0000 0011 1111
30COOOCC001 1*11
OOFF
007F
007F
7
7
87
7
OOC 0111 11001000000 0111 1100 0111
000 0011 110C0111
07C807C703C7
3334
35
21
2223
3637
38
3940
41
5
8S
33
003F
003F
001F
66
S 5
OOC 0011 HOC 0110
300 000- HOC 0110
30COOO- HOC 0101
03C631 CS01 cs00C5OOC*0044
36
37
38
394041
24
25
25
27 "
2829
' 54
4
221
00G 0000 0001 1111
000 0000 00001111000 0000 0000 1111
00C000CC00C011130C0O00C00CC111OOCOOOCCQOCOO-1000 0000 0000 0011
000 0000 0000 0001
000 0000 0000 0001
30C 0000 COX 0000
00C 000C COOC 000030C COOC COOC 0001
000 0000 0000 0001
000 0000 0000 0011
OOC 0000 0000 0011
001F
OOOF
OOOf
54
4
54
000 00001 IOC 01 01
OOC 0000 1100 01 0000000000100 0100
424344
3
1
c
0007
0007
0003
3
2
3
3
2
000 0000 0100 0011
OOC 0000 OOOC 001
1
000 OOOC OOOC 0C1C
000 0000 0100 0010
OOC OOOC 01 00 0001
000 00001100 0001
X4300030002
42
4344
2A262C
454647
2
1
1
1
1
2
00030001
0001
21
1
21
1
00420041
00C1
45
4647
202£
, 2F '
48
49
50 1
2
3
3
OOOC
OOOC
0001
C
C
1
C OOC 30X1 IX OOOCXCOOOl 11X0OXOOC 0001 11X0001WO 0011 11X00010X0011 11X00100X0111 11X0010OOC 01 11 11X00110X1111 11X00110001111 11000100001 1111 11X01XXI 1111 11X0101011 111111X0101
ooco01 CO01 CI
48
49
5C
3C
31
32
51
52
S354
55
56
1
22
44
5
0001
0003
0003
1
I
1
22
C3C1
03C207C2
51
52S3
33"
34
35
3
4
S6
6
OOC COOC COOC C1 11
OOC COOC COOC C1 11
OOC COOC COOC 1111
0007
0007
OOOF
3
4
3
4
C7C3"0FC33FC4
54
55
se
35
37
38
57
58
59
4
55
7
78
OOC 0000 0000 11 11
000000000011111OOC 0000 0001 1111
OOC COOC 0011 1111
OOC 0000 0011 1111
ooc oooo cm 1111
CO0CCO0C111 1111
OOOF001F
001F
4
S
4
5S
1FC41FC53FCS
5758SS
"39""
3A36
SC
SI
52
S
s
8
7
0C3F
0C3F
007F
s
6
5
6
7
XI 1111 11X011CXI 1111 11X0*11
3FC61FC61FC7
SC
S1
S2
30
3D3=
53 6 007F 7 7 3X1111 11X0111 0FC7 S3 ''
"3F "
Table 6.3: RSNS Encoding Scheme [from 5].
62
IHKOM- ATVIX AT28C256
C7-1S-
C7-13-
C7.8-
C7-7-
C7-6-
C7-S-
C7-4-
C7-3-
C7.2-
C7-1-
I All
2- A12
3 A?
4 A£
1 A5
& A4
7: A3
8: A3
». AI
10 AC
u voa-ia
I2WI
U102
14:01©
Vcr 28
WI 27
A13
AS X,
A9 *
All 3D
a 22
A10 J
cr 20
»ic it
roe ;ie
»5 17
roi te
»3 is
— »5V
— »SV
— C7-14
— C7<
C7-10
— C7J2
GHD
— C711
GND
CKD-
C8-7-
C8-2-
CB-1-
C7-K-
C7-17-
DICM7-
dkms-
CKD-
UPROlt ATim. AT28C2M
1 A14 Va if — »sv
1 A12 IT 27 — «SV
3 A7 AI3 j-. — CM
4 U. A8 ii — C8-3
3 AS A9 94 — CS-4
6 A* All Zl — CM
7 A3 cr a — qh>
8 A2 am 21 1— cs-s
9 Al (3 2C — GHD
10 AD mX7 .19
u roo-ui not 18
I2V01 »5 17 — HO-37
13:1*32 ITO4 16 — no-39
14 CXE IC3 LS — no-4i
Figure 6.9: Schematic Diagram of Mod 17 Comparator Output to EEPROM#2 Input.
EEFROM. A7MEL AT28C2S64C CfflrtjOT:
30GND — 1 A14 Vcc 28 — *5V
C8-7
—
2: A12 H 27 — »5V49
C8-2
—
3 A? Ali a —CM48
47C8-1— 4 A6 AS 25 — C8-3
C7-17— 5 A5 AS 24 — C8>4
46
45C7-16
—
6 A4 All 2} i—CM
Q-15— 7 A3 OE 22 — GHD— 44
3 A2 A10 21 — CXJ43
D-13
—
n-12— * ai a 20 — GHD— 42
10 AD nlC7 1$
41
ii —11 ICO-ub HOC 18
— 40
12U01 I»J 17
13L02 l«Ot 16
39
- 36
GND — 14 GND 1/03 15
37
36
35
34
33
32
2
«ID
Figure 6.10: Schematic Diagram of Mod 8 Comparator to DIO Board Wiring.
63
The first stage encodes the 15 least significant (lowest threshold) comparators of
the modulus 17 channel into a 4-bit representation (thermometer-to-binary conversion).
The first column of Table 6.2 is the reported angle bin. The second column is the number
of comparators active in the modulus 17 channel in each bin. The fourth column is a
binary representation of the state of the input pins for the first EEPROM, and the fifth
column is the hexadecimal representation of that binary number. The sixth column is the
decimal output desired from EEPROM #1 for the given input; it is the decimal number of
number of active comparators. The seventh column is the hexadecimal representation of
that digital number. The result is that the number of active comparators is converted to a
4-bit number. The shift and bias circuit and comparators for Modulus 17 and EEPROM
#1 are physically located on the same circuit board. The output of EEPROM #1 and
comparators 16 and 17 must be passed to EEPROM #2 on the second circuit board.
Figure 6.9 illustrates how this signal is passed to EEPROM #2 [5].
E. CIRCUIT SIMULATION
A schematic capture and simulation software package is used to test and validate
the entire circuit design. Multisim ™ from Electronic Workbench was chosen because it
is powerful, easy to learn and use. No knowledge of SPICE or other simulation language
is needed to conduct basic simulations. The only knowledge that is necessary is basic
circuitry design. The interface is graphical and very intuitive.
Validation for each of the parts of the RSNS processor is done by selecting all the
individual resistors, capacitors, integrated circuits, power supplies, and connecting the
correct pins together. The program allows the user to add various measuring equipment
to the circuit to monitor performance. Items such as oscilloscopes and voltmeters are
64
very useful to verify and tweak the initial design. The built-in function generator was
used to provide the mixer output signal and each of the EEPROM inputs was monitored
to ensure that the comparator network operated properly.
A simulation of the complete system was not completed. The difficulty arose
from the EEPROM. No standard SPICE model exists for EEPROMs, so a model needed
to be created. Included in Multisim™ is a component creator that allows the user to
generate their own unique components. This ability is limited to basic components such
as diodes and opamps. In order to create a model for the EEPROMs a VHSIC Hardware
Description Language (VHDL) add-on package is required. This language allows a
programmer to model all levels of circuit design. It supports behavioral description of
hardware from the digital system level to the gate level. The language is able to take a
black-box approach to designing a system since all that is required in input/output
information. This makes the language technology independent and extremely flexible.
Three approaches were considered to simulate the behavior of the EEPROM. The
first method is the easiest conceptually and most direct method. The truth table is entered
into the VHDL code as a constant [13]. For smaller truth tables this method gives the
programmer direct control of all input and output bits. For this system, there are 15 input
bits that need to be accounted for thus requiring a truth table that has 215
lines. The
second method uses a programmable logic array (PLA) instead of truth tables. The table
is replaced with an AND array that realizes selected product terms of the input variables
and an OR array that operates on the product terms to form an output. This approach
eliminates the need to include every possible input combination, thus reducing the
number of lines of code. The drawback to this method though is that equations need to
be developed and entered into Karnaugh maps, and a separate VHDL library file needs to
be created to use this method. The third approach is the Case Model [14]. This approach
is usually used to realize a multiplexer, however, it can be manipulated to simulate the
operation of a ROM. The case statement allows the programmer to directly read the
input bits and convert them into an output. This is similar to programming in a truth table
except that only the required lines from the table are included instead of all the lines.
Appendix A is the code developed to simulate the EEPROM.
65
Once the VHDL code was developed, it can be imported to Multisim™ and
attached to a component. The component can then be added to the circuit for simulation.
When the EEPROM components were added to the simulation, however, the Multisim™
package crashed. After troubleshooting, it was discovered that the VHDL interface for
Multisim™ was not functioning. Electronics Workbench is developing a newer version
of their design software to correct this bug, however, the fix was not available in time for
the submission of this work.
F. PRINTED CIRCUIT BOARD CONSTRUCTION
In order to produce a PCB for the system, the entire circuit needs to be
constructed in a program capable of generating a Gerber file (drawing file used by PCB
milling machines). The Multisim/Ultiboard/Ultiroute™ software package produced by
Electronics Workbench was selected to do this design. Multisim™ is a schematic capture
and simulation program. It is used to design and test circuits. Once a design is complete,
the program will generate a parts list and netlist, which is necessary to lay out the PCB.
The Ultiboard program converts the parts list into a nearly complete scale drawing of all
the components and the board itself. A board size is selected and the components are
arranged to fit. Once the component layout is complete, the Ultiroute program converts
the netlist into a network of traces. It does this conversion automatically and optimizes
the design to reduce the number of traces required in the system. For complicated boards
the routing process will invariably miss a couple of pins. This is corrected by manually
adding the traces.
The next step in the process is to generate a Gerber file for production. There are
a few different types Gerber files that Ultiboard™ will generate. The equipment that is
used to manufacture the PCB dictates the type that needs to be generated. Once the
Gerber file is created, it is sent to a manufacturing site. The PCBs that were constructed
for this system were milled by the NPS Physics department. The department owns a
small milling machine capable of manufacturing 1 1 in. by 9 in. circuit boards. Because
66
of the size limitations of the milling machine, two circuit boards were designed. Once
the boards were milled, ground and continuity checks were completed. When each of the
boards was certified, they were stuffed and soldered. Tables 6.4 and 6.5 list all the
materials required to assemble the printed circuit boards.
Bill of Materials Modulus 8 PCB
Quantity Description Reference ID Packaqe
1 CONNECTORS, HDR2X7 CON1 HDR2X7
1 CONNECTORS, RIBBON 14V MNT CON2S RIBBON14VM3 74 LS, 74LS273N U36, U34.U30 NO20
8 CAPACITOR. 100pF C83.C82.C81.C80.
C79.C78.C77.C76
cap2
16 RESISTOR. lOOkohm R137.R136.R135. R
134.R133.R132. R1
31.R130.R109.R10
5, R101.R97.R93.
R89. R85.R81
RESO.5
1 SOCKETS. DIP28 U26 DIP-28
3 POTENTIOMETER, 50K UN R110,R106,R103 UN POT1 RESISTOR, 330kohm R112 RES0 5
1 RESISTOR, 240kohm R107 RES0.5
1 RESISTOR, 120kohm R104 RES0.5
1 RESISTOR, 75kohm R100 RES0.5
1 POTENTIOMETER. 20K LIN R98 LIN POT1 RESISTOR, 47kohm R95 RES0.5
2 POTENTIOMETER, 10K UN R94.R91 UN POT9 RESISTOR. 22kohm R92. R111.R108.R1
02. R99.R96.R90,
R87.R84
RES0.5
1 RESISTOR, 12kohm R88 RES0.5
1 RESISTOR. 6.2kohm R83 RES0.5
20 CAPACITOR. 100nF C58.C57.C56.C55.
C54.C53.C52.C51
,C50,C49,C48,C4
7, C46, C45, C44. C
43, C42.C41.C40,
C39
CAP4
8 COMPARATOR. LM311N U22.U20.U18.U16.
U14.U12.U10.U8DIP-8(N08E)
3 POTENTIOMETER, 1K UN R86, R82, R79 UN POT2 RESISTOR, 20kohm R80. R75 RES0.5
1 RESISTOR, 1 6ohm R78 RES0.5
1 RESISTOR, 24kohm R77 RES0.5
1 RESISTOR. 10kohm R76 RESO.5
2 OPAMP. LM741CN IB, U4 DIP-8(N08E)
Table 6.4: Bill of Materials for Modulus 8 PCB.
67
Bill of Materials Modulus 17 PCB
Quantity Description Reference ID Packaqe
1 RESISTOR, 6.2kortm R139 RES0 5
1 RESISTOR. 1.3kohm R138 RES0.5
17 RESISTOR. 10Mohm R129. R124.R123.R128.R127.R122.R1
21.R126.R125.R12
0. R119.R118.R117
,R11B. R115. R114.
R113
RES05
1 CONNECTORS. HDR2X7 CON18 HDR2X71 TIMER. LM555CN U38 NOSE
39 CAPACITOR. 100nF C84.C1.C2.C3.C4
,C5, C6, C35, C3G,
C37.C38.C34.C33
,C32,C31,C30,C2
9, C28, C27, C26, C
25,C24,C23,C22,
C21.C20.C19.C18.
C17.C16.C15.C14
.C13.C12.C11.C1
0.C9. C8. C7
cap4
3 74LS, 74LS273N U37U32.U28 NO2017 CAPACITOR. 10OpF C75.C74.C73.C72.
C71.C70.C69.C68
.C67.C66.C65.C6
4, C63.C62.C61.C60.C59
cap2
1 SOCKETS, DIP28 U24 DIP-28
17 COMPARATOR. LM311N U3, U5, U7, U35, U3
3, U31.U29.U27.U25, U23.U21.U19,
U17.U15.U9.U11.
U13
DIP-8(N08E)
18 RESISTOR. lOOkohm R7.R11.R15.R71,
R67.R63.R59.R55.
R50.R49.R46.R42.R39.R35.R31.R1
9. R23. R27
RES0.5
3 POTENTIOMETER. 1K LIN R8.R12. R1 LIN POT1 RESISTOR. 5Ekohm R9 RES0 5
18 RESISTOR, 22kohm R10.R14.R17.R72.
R68.R64.R60.R56
,R51.R54,R43.R4
7.R37.R34.R21.R25.R28.R30
RES0.5
1 RESISTOR, 6.8kohm R13 RES0.5
6 POTENTIOMETER. 10KJJN R16. R36.R32.R20.
R24.R29
UN_POT
1 RESISTOR, 9 1kohm R18 RES052 OPAMP, LM741CN U1.U2 DIP-8(N08E)
2 RESISTOR. 20kohm R4.R6 RES0 5
1 RESISTOR, lOkohm R3 RES0 5
1 RESISTOR. 24kohm R2 RES051 RESISTOR. 1 6ohm R5 RES0 5
2 RESISTOR, 300kohm R74, R70 RES054 POTENTIOMETER, 100K UN R73, R69.R65.R61 UN POT1 RESISTOR, 2O0kohm R66 RES0 5
2 RESISTOR. 150kohm R62.R58 RES0.5
2 POTENTIOMETER, 50K UN R57.R52 UN POT1 RESISTOR. 120kohm R53 RES0 5
3 POTENTIOMETER, 20K LIN R48, R44.R40 UN POT1 RESISTOR, 75kohm R45 RES051 RESISTOR, 55kohm R41 RES051 RESISTOR. 47kohm R38 RES0 5
1 RESISTOR. 33kohm R33 RES0 5
1 RESISTOR. 12kohm R22 RES0 5
1 RESISTOR. 18kohm R26 RES05
Table 6.5: Bill of Materials for the Modulus 17 PCB.
68
After the board is stuffed and soldered, power is connected. The component
connections are tested and the trim potentiometers are set to provide the correct bias and
amplification to the signal and provide the proper reference voltages for the comparators.
Now the boards are ready for operation. The Modulus 17 and 8 PCBs are shown in
Figures 6.11 and 6.12 respectively. Appendix C gives a detailed narrative of how to
manufacture a PCB.
Figure 6.1 1: Modulus 17 Printed Circuit Board.
69
Figure 6.12: Modulus 8 Printed Circuit Board.
70
VII. TEST AND EVALUATION OF PROTOTYPE HARDWARE
A. TEST PROCEDURES
The prototype antenna was tested in the Naval Postgraduate School Microwave
Anechoic Chamber. The major components and communication paths used for testing
are shown in Figure 7.1. The test system architecture centerpiece is a Pentium II
computer. One of two LABVTEW programs controls the test via a General Purpose
Interface Bus (GPDB), the serial port, and a PC-DIO-96 board. The signal generator that
produces the radiated signal is located on the same rack as the Hewlett Packard 8510
Vector Network Analyzer (VNA). In the anechoic chamber, a standard gain feed horn
transmits the microwave signal generated by the signal generator. The antenna is placed
on a pedestal (Figure 7.1) approximately 19 feet from the transmit horn with the
microwave circuit mounted on the back of the array ground plane. A servomotor is
controlled through the computer serial port and rotates the pedestal, which is capable of
steps as small as 0.1°. The microwave circuit continuously analyzes the received signal,
and the mixer output is sampled at each resolution step. The mixer output is carried out
of the anechoic chamber on RG-59 coaxial cables and either connected to the RSNS
processor or two HP 3478A multimeters. The 6-bit output of the RSNS processor is
transmitted to the computer via the DIO board. Two HP 3478A digital multimeters
measure either the mixer output or the shift and bias circuit output. The computer
samples the multimeters through the GPIB bus.
71
Antennas and
Microwave Qrcmt
Transmit Horn
Pedestal
Motor
Vector
Network
Analyzer
Signal
Generator
-*\ gpib Y Multimeters
Serial Port
DIO Board RSNS Processor
Computer
Figure 7.1: Anechoic Chamber Setup.
The data collection and processing technique is illustrated in Figure 7.2. Two
types of tests are conducted depending upon the parameter of interest. The first test
measures the output of the mixer, and other test measures the output of the shift and bias
amplifier and the binary output of the RSNS processor simultaneously. One LABVIEW
program is written for each test. When the mixer output is measured, the procedure
follows the left path on Figure 7.2. The LABVIEW VI code DF_mm_R2 samples the
multimeters at each servomotor step. The data is saved in column format. The four
columns of data are (1) antenna position, (2) channel 1 (modulus 8) multimeter output,
(3) antenna position, and (4) channel 2 (modulus 17) multimeter output. The data is
analyzed with Microsoft Excel using the "text-tab delimited" format. Manual
72
normalization of the data is performed. The minimum and maximum values of the phase
detector folding waveforms are located. A column is inserted between the second and
third data columns. The normalized phase detector output r|j,norm is calculated using the
equations:
n = (Tl max +ri min )/2, (7.1)
AT| = (t|_-Ti»ta )/2, (7.2)
Ar)
The normalized output for each channel is placed in the new third column (modulus 8)
and the sixth columns (modulus 17). The normalized phase detector output is saved in
tab delimited text format with a ".dat" extension. This is the standard input format for
the MATLAB processing programs provided in Appendix A. The measured phase
(mixer output) is visually compared to the simulated data using the rsns8.m and rsnsl7.m
programs. Phase_error.m calculates and plots the phase error between a simulated and
normalized measured mixer output. The normalized mixer output is passed through a
simulation of the digital processing in Bin_Pop.m.
The output of the digital circuit follows the path on the right of Figure 7.2. The
shift and bias circuit output is connected to the multimeters. The binary output of the
digital circuit is connected to the computer via the DIO board. The LABVTEW VI code
DF5_DIO_R2 samples the multimeters and DIO board at each servomotor step. The data
is again saved in column format. No normalization is required for this data, but it must
be saved in tab delimited text format with a ".dat" extension. Analysis of the data is
performed by one program, AOAjnap.m. This program plots the folding waveforms and
the bin mapping. It converts the bin numbers into an estimated angle of arrival and plots
the transfer function.
73
Phase
Detector
Shift and
Bias Circuit
nor)*
HP 3478A
Multimeter
EEPROM #2
Combiner
HP 3478A
Multimeter
I
LABVIEW 5.1
DF 3 R2.viPnly one
LABVEEW 5.1
DF5 DIO R2.vi
EXCELManual
Normalization
MATLABAOA_map.m
lMATLABrsns8.m
rsnsU.m
r \ f\
MATLAB MATLABBin?fop.m
J
phase_error.
m
)
Figure 7.2: Anechoic Chamber Control and Recording Equipment.
74
B. RKSULTS
The RSNS direction finding system was built and tested. The array design is
scaled so that the field of view is 60°. The tests were conducted at 8 GHz at a resolution
of 0.1°. Data from the mixer outputs, RSNS processor, and level and bias amplifiers
were recorded.
The folding waveforms for both moduli are shown in Figures 7.3 and 7.4. The
blue curves are the ideal waveform and the red curves are the measured waveforms after
they have been normalized. The green curve is the residual error of the measured signal.
BinPop.m produces the simulated RSNS antenna transfer function using measured mixer
outputs. Figure 7.5 shows this transfer function. Once it was shown that the transfer
function was mostly continuous, a complete test of the system was conducted. Figure 7.6
is the folding waveforms after the shift and bias amplifiers have processed them. The
output of the RSNS processor is recorded through the DIO board and the AOA_map.m
file produces the angle of arrival estimation of the entire system, shown in Figure 7.7.
Modulus 8, Measured values • Expected values
8
0.6
- 0.4
O 2
NI "° 2
E
I -0 4
-0 6
-0 8
- -
f\i
s"",tLj^yS
Simulated
Measured
Difference
1
-80 -60 -40 -20 20 40
Angle of Arrival (degrees)
60 80
Figure 7.3: Modulus 8 Normalized Mixer Output.
75
Modulus 17, Measured values - Expected values
1
0.8
0.6
S 04Q.
0.2
ox2DCO
3 -02
£
1 -0.4
-0.6
-0.8
-1
/ Simulated
Measured
Difference
- - ' i
k?s/V/Vv
»^_ -•
-80 -60 -40 -20 20
Angle of Arrival (degrees)
40 60 80
Figure 7.4: Modulus 17 Normalized Mixer Output.
80
60
CD
£ 40
| 20
B -
0)
o -20Q.
cr
-40
-60
. r-^L^ / I . In !
i 1 1 1 i i i \ 1 1 1
-100 -80 -60 -40 -20 20 40 60 80 100
Angle of Arrival (degrees)
Figure 7.5: Simulated RSNS Antenna Transfer Function Using Measured Mixer Outputs.
76
14
12
10
S- 8
CO 6
/ :
— Modulus 8 /
Modulus 17 I /
\y
-80 -60 -40 -20 20 40
Angle of Arrival (degrees)
60 80
Figure 7.6: Level and Bias Amplifiers Outputs.
< 20
« -20
W .40
-60 -40 -20 20
Angle of Arrival (degrees)
40 60 80
Figure 7.7: RSNS Antenna Transfer Function.
77
THIS PAGE INTENTIONALLY LEFT BLANK
78
VIII CONCLUSIONS
A. CONCLUSIONS
This research has introduced the Robust Symmetrical Number System and shown
that it can be used to resolve ambiguities in phase sampling interferometry. A direction
finding antenna architecture based on the RSNS has many inherent advantages over
conventional direction finding techniques including: simple microwave beamforming
network that incorporates wideband components, wide instantaneous field of view, and
high resolution angle of arrival with a variety of element arrangements having very short
baselines. The design equations for comparator thresholds, broadside phase difference,
and a scale factor are derived. The simulated transfer function demonstrates that the
RSNS antenna will have a wide instantaneous field of view and high resolution.
A second prototype array was built and its performance measured. Several
improvements were made to the original RSNS prototype antenna. By adopting the
scaled antenna carriage, adding isolators, and completing the ground plane with copper
tape between the antenna elements mutual coupling effects are reduced. Mounting the
microwave components on a brass plate has reduced errors contributed by vibrations and
temperature. Tailor cutting all semi-rigid coaxial lines has reduced the number of
connectors required to assemble the microwave circuit and has subsequently reduced the
errors inherent in connectors. Matching amplifiers by amplification stage rather than by
signal line has reduce relative phase errors between channels as well as better matched
the power outputs of both amplification stages. Two printed circuit boards were designed
and built for the RSNS processor. The printed circuit boards provide a more stable
platform over the original design, which was assembled on breadboards.
The measured transfer function of the new prototype exhibits the basic features of
the ideal transfer function. The measured transfer function contains small encoding
errors. These errors are attributed to phase errors in the microwave circuit and its
components as well as threshold errors inherent in the RSNS processor. Comparing the
79
transfer functions of the first and second prototypes and the ideal case, the improvements
in the system are revealed. Figure 8.1 shows the simulated transfer function of the first
prototype RSNS antenna using the measured mixer outputs. Note that the large phase
errors present (see Figure 4.7 and 4.8) cause a significant degradation in the antenna
performance.
-80 -60 -40 -20 20 40
Angle of Arrival (degrees)
60 80
Figure 8.1: Simulated Transfer Function of the RSNS Antenna Using Measured Mixer
Outputs (First Prototype) [from 5].
Figure 8.2 shows the simulated transfer function of the second prototype RSNS antenna
using the improved mixer output response (see Figure 7.3 and 7.4). Note that this
response matches the ideal response (shown in Figure 8.3) much more closely with only a
few encoding errors present.
80
80
60
£ 40
f 20
-20
-40
-60
. . r~y L,. . . /. I ht____ . .
-100 -80 -60 -40 -20 20 40 60 80 100
Angle of Arrival (degrees)
Figure 8.2: Measured Mixer Output Through Simulated RSNS Processor, Second
Prototype.
80
60 -
40 -
« 20
<--
-20
o -40
-60
-80
-80 -60 -40 -20 20 40
Angle of Arrival (degrees)
60 80
Figure 8.3: Ideal Transfer Function.
81
The initial results from the RSNS digital processor shown in Figure 8.4 were not
expected. The EEPROM programming will output zeros if the inputs do not match a
known set of inputs from Table 6.3. This occurs in the regions where the estimated angle
of arrival is -90°. Each set of components (i.e. program on EEPROM, latches,
comparator thresholds, and bias and level amplifier performance) was individually
verified for proper function; however, when the whole system is tested it does not
entirely work. Errors in the circuit design may be attributed to the comparators
themselves. Data sets from different runs were compared against each other to see where
the errors occurred. It was noticed that the errors sometimes occurred at a specific angle
and sometimes not. Using the anechoic chamber and testing a single angle verified this.
Even though the comparator threshold's accuracy is improved with the Schmitt trigger,
errors may still be occurring. To test this, the Labview code needs to be modified so the
comparator states, input signal, and threshold values can be monitored. If it is
determined that the comparators are not accurate enough, a precision comparator such as
the CMP02 or CMP04 could be substituted for the LM31 1.
-80 -60 -40 -20 20 40
Angle of Arrival (degrees)
Figure 8.4: Measured Antenna Transfer Function.
82
B. FUTURE WORK
The complete design of the RSNS direction finding system is an continually
evolving process. A number of areas for further research exist. These areas include
topics such as frequency agility, increased resolution, and operation in a multi-signal
environment.
It is desired to design a new system capable of handling a wide range of
frequencies. The angle of incidence of the signal determines the phase difference
between the antenna elements. This phase difference is linearly dependant upon the
wavelength and therefore the frequency of the incoming signal. A relationship between
the angular resolution and the dynamic range of the RSNS can be derived. Research into
how to control the frequency effects on the RSNS antenna array is needed.
Another improvement to the design that can be looked into is increasing the
resolution of the system. There are several methods that could be used to accomplish this
task. Some ideas are to increase the dynamic range of the RSNS by increasing modulus
number in each channel or by increasing the number of channels. Preliminary data
suggests that phase errors are more prevalent in higher modulus channels therefore this
might not be a desirable method to accomplish increased resolution. Work needs to be
conducted to determine the optimal method to accomplish this task.
Finally, in order to be able to field a system in an uncontrolled environment, a
multi-signal capability needs to be included into the design. It maybe possible to select
individual frequencies by adding an adaptive filter or frequency selector to the front end
of the system.
C. CONCLUDING REMARKS
The focus of this thesis research has been to improve the design and
performance of a previous RSNS DF array. The design equations and operating
parameters have been presented. The overall performance of the microwave circuit has
83
been improved and the phase errors reduced to a level to where the signal processor con
effectively operate. Although the results from the RSNS signal processor are
disappointing it has been shown that the RSNS signal processing technique is a viable
technique for future DF applications.
84
APPENDIX A. VHDL CODE
This appendix presents the VHDL code used to simulate both EEPROMs for the
system. Each EEPROM needs two modules to function correctly. The first module is the
actual code that is used to simulate the component. The second module is a test bench
that is used to verify the functionality of the code.
--EEPROM #1 Module
-- Note: comments beginning with WIZ should be left intact.Other comments are informational only.
-- Multisim VHDL software version: 3.75a
library ieee;use ieee. std_logic_l 164 .all
;
-- use ieee. numeric_std. all ; -- Note: uncomment this if you use-- IEEE standard signed or unsigned types.
-- use ieee. std_logic_arith. all; -- Note: uncomment this if you use-- Synopsys signed or unsigned types,
entity EEPROM_l isgeneric (D:time :=10 ns)
;
port (
AO: in bit;Al: in bit;A2: in bit;A3: in bit;A4: in bit;A5: in bit;A6: in bit;A7: in bit;A8: in bit;A9: in bit;A10 in bitAll in bitA12 in bitA13 in bitA14 in bitIOO out bit;101 out bit;102 out bit;103 out bi t
);
end EEPR0M_1;-- From VHDL Design, J.R. Armstrong, pg. 320-- Model for combinational logic using CASE statementarchitecture EEPR0M_1A of EEPR0M_1 isbegin
PI : process ( Al 4 , Al 3 , A12 , Al 1 , Al , A9 , A8 , A7 , A6 , A5 , A4 , A3 , A2 , Al , AO
)
begincase A14&A13&A12&A11&A10&A9&A8&A7&A6&A5&A4&A3&A2&A1&A0 is
when "000000000000000" => 103 <= '0' after D; 102 <= '
101 <= '0' after D; IOO <= '0' after Dwhen "000000000000001" => 103 <= '0' after D; 102 <
101 <= '0' after D; IOO <= '1' after Dwhen "000000000000011" => 103 <= '0' after D; 102 <=
101 <= '1' after D; IOO <= '0' after Dwhen "000000000000111" => 103 <= '0' after
IOl <= '1' after D; IOO <= '1' after Dwhen "000000000001111" => 103 <= '0' after D; 102 <=
IOl <= '0' after D; IOO <= '0' after D
after D;
after D;
after D;
D; 102 <= '0' after D;
after D;
85
when "000000000011111" => 103 <= '0' after D; 102 <= ' 1' after D101 <= '0' after D; IO0 <= '1' after D;
when "000000000111111" => 103 <= '0' after D; 102 <= '1' after D101 <= '!' after D; IOO <= '0' after D;
when "000000001111111" => 103 <= '0' after D; 102 <= '1' after D101 <= '1' after D; IOO <= '1' after D;
when "000000011111111" => 103 <= '1' after D; 102 <= '0' after D101 <= # 0' after D; IOO <= '0' after D;
when "000000111111111" => 103 <= '1' after D; 102 <= '0' after DIOl <= '0' after D; IOO <= '1' after D;
when "000001111111111" => 103 <= '1' after D; 102 <= '0' after DIOl <= '1' after D; IOO <= '0' after D;
when "000011111111111" => 103 <= '1' after D; 102 <= '0' after DIOl <= '1' after D; IOO <= '1' after D;
when "000111111111111" => 103 <= '1' after D; 102 <= '1' after DIOl <= '0' after D; IOO <= '0' after D;
when "001111111111111" => 103 <= '1' after D; 102 <= *1' after DIOl <= '0' after D; IOO <= ' 1' after D;
when "011111111111111" => 103 <= '1' after D; 102 <= '1' after DIOl <= '1' after D; IOO <= '0' after D;
when "111111111111111" => 103 <= '1' after D; 102 <= '1' arcer DIOl <= '1' after D; IOO <= '1' after D;
end case;end process PI
;
end EEPR0M_1A;
--Test Bench Module for: EEPROM_l
-- Note: comments beginning with WIZ should be left intact.Other comments are informational only.
-- Multisim VHDL software version: 3.75a
library ieee;use ieee. std_logic_1164 .all;-- use ieee. numeric_std. all; -- Note: uncomment this if you use
-- IEEE standard signed or unsigned types.-- use ieee. std_logic_arith. all; -- Note: uncomment /modify this if you use
-- Synopsys signed or unsigned types,use std. text io. all;use work. all;
entity TESTBNCH isend TESTBNCH;
architecture stimulus of TESTBNCH iscomponent EEPROM_l is
port (
A0 in BITAl in BITA2 in BITA3 in BITA4 in BITA5 in BITA6 in BITA7 in BITA8 in BITA9 in BITAl(): in BIT;ai:L: in BIT;ai;>: in BIT;ai:S: in BIT;Al'1: in BIT;IO(): out BITio:L : out BITio:> : out BITio:i : out b:[T
86
) ;
end component;constant PERIOD: time := 50 ns;-- Top level signals go here...signal A0 : BIT;signal Al : BIT;signal A2 : BIT;signal A3: BIT;signal A4 : BIT;signal A5 : BIT;signal A6 : BIT;signal A7 : BIT;signal A8: BIT;Signal A9 : BIT;signal A10: BITsignal All: BITsignal A12: BITsignal A13: BITsignal A14: BITsignal IOO: BITsignal 101: BITsignal 102: BITsignal 103 : BIT
signal done: boolean false;
beginDUT: EEPR0M_1 port map (
AO,Al,
A2,A3,
A4,
A5,
A6,A7,
A8,A9,
A10,All,A12,A13,A14,IOO,101,102,
103
);
STIMULUS1 : processbegin
-- Sequential stimulus goes here.
-- Sample stimulus...
< =
<=AO
Al
A2 < =
A3 < =
A4 < =
A5 < =
A6 < =
A7 < =
A8 < =
A9 < =
afterafter
afterafter
ns,
ns.
after ns,
ns,
ns,
after 100 ns;after 200 ns;after 300 ns;
after 400 ns;
after 500 ns;
87
A10 < = '0'
All < = '0'
A12 < = •0"
A13 < = •0'
A14 < = '0'
wait; _
end process STIMULUS 1
;
Suspend simulation
end stimulus;
--EEPROM #2 Module
-- Note: comments beginning with WIZ should be left intact.Other comments are informational only.
-- Multisim VHDL software version: 3.75a
library ieee;use ieee. std_logic_1164. all;-- use ieee.numeric_std.all;
-- use ieee. std_logic_arith. all;
Note: uncomment this if you useIEEE standard signed or unsigned types.Note: uncomment this if you useSynopsys signed or unsigned types.
entity EEPROM_2 isgeneric (D:time :=10 ns)
;
port (
-- WIZ BEGINPORTS (Entity Wizard command)A0 in BIT;Al in BIT;A2 in BIT;A3 in BIT;A4 in BIT;A5 in BIT;A6 in BIT;A7 in BIT;A8 in BIT;A9 in BIT;Alt): in BITA1j.: in BIT .
ai:>: in BITai:1: in BITIO(): out BIT10]. : out BITio;>: out BITio:5: out BITIO^I: out BITio:>: out BI T
WIZ ENDPORTS (Entity Wizard command))
end EEPROM_2;-- From VHDL Design, J.R. Armstrong, pg. 320-- Model for combinational logic using CASE statementarchitecture EEPROM_2A of EEPROM_2 isbegin
PI : process ( A13 , A12 , All , A10 , A9 , A8 , A7 , A6 , A5 , A4 , A3 , A2 , Al , A0
)
begincase A13&A12&A11&A10&A9&A8&A7&A6&A5&A4&A3&A2_A1&AO is
when "00000000000000" => 105 <=
103 <= '0' after D; 102 <=
IOO <= '0' after D; --0
when "00111111001010" => 105 <=
103 <= 'O' after D; 102 <=
IOO <= '0' after D; --0
when "00011111001010" => 105 <=
103 <= '0' after D; 102 <=
IOO <= •!• after D; --1
•0' after D; 104 <= '0' after D;0' after D; 101 <= '0' after D;
after D;
after D;
after D;
after D;
104 <=
101 < =
104 < =
101 < =
1 0' after D;' 0" after D;
•0' after D;
1 0' after D;
88
when "00011111001011" => 105 <= '0' after D; 104 <= '0' after D;
103 <= '0' after D; 102 <= '0' after D; 101 <= ' 1' after D;
IOO <= '0' after D; --2
when "00001111001011" => 105 <= '0' after D; 104 <= '0' after D;
103 <= '0' after D; 102 <= '0' after D; 101 <= ' 1' after D;
IOO <= '1' after D; --3
when "00001111001100" => 105 <= '0' after D; 104 <= '0' after D;
103 <= '0' after D; 102 <= ' 1' after D; 101 <= '0' after D;
IOO <= '0' after D; --4
when "00000111001100" => 105 <= '0' after D; 104 <= '0' after D;
103 <= '0' after D; 102 <= '1' after D; 101 <= '0' after D;
IOO <= '1* after D; --5
when "00000111001101" => 105 <= '0' after D; 104 <= '0' after D,-
103 <= '0' after D; 102 <= ' 1' after D; 101 <= ' 1' after D;
IOO <= '0' after D; --6
when "00000011001101" => 105 <= '0' after D; 104 <= '0' after D;
103 <= '0' after D; 102 <= '1' after D; 101 <= '1' after D;
IOO <= '1' after D; --7
when "00000011001110" => 105 <= '0' after D; 104 <= '0' after D;
103 <= ' 1' after D; 102 <= '0' after D; 101 <= '0' after D;
IOO <= '0' after D; --8
when "00000001001110" => 105 <= '0' after D; 104 <= '0' after D;
103 <= '1' after D; 102 <= '0' after D; 101 <= '0' after D;
IOO <= '1' after D; --9
when "00000001001111" => 105 <= '0' after D; 104 <= '0' after D,-
103 <= '1' after D; 102 <= '0' after D; 101 <= '1' after D;
IOO <= '0' after D; --10
when "00000000001111" => 105 <= '0' after D; 104 <= '0' after D;
103 <= '1' after D; 102 <= '0' after D; 101 <= ' 1' after D;
IOO <= '1' after D; --11
when "00000000011111" => 105 <= '0' after D; 104 <= '0' after D;
103 <= '1' after D; 102 <= '1' after D; 101 <= '0' after D;
IOO <= '0' after D; --12
when "00000001011111" => 105 <= '0' after D; 104 <= '0' after D;
103 <= '1' after D; 102 <= '1' after D; 101 <= '0' after D;
IOO <= '1' after D; --13
when "00000001111111" => 105 <= '0' after D; 104 <= '0' after D;103 <= '1' after D; 102 <= '1' after D; 101 <= '1' after D;
IOO <= '0' after D; --14when "00000011111111" => 105 <= '0' after D; 104 <= '0' after D;
103 <= '1' after D; 102 <= ' 1' after D; 101 <= '1' after D;
IOO <= '1' after D; --15when "00000011011111" => 105 <= '0' after D; 104 <= '1' after D;
103 <= '0' after D; 102 <= ' 0" after D; 101 <= '0' after D;
IOO <= '0' after D; --16when "00000111011111" => 105 <= '0' after D; 104 <= '1' after D;
103 <= '0' after D; 102 <= '0 1 after D; 101 <= '0' after D;
IOO <= '1' after D; --17
when "00000111001111" => 105 <= '0' after D; 104 <= '1' after D;
103 <= '0' after D; 102 <= '0' after D; 101 <= '1' after D;
IOO <= '0' after D; --18when "00001111001111" => 105 <= '0' after D; 104 <= '1' after D;
103 <= '0' after D; 102 <= '0* after D; 101 <= '1' after D;
IOO <= '1' after D; --19when "00001111001110" => 105 <= '0' after D; 104 <= '1* after D;
103 <= '0' after D; 102 <= '1' after D; 101 <= '0' after D;
IOO <= '0' after D; --20when "00011111001110" => 105 <= '0' after D; 104 <= '1' after D;
103 <= '0' after D; 102 <= '1' after D; 101 <= '0' after D;
IOO <= '1' after D; --21when "00011111001101" => 105 <= '0' after D; 104 <= '1' after D;
103 <= '0' after D; 102 <= '1' after D; 101 <= '1' after D;
IOO <= '0' after D; --22when "00111111001101" => 105 <= '0' after D; 104 <= '1' after D;
103 <= '0' after D; 102 <= '1' after D; 101 <= '1' after D;
IOO <= '1' after D; --23when "00111111001100" => 105 <= '0' after D; 104 <= '1' after D;
103 <= ' 1' after D; 102 <= '0' after D; 101 <= '0' after D;
IOO <= '0' after D; --24
89
when "01111111001100" => 105 <= '0' after D; 104 <= '1' after D;
103 <= '1' after D; 102 <= '0' after D; 101 <= '0' after D;
IOO <= '1' after D; --25
when "01111111001011" => 105 <= '0' after D; 104 <= '1' after D;
103 <= ' 1' after D; 102 <= '0' after D; 101 <= '1' after D;
IOO <= '0' after D; --26
when "11111111001011" => 105 <= '0' after D; 104 <= '1' after D;
103 <= '1' after D; 102 <= '0' after D; 101 <= '1' after D;
IOO <= '1
' after D; --27
when "11111111001010" => 105 <= '0' after D; 104 <= '1' after D;
103 <= '1' after D; 102 <= '1' after D; 101 <= '0' after D;
IOO <= '0' after D; --28when "01111111001010" => 105 <= '0' after D; 104 <= 'l' after D;
103 <= '1' after D; 102 <= '1' after D; 101 <= '0' after D;
IOO <= '1' after D; --29
when "01111111001001" => 105 <= '0' after D; 104 <= '1' after D;
103 <= '1' after D; 102 <= '1' after D; 101 <= '1' after D;
IOO <= '0' after D; --30when "00111111001001" => 105 <= '0' after D; 104 <= '1' after D;
103 <= '1' after D; 102 <= '1' after D; 101 <= '1' after D;
IOO <= '1' after D; --31
when "00111111001000" => 105 <= '1' after D; 104 <= '0' after D;
103 <= '0' after D; 102 <= '0' after D; 101 <= '0' after D;
IOO <= '0' after D; --32
when "00011111001000" => 105 <= '1' after D,- 104 <= '0' after D;
103 <= '0' after D; 102 <= '0' after D; 101 <= '0' after D;
IOO <= '1' after D; --33
when "00011111000111" => 105 <= '1' after D; 104 <= '0' after D;
103 <= '0' after D; 102 <= '0' after D; 101 <= '1' after D;
IOO <= '0' after D; --34
when "00001111000111" => 105 <= '1' after D; 104 <= 'O" after D;
103 <= '0' after D; 102 <= '0' after D; 101 <= '1' after D;
IOO <= '1' after D; --35
when "00001111000110" => 105 <= '1' after D; 104 <= '0' after D;
103 <= '0' after D; 102 <= '1' after D; 101 <= '0' after D;
IOO <= '0' after D; --36
when "00000111000110" => 105 <= '1' after D; 104 <= '0' after D;
103 <= '0' after D; 102 <= '1' after D; 101 <= '0' after D;
IOO <= '1' after D; --37
when "00000111000101" => 105 <= '1' after D; 104 <= '0' after D;
103 <= '0' after D; 102 <= '1' after D; 101 <= '1' after D;
IOO <= "0' after D; --38
when "00000011000101" => 105 <= '1' after D; 104 <= '0' after D;
103 <= '0' after D; 102 <= '1' after D; 101 <= '1' after D;
IOO <= '1' after D; --39
when "00000011000100" => 105 <= '1' after D; 104 <= '0' after D;
103 <= '1' after D; 102 <= '0' after D; 101 <= '0' after D;
IOO <= '0' after D; --40
when "00000001000100" => 105 <= '1' after D; 104 <= '0' after D;
103 <= '1' after D; 102 <= '0' after D; 101 <= '0' after D;
IOO <= '1' after D; --41
when "00000001000011" => 105 <= '1' after D; 104 <= '0' after D;
103 <= '1' after D; 102 <= '0' after D; 101 <= '1' after D;
IOO <= '0' after D; --42
when "00000000000011" => 105 <= '1' after D; 104 <= '0' after D;
103 <= '1' after D; 102 <= '0' after D; 101 <= '1' after D;
IOO <= '1' after D; --43
when "00000000000010" => 105 <= '1' after D; 104 <= '0' after D;
103 <= '1' after D; 102 <= '1' after D; 101 <= ' 0' after D;
IOO <= '0' after D; --44
when "00000001000010" => 105 <= '1' after D; 104 <= '0' after D;
103 <= '1' after D; 102 <= '1' after D; 101 <= *0' after D;
IOO <= '1' after D; --45
when "00000001000001" => 105 <= '1' after D; 104 <= '0' after D;
103 <= '1' after D; 102 <= '1' after D; 101 <= '1' after D;
IOO <= '0' after D; --46
when "00000011000001" => 105 <= '1' after D; 104 <= ' 0" after D;
103 <= '1' after D; 102 <= '1' after D; 101 <= '1' after D;
IOO <= '1' after D; --47
90
when "00000011000000" => 105 <= ' 1" after D; 104 <= • 1" after D;
103 <= '0' after D; 102 <= '0' after D; 101 <= '0' after D;
IO0 <= • 0' after D; --48
when "00000111000000" => 105 <= ' 1' after D; 104 <= ' 1' after D;
103 <= '0' after D; 102 <= '0' after D; 101 <= '0' after D;
IO0 <= '1' after D; --49
when "00000111000001" => 105 <= ' 1' after D; 104 <= '1' after D;
103 <= '0' after D; 102 <= '0' after D; 101 <= ' 1" after D;
IOO <= '0' after D; --50
when "00001111000001" => 105 <= ' 1' after D; 104 <= '1' after D;
103 <= '0' after D; 102 <= • 0' after D; IOl <= ' 1' after D;
IOO <= '1' after D; --51
when "00001111000010" => 105 <= ' 1* after D; 104 <= ' 1' after D;
103 <= '0' after D; 102 <= '1' after D; IOl <= '0' after D;
IOO <= '0' after D; --52
when "00011111000010" => 105 <= ' 1' after D; 104 <= ' 1' after D;
103 <= '0' after D; 102 <= ' 1' after D; IOl <= '0' after D;
IOO <= ' 1" after D; --53
when "00011111000011" => 105 <= '1' after D; 104 <= '1' after D;
103 <= '0' after D; 102 <= ' 1' after D; IOl <= '1' after D;
IOO <= '0' after D; --54
when "00111111000011" => 105 <= '1' after D; 104 <= '1' after D;
103 <= '0' after D; 102 <= 1' after D; IOl <= '1' after D;
IOO <= ' 1' after D; --55
when "00111111000100" => 105 <= '1' after D; 104 <= • 1" after D;
103 <= ' 1' after D; 102 <= '0' after D; IOl <= '0' after D;
IOO <= 'O 1 after D; --56
when "01111111000100" => 105 <= '1' after D; 104 <= ' 1" after D;
103 <= ' 1" after D; 102 <= '0' after D; IOl <= '0' after D;
IOO <= '1' after D; --57
when "01111111000101" => 105 <= '1' after D; 104 <= ' 1' after D;
103 <= '1' after D; 102 <= "0* after D; IOl <= '1' after D;
IOO <= '0' after D; --58
when "11111111000101" => 105 <= '1' after D; 104 <= ' 1' after D;
103 <= ' 1' after D; 102 <= "O" after D; IOl <= '1' after D;
IOO <= '1' after D; --59
when "11111111000110" => 105 <= ' 1" after D; 104 <= '1' after D;
103 <= ' 1' after D; 102 <= '1' after D; IOl <= '0' after D;
IOO <= '0' after D; --60
when "01111111000110" => 105 <= '1' after D; 104 <= ' 1" after D;
103 <= '1' after D; 102 <= '1' after D; IOl <= '0" after D;
IOO <= '1' after D; --61
when "01111111000111" => 105 <= '1' after D; 104 <= '1' after D;
103 <= '!' after D; 102 <= '1' after D; IOl <= '1' after D;
IOO <= '0' after D; --62when "00111111000111" => 105 <= '1' after D; 104 <= '1' after D;
103 <= ' 1" after D; 102 <= '1' after D; IOl <= '1' after D;
100 <= •!' after D; --63
end case;end process PI
;
end EEPROM_2A;
--Test Bench Module for: EEPROM_2
-- Note: comments beginning with WIZ should be left intact.Other comments are informational only.
-- Multisim VHDL software version: 3.75a
library ieee;use ieee. std_logic_1164 .all;-- use ieee. numeric_std. all; -- Note: uncomment this if you use
-- IEEE standard signed or unsigned types.-- use ieee.std_logic_arith.all; -- Note: uncomment /modify this if you use
-- Synopsys signed or unsigned types,use std. textio.all;use work. all;
91
entity TESTBNCH is
end TESTBNCH
;
architecture stimulus of TESTBNCH iscomponent EEPR0M_2 is
port (
in BIT;AGAl
A2A3
A4
A5
A6A7
A8A9A10AllA12A13
in BITin BITin BITin BITin BITin BITin BITin BITin BITin BITin BITin BITin BIT
IOO: out BIT101: out BIT
out BITout BIT
104: out BIT105: out BIT
102:
103:
);
end component;constant PERIOD: time := 50 ns;-- Top level signals go here...signal AO : BIT;signal Al : BITsignal A2 : BITsignal A3 : BITsignal A4 : BITsignal A5 : BITsignal A6 : BITsignal A7 : BITsignal A8 : BITsignal A9 : BITsignal A10: BITsignal All: BITsignal A12: BITsignal A13: BITsignal IOO: BITsignal 101: BITsignal 102: BITsignal 103: BITsignal 104: BITsignal 105: BIT
signal done: boolean := false;
beginDUT: EEPR0M_2 port map (
AO,
Al,A2,
A3,A4,
A5,A6,
A7,A8,
A9,A10,
92
All,A12,A13,IOO,
101,
102,103,
104,105
>;
STIMULUS1: processbegin
-- Sequential stimulus goes here.
-- Sample stimulus. .
.
AO <= •0',
•1' after 100 ns;
Al <= ' 1' ;
A2 <= •0', •1' after 100 ns;A3 <= ' 1' ;
A4 < = •0';
A5 <= '0';
A6 <= •1",
'0' after 100 ns;A7 <= •1'
,•0' after 100 ns;
A8 <= '1*,
'0' after 100 ns;A9 <= •1'
,•0' after 100 ns;
A10 < = •1',
'0 1 after 100 ns;All < = '1',
,
'0 ' after 100 ns;
A12 < = '0',
A13 <= •o\
wait; -- Suspend simulationend process STIMULUS1;
end stimulus;
93
THIS PAGE INTENTIONALLY LEFT BLANK
94
APPENDIX B. MATLAB SIMULATION AND DATA
EVALUATION CODE
%RSNS8 WITH SHIFTING
% LT Nathan York, 15 December 2 000% Generates the simulated folding waveform. Two element arraysassumed.% Can accept normalized mixer output for comparison to simulatedwaveform.% Plots folding waveforms for simulated and measured data.% m = modulus; d = spacing (m) ; f = frequencyclearN=2;f=8.0e9; c=3e8; wavl=c/f;k=2*pi/wavl;rad=pi/180;sf=sqrt(3)/2 % sf is the scale factor
% ffd is forced phase difference to align signal to required zerocrossingffd=45; %original is 45!
% number of moduli in array design and their valuesmm=[8 17]; nm= length (mm)
;
disp('moduli are: '),disp(mm)% specify a modulus to plotm=8;
% M is Dynamic RangeM=64;% nf is number of foldsnf=M/ (2*m*N)
;
% determines required element spacing
d=nf*wavl/sf/2;
% start, stop, increment anglesstart=-90; stop=90; inc=0.1;N= floor ( (stop- start) /inc) + 1;
for n=l:N;thd(n)=start+(n-l) *inc; thr=thd(n) *rad;arg(n) =k*d*sin(thr)
;
% mixer outputmx(n)=cos(arg(n)+(ffd)*(pi/180) )
;
end
95
load rsnsl4.datboth8= [thd' mx'];save simu8.dat both8 -ascii
figure (1)
holdplot ( thd,mx, '
b')
;
plot (rsnsl4 ( : , 1) ,rsnsl4 ( : , 3), "r '
)
hold offxlabel ( 'Angle of Arrival ' ) , ylabel ( 'Normalized Mixer Output
' )
;
gridxlabel ( 'Angle of Arrival (degrees)')ylabel ( 'Normalized Mixer Output
'
)
title ([ 'Modulus 8, with ffd = ' ,num2str ( f fd) ]
)
legend (
' Simulated'
,
' Measured ' , )
axis{ [-90,90,-1,1]
)
orient landscape
temp=rsnsl4 ( : , 3 ) ;
templ=rot90 (temp)
;
lef t =tempi -mx;
:
zero=0;
figure (2)
holdplot (thd, mx, 'b' ) ;
plot (rsnsl4( : , 1) , rsnsl4 ( : ,3), 'r '
)
plot (thd, left,'
g')
;
plot (thd, zero, 'k'
)
;
xlabel ( 'Angle of Arrival (degrees)')ylabel ( 'Normalized Mixer Output '
)
legend (
' Simulated' , 'Measured' , 'Difference ' , 0)
axis( [-90,90,-1,1]
)
gridtitle ( 'Modulus 8, Measured values - Expected values')
%RSNS17 WITH SCALING
% LT Nathan York, 15 December 2000% Generates the simulated folding waveform. Two element arraysassumed.% Can accept normalized mixer output for comparison to simulatedwaveform.% Plots folding waveforms for simulated and measured data.% m = modulus; d = spacing (m) ; f = frequency
clearN=2;f=8e9; c=3e8; wavl=c/f;sf=.8746; %sqrt(3)/2k=2*pi/wavl
;
rad=pi/180;
96
% ffd is forced phase difference to align signal to required zerocrossingffd=90 %original is 90!
m=17;
% M is Dynamic RangeM=64;% nf is number of foldsnf=M/ (2*m*N)
;
% calculation of required element spacingd=nf *wavl / sf / 2
;
% start, stop, increment anglesstart=-90; stop=90; inc=0.1;N= floor ( ( stop- start) /inc) + 1;
for n=l:N;thd(n) =start+ (n-1) *inc; thr=thd(n) *rad;
arg (n) =k*d*sin ( thr)
;
% mixer outputmx(n)=cos(arg(n)+(ffd) * (pi/180) )
;
end
load rsnsll.dat;load rsnsl4.dat;load PAT9.dat;load PAT10.dat;load patlOa.dat
bothl7=[thd' mx' ] ;
save simul7.dat bothl7 -ascii;
figure (3)
holdplot(thd,mx, 'b' ) ;
% LABVIEW Output has mod 17 mixer output in second column.% Normalization technique puts normalized mixer output in thirdcolumn.plot (rsnsl4 ( : ,4) , rsnsl4 ( : , 6)
,'r'
)
hold offxlabel ( 'Angle of Arrival (degrees) ') ,ylabel ( 'Normalized Mixer Output')gridtitle ([ 'Modulus 17, with ffd = ' ,num2str (f fd) ]
)
legend (' Simulated '
,' Measured
' , )
xlabel ( 'Angle of Arrival (degrees) ')
ylabel ( 'Normalized Mixer Output')axis( [-90,90,-1,1] )
orient landscape
97
temp=rsnsl4 ( : , 6 )
;
templ=rot90 (temp)
;
lef t=tempi -mx;zero=0
;
figure (4)
holdplot ( thd,mx /
' b' ) ;
plot(rsnsl4( : ,4) , rsnsl4 ( : , 6), 'r'
)
plot (thd, left, 'g'
)
plot ( thd, zero, '
k'
)
legend (' Simulated '
,' Measured
'
,
' Difference'
, )
gridxlabel ( 'Angle of Arrival (degrees)')ylabel ( 'Normalized Mixer Output')axis( [-90,90,-1,1]
)
title ( 'Modulus 17, Measured values - Expected values')
%BinPop.m
% LT Nathan York 15 December 2000
% step size is 0.1 degrees based on minimum stepper motor resolution% simulates the entire transfer function% 1- determines number of active comparators at each step for bothmodulus% 2- determine bin number% 3- determine angle of arrival
% Also calculates bin population and quantization error.
% Load either the simulated data (simul7.dat, simu8.dat)% or the experimental data - SEE BELOW (ALSO SEE LINE 155-156)% Uses predicted thresholds calculated from cosine of equally spacedanglesa**********************************
format long;clear;sum_error_squared=0 ; Excess_RE=0
;
sf=sqrt (3) /2;
%load simul7.dat%load simu8.dat%dfl=simul7;
load rsnsl4.datdfl=[rsnsl4(: ,4) rsnsl4 ( : , 6) ] ;
ft*********************************
point_num=1801
;
Sum_AE=0;
%comparators mod 17
98
for i=l :point_num
c_ml7 i, 1] )
c_ml7 i
,
2])
c_ml7 i
,
3])c_ml7 i, 4])c_ml7 i, 5])c_ml7 i
,
6])
c_ml7 i, 7])c_ml7 i
,
8])c_ml7 i, 9])
c_ml7 i
,
10]
c_ml7 i
,
11]
c_ml7 i
,
12]
c_ml7 i
,
13]
c_ml7 i
,
14]
c_ml7 i
,
15]
c_ml7 i
,
16]
c_ml7 i
,
17]
c_ml7 i
,
18]
= 1
-0
=
=
=
=
=
=0=
)=0)=0
)=0)=0)=0
)=0
)=0
)=0)=0
end
%SIMULATION THRESHOLDStl = cos(33*pi/34)t2 = cos(31*pi/34)t3 = cos(29*pi/34)t4 = cos(27*pi/34)t5 = cos(25*pi/34)t6 = cos(23*pi/34)t7 = cos(21*pi/34)t8 = cos(19*pi/34)t9 = cos(17*pi/34)tlO = cos(15*pi/34)til = cos(13*pi/34)tl2 = cos(ll*pi/34)tl3 = cos(9*pi/34)tl4 = cos(7*pi/34)tl5 = cos(5*pi/34)tl6 = cos(3*pi/34)tl7 = cos (pi/34)
;
for i=l :point_num
% all the data points% cl is the bottom comparator% tl is the threshold voltage for cl etc
if (dfl(i, [2] ) )> tlC_ml7(i, [2] ) = 1;
elsec_ml7(i, [2] ) = 0;
end
99
if (dfl(i. [2]))c_ml 7 (
i
[3])
elsec_ml7 (
i
[3])
end
if (dfl(i, [2]))c_ml7 (i [4])
elsec_ml7 (i [4])
end
if (dfl(i, [2]))c_ml7 (i [5])
elsec_ml7 (i [5])
end
if (dfl(i. [2]))c_ml7 (i [6])
elsec_ml7 (
i
[6])
end
if (dfl(i, [2]))c_ml7 (i [7])
elsec_ml7 (i [7])
end
if (dfl(i. [2]))c_ml7 (i [8])
elsec_ml7 (i [8])
end
if (dfl(i. [2]))c_ml 7 (
i
[9])
elsec_ml7 (i [9])
end
if (dfl(i, [2]))c_ml 7 (
i
[10]else
c_ml7 (i [10]
end
if (dfl(i, [2]))c_ml 7 (
i
[11]
elsec_ml7 (i [11]
endif (dfl(i [2])
> t2
= 1;
= 0;
> t3= 1;
= 0;
> t4= 1;
= 0;
> t5= 1;
= 0;
> te= 1;
= 0;
> t7= 1;
= 0;
> t8= 1;
= 0;
> t9
) = 1;
) = 0;
> tlO
) = 1;
) = 0;
)> til
100
c_ml7(i, [12] ) = 1;
elseC_ml7 (i, [12] ) = 0;
end
if (dfl(i, [2] ) )> tl2c_ml7 (i, [13] ) = 1;
elsec_ml7(i, [13] ) = 0;
end
if (dfl(i, [2] ) )> tl3c_ml7(i, [14] ) = 1;
elsec_ml7(i, [14] ) = 0;
end
if (dfl(i, [2] ) )> tl4c_ml7(i, [15] ) = 1;
elseC_ml7(i, [15] ) = 0;
end
if (dfl(i, [2] ) )> tl5c_ml7(i, [16] ) = 1;
elsec_ml7 (i, [16] ) - 0;
end
if (dfl(i, [2] ) )> tl6c_ml7(i, [17] ) = 1;
elsec_ml7(i, [17] ) = 0;
end
if (dfl(i, [2] ) )> tl7c_ml7(i, [18] ) = 1;
elsec_ml7(i, [18] ) = 0;
end
end%encoding the thermometer code into a decimal number.%rsns_ml7 contains the number of comparators on at each time%step
for j=l :point_num
A=c_ml7(j, [2]
)
B=c_ml7(j, [3]
)
C=c_ml7(j, [4]
)
D=c_ml7(j, [5]
)
E=c_ml7(j, [6]
)
F=c_ml7(j, [7]
)
101
end
G=c_ml7(
j
H=c_ml7 (
j
I=c_ml7(jJ=c_ml7
(
j
K=c_ml7(
j
L=c_ml7(
j
M=c_ml7 (
j
N=c_ml7(
j
0=c_ml7(
j
P=c_ml7 (
j
Q=c_ml7(
j
[8]);[9]);[10])
[11])
[12])
[13])
[14])
[15])
[16])
[17])
[18])
Z=A+B+C+D+E+F+G+H+I+J+K+L+M+N+0+P+Q;
rsns_ml7 ( j ) = Z;
xarray= [-90: 180/1800: 90]
;
figure (6)
plot (xarray , rsns_ml7 ( : ) ) , gridxlabel ( 'Angle of Arrival (degrees) 1
)
ylabel ( 'Number of Comparators'
)
% title (' Number of Comparators on each time step for mod 17')
axis( [-90 90 -1 17]
)
clear dfl
%dfl=simu8;
dfl=[rsnsl4(:,l) rsnsl4 ( : , 3) ]
;
%***************•*****************
%comparators mod 8
for i=l :point_num
c_m8 ( i
,
c_m8 ( i
,
c_m8 ( i
,
c_m8 ( i
,
c_m8 ( i
,
c_m8 ( i
,
c_m8 ( i
,
c_m8 ( i
,
c_m8 ( i
,
end
tl = cos(15*pi/16)t2 = cos(13*pi/16)t3 = cos(ll*pi/16)t4 = cos(9*pi/16)
;
t5 = cos(7*pi/16)
;
[1] = i;
[2] = 0;
[3] = 0;
[4] = 0;
[5] = 0;
[6] = 0;
[7] = 0;
[8] = 0;
[9] = 0;
102
t6 = cos(5*pi/16)
;
t7 = cos(3*pi/16)
;
t8 = cos (pi/16)
;
for i=l :point_num
% all the data points% cl is the bottom comparator% tl is the threshold voltage for cl etc
if (dfl [i / .2))
c_m8 [i
,
2])else
c_m8 'i
,
2])
end
if (dfl i, 2])
c_m8 i. 3])else
c_m8 i, 3])
end
if (dfl i
,
2])c_m8 i
,
4])else
c_m8 i
,
4])end
if (dfl i
,
2])
c_m8 i
,
5])
elsec_m8 i, 5])
end
if (dfl i. 2])c_m8 i
,
6])else
c_m8 i
,
6])end
if (dfl i
,
2])c_m8 i
,
7])
elsec_m8 i, 7])
end
if (dfl i, 2])c_m8 i, 8])
elsec_m8 i
,
8])end
if (dfl i, .2])
c_m8 i, :9])
> tl= 1;
= 0;
)> t2
= 1;
= 0;
)> t3= 1;
= 0;
)> t4= 1;
= 0;
)> t5= 1;
= 0;
> t6= 1;
= 0;
)> t7= 1;
= 0;
)> t8= 1;
else
103
c_m8 ( i , [ 9 ] ) = ;
end
end
%encoding the thermometer code into a decimal number.%rsns_m8 contains the number of comparators on at each time%step
for j=l :point_num
A=c_m8(
j
[2])
B=c_m8 (
j
[3])
C=c_m8 (
j
[4])
D=c_m8(
j
[5])
E=c_m8 (
j
[6])
F=c_m8 ( j
,
[7])
G=c_m8( j
,
[8])
H=c_m8 ( j
,
[9])
Z=A+B+C+D+E+F-kG+H
rsns_m8 (j ) =Z;
end
figure (7)
plot (xarray , rsns_m8 ( : ) ,' r '
) , gridxlabel ( 'Angle of Arrival (degrees)')ylabel ( 'Number of Comparators')% title ( 'Number of Comparators on each time step for m8 '
)
axis( [-90 90 -1 8]
)
figure (8)
hold onplot (xarray, rsns_ml7 ( : ) , 'b' )
plot (xarray, rsns_m8 ( : )
,
'
r'
)
hold offxlabel ( 'Angle of Arrival (degrees) ')
ylabel ( 'Number of Comparators '
)
legend ('Mod 8', 'Mod 17 ',0)
%title ( 'Number of Comparators on each time step for mod 17 & mod 8')
axis( [-90 90 17]
)
orient landscape
% integers for trans_funct filebin=-l; bin_ctr=l; start_th=-90; end_th=0; sum_error_squared=0;
% Bin mapping for thermometer code. doa is the bin number.for s=l :point_num
if (rsns_ml7 (s) ==10 & rsns_m8 (s) ==6)
doa(s) = 0;
elseif (rsns_ml7 (s) ==10 & rsns_m8 (s) ==5)
104
doa ( s ) = 1
;
elseif (rsns_ml7 (s) ==11 & rsns_m8 (s) ==5)
doa ( s ) = 2
;
elseif (rsns_ml7 (s) ==11 & rsns_m8 (s) ==4)
doa ( s ) = 3
;
elseif (rsns_ml7 (s) ==12 & rsns_m8 (s) ==4)
doa(s) =4;
elseif (rsns_ml7 (s) ==12 & rsns_m8 (s) ==3)
doa ( s ) = 5
;
elseif (rsns_ml7 (s) ==13 & rsns_m8 (s) ==3)
doa ( s ) = 6
;
elseif (rsns_ml7 (s) ==13 & rsns_m8 (s) ==2)
doa ( s ) = 7
;
elseif (rsns_ml7 (s) ==14 & rsns_m8 (s) ==2
)
doa ( s ) = 8
;
elseif (rsns_ml7 (s) ==14 & rsns_m8 (s) ==1)
doa(s) = 9;
elseif (rsns_ml7 (s) ==15 & rsns_m8 (s) ==1)
doa(s) = 10;
elseif (rsns_ml7 (s) ==15 & rsns_m8 (s) ==0)
doa(s) = 11;
elseif (rsns_ml7 (s) ==16 & rsns_m8 (s) ==0)
doa(s) =12;
elseif (rsns_ml7 (s) ==16 & rsns_m8 (s) ==1)
doa(s) = 13;
elseif (rsns_ml7 (s) ==17 & rsns_m8 (s) ==1)
doa(s) = 14;
elseif (rsns_ml7 (s) ==17 & rsns_m8 (s) ==2)
doa(s) = 15;
elseif (rsns_ml7 (s) ==16 & rsns_m8 (s) ==2)
doa ( s ) = 16;
elseif (rsns_ml7 (s) ==16 & rsns_m8 (s) ==3
)
doa(s) = 17;
elseif (rsns_ml7 (s) ==15 & rsns_m8 (s) ==3)
doa(s) = 18;
elseif (rsns_ml7 (s) ==15 & rsns_m8 (s) ==4)
doa(s) = 19;
105
elseif (rsns_ml7(sdoa(s) = 20;
elseif (rsns_ml7(sdoa ( s ) = 21;
elseif (rsns_ml7(sdoa(s) = 22;
elseif (rsns_ml7(sdoa(s) = 23;
elseif (rsns_ml7(sdoa(s) = 24;
elseif (rsns_ml7(sdoa(s) = 25;
elseif (rsns_ml7(sdoa(s) = 26;
elseif (rsns_ml7(sdoa ( s ) = 27;
elseif (rsns_ml7(sdoa(s) = 28;
elseif (rsns_ml7(sdoa(s) = 29;
elseif (rsns_ml7(sdoa(s) = 30;
elseif (rsns_ml7(sdoa(s) = 31;
elseif (rsns_ml7(sdoa ( s ) = 32;
elseif (rsns_ml7(sdoa(s) = 33;
elseif (rsns_ml7(sdoa ( s ) = 34;
elseif (rsns_ml7(sdoa(s) = 35;
elseif (rsns_ml7(sdoa ( s ) = 36;
elseif (rsns_ml7 (s
doa(s) = 37;
==14 & rsns_m8 (s) ==4)
==14 & rsns_m8 (s)==5i
==13 & rsns_m8(s)==5)
==13 & rsns_m8 (s) ==S.
= = 12 Sc rsns_m8 (s)= = 6)
==12 & rsns_m8 (s) ==7)
==11 & rsns_m8 (s)==7;
==11 & rsns_m8 (s) ==8)
==10 & rsns_m8 (s) ==8)
==10 & rsns_m8 (s) ==7;
==9 & rsns_m8 (s) ==7)
==9 & rsns_m8 (s) ==6)
==8 & rsns_m8 (s) ==6)
==8 Sc rsns_m8 (s)==5)
==7 Sc rsns_m8 (s) ==5)
==7 Sc rsns_m8 (s) = = 4)
==6 Sc rsns_m8 (s) = = 4)
==6 Sc rsns_m8 (s) = = 3 )
106
elseif (rsns_ml7 (s) ==5 & rsns_m8 (s) ==3
)
doa(s) = 38;
elseif (rsns_ml7 (s) ==5 & rsns_m8 (s) ==2)
doa(s) = 39;
elseif (rsns_ml7 (s) ==4 & rsns_m8 (s) ==2)
doa(s) = 40;
elseif (rsns_ml7 (s) ==4 & rsns_m8 (s) ==1)
doa(s) = 41;
elseif (rsns_ml7 (s) ==3 & rsns_m8 (s) ==1)
doa(s) = 42;
elseif (rsns_ml7 (s) ==3 & rsns_m8 (s) ==0)
doa(s) = 43;
elseif (rsns_ml7 (s) ==2 & rsns_m8 (s) ==0)
doa(s) = 44;
elseif (rsns_ml7 (s) ==2 & rsns_m8 (s) ==1)
doa(s) = 45;
elseif (rsns_ml7 (s) ==1 & rsns_m8 (s) ==1)
doa ( s ) = 46;
elseif (rsns_ml7 (s) ==1 & rsns_m8 (s) ==2)doa(s) = 47;
elseif (rsns_ml7 (s) ==0 & rsns_m8 (s) ==2)
doa(s) = 48;
elseif (rsns_ml7 (s) ==0 & rsns_m8 (s) ==3
)
doa(s) = 49;
elseif (rsns_ml7 (s) ==1 & rsns_m8 (s) ==3
)
doa(s) = 50;
elseif (rsns_ml7 (s) ==1 & rsns_m8 (s) ==4)
doa ( s ) = 51;
elseif (rsns_ml7 (s) ==2 & rsns_m8 (s) ==4)
doa(s) = 52;
elseif (rsns_ml7 (s) ==2 & rsns_m8 (s) ==5)doa(s) = 53;
elseif (rsns_ml7 (s) ==3 & rsns_m8 (s) ==5)
doa(s) = 54;
elseif (rsns_ml7 (s) ==3 & rsns_m8 (s) ==6)
doa ( s ) = 55;
elseif (rsns_ml7 (s) ==4 & rsns_m8 (s) ==6)
107
doa ( s ) = 56;
elseif (rsns_ml7 (s) ==4 & rsns_m8 (s) ==7)
doa(s) = 57;
elseif (rsns_ml7 (s) ==5 & rsns_m8 (s) ==7)
doa(s) = 58;
elseif (rsns_ml7 (s) ==5 & rsns_m8 (s) ==8)
doa(s) = 59;
elseif (rsns_ml7 (s) ==6 & rsns_m8 (s) ==8)
doa(s) = 60;
elseif (rsns_ml7 (s) ==6 & rsns_m8 (s) ==7
)
doa ( s ) = 61;
elseif (rsns_ml7 (s) ==7 & rsns_m8 (s) ==7)
doa(s) = 62;
elseif (rsns_ml7 (s) ==7 & rsns_m8 (s) ==6)
doa ( s ) = 63;
elsedoa(s) = 100; % if the vector does not map, 100 is the error
code
end
% Uses the formula asin [ ( #-34 ) /64] to find bin centergamma=doa (s) +1
;
bin_center(s)=2*asin( (gamma-32) *sf/64) *180/3.1415;
% if
if doa(s)==100bin_center (s) =0; % if the vector did not map, reports as
broadsideendangle_error (s) =bin_center (s) - (s-900) /10;
%Calculation of RMS Reporting Error%if statement eliminates excessive errors and subs with mean error.if abs (angle_error (s) ) <= 15
Sum_AE = Sum_AE + angle_error (s) *angle_error (s)
;
Excess_RE=Excess_RE+l
;
endend
z=0:63;
for 1=1:64bin_count ( 1 ) =0
;
end
108
for lb =1:1801if doa(lb)==100
bc=l;else
bc=doa(lb)+l;endbin_count ( be ) =bin_count ( be ) + 1
;
end
figure (9)
holdplot (z,bin_count, 'b' ) , axis( [0,63, 0, 60] ) ,
gridhold offxlabel('Bin Number')ylabel('Bin Population')
figure (10)
plot (xarray,doa, *b' ) ,axis( [-90, 90, 0, 65])xlabel ( 'Angle of Arrival (degrees)')ylabel (
' Bin Number '
)
grid
figure (11)
plot (xarray, bin_center, 'b') ,gridxlabel ( 'Angle of Arrival (degrees)')ylabel (' Reported Angle of Arrival (degrees) ')
figure (12)
plot (xarray, angle_error, 'b'
) ,grid
axis( [-60,60,-10,10] )
;
ylabel ( 'Reporting Error (degrees)'
)
xlabel ( 'Angle of Arrival (degrees)')
% end of program.
% phase_error .m
% Determines the phase error between a predicted and measured waveform% 2 channel input% Written by Dave Wickersham
clear all;
load rsnsl4.dattheta=[rsnsl4 (: ,1) ]
;
dv8=[rsnsl4( : ,3) ] ;
dvl7=[rsnsl4( : ,6) ] ;
md=length (dv8)
;
% constants and design variables
109
N=2;f=8e9; c=3e8; wavl=c/f;sf=2/sqrt (3)
;
k=2*pi/wavl
;
M=64;nf=M/(2*N);% nf is number of folds (not really, no modulus in thisequation)dw=nf/2; % new design for mixer ouputs
FirstMin=0 ; FirstMax=0 ; SecMin=0 ; SecMax=0 ; Maxl7=0 ;Minl7=0
;
rad=pi/180;
thet_r= theta * rad
;
ffd8=45; %45ffdl7=90; %90
e8_sq=0; el7_sq=0; cnt8=0; cntl7=0;d8=dw*wavl*sf /8;dl7=dw*wavl*sf/17;
%subroutine to find local max and min% works because I know about where the max and min will fall% used to get the right quadrant for the arccos%Mod 8
for i=(md-l)/6: (md-1) /2
if dv8 (i)<FirstMinFirstMin=dv8 (i)
;
IndexlMin=i;end
end
for i= (md-1) /3: (md-1) 12
if dv8 (i) >FirstMaxFirstMax=dv8(i)
;
IndexlMax=i;end
end
for i=(md-l)/2:2*(md-l)/3if dv8 (i)<SecMin
SecMin=dv8 ( i )
;
Index2Min=i;end
end
for i=2* (md-1) /3:8* (md-1) /9
if dv8 (i) >SecMaxSecMax=dv8 (i)
;
Index2Max=i;end
end
%Mod 17
110
for i=(md-l)/2:5*(md-l)/6if dvl7 (i)<Minl7
Minl7=dvl7 (i)
;
Indexl7Min=i
;
endend
for i=(md-l) /6: (md-1) /2
if dvl7 (i)>Maxl7Maxl7=dvl7(i)
;
Indexl7Max=i ;
endend
for n=l:mddelt8 (n)=k*d8*sin(thet_r (n) )+(f fd8) *rad; %delt8 is the simulated
total angle in radunwrap (delt8 (n) ) ;
%while delt8(n)>pi% delt8(n)=delt8(n) -2*pi;%end%while delt8(n)<-pi% delt8(n)=delt8(n)+2*pi;%end
dm8 (n) =acos (dv8 (n) ) ; %dm8 is measured data's total angle in rad% unwrap ( dm8 ( n )
;
if (n>=IndexlMin) & (n<=IndexlMax)dm8 (n)=-dm8 (n)
;
endif (n>=Index2Min) & (n<=Index2Max)
dm8 (n)=-dm8(n)
;
end
phi8 (n) = (delt8 (n) -dm8 (n) )
;
% unwrap phi8(n);while phi8(n)>pi
phi8 (n) =phi8(n) -2*pi;endwhile phi8(n)<-pi
phi8 (n) =phi8(n) +2*pi;end
deltl7(n)=k*dl7*sin(thet_r(n) )+(ffdl7) *rad; %deltl7 is thesimulated total angle in rad
% unwrap (deltl7(n) )
;
while deltl7(n)>pideltl7 (n) =deltl7 (n) -2*pi;
endwhile deltl7 (n) <-pi
111
deltl7 (n) =deltl7 (n) +2*pi;end
dml7 (n) =acos (dvl7 (n) ) ; %dml7 is measured data's total angle inrad
if n>=Indexl7Mindml7(n)=-dml7(n)
;
end
if n<=Indexl7Maxdml7(n)=-dml7(n)
;
end
phil7 (n) = (deltl7 (n) -dml7 (n) )
;
while phil7(n)>piphil7 (n)=phil7 (n)-2*pi;
endwhile phil7(n)<-pi
phil7 (n) =phil7 (n) +2*pi;end
end
phi8=phi8/rad;phil7=phil7/rad;
for i=l:md %phi contributes to RMS erroronly if it is real
e8_sq = e8_sq + (real (phi8 (i) ) *real (phi8 (i) ) )
;
el7_sq = el7_sq+ (real (phil7 (i) ) *real (phil7 (i) ) )
;
end
rms8=sqrt (e8_sq) / (md-1)
;
%calculate RMS phase error for eachchannelrmsl7=sqrt (el7_sq) / (md-1)
;
disp(['RMS Phase Error of Mod 8 is ' ,num2str (rms8) ,
' '])
disp(['RMS Phase Error of Mod 17 is ' ,num2str (rmsl7 )
,
' '])
figure (5)
hold%plot(pl2( :,4) ,pl2(: ,8) , '--r'
)
plot (theta,phi8, 'b' )
;
plot ( theta,phil7 ,'
r' )
;
axis( [-90,90,-90,90]
)
hold offlegend (
' Mod 8'
,' Modl7 ' , )
xlabel ( 'Angle of Arrival (degrees) ') ,ylabel (' Phase Error (degrees)');grid
112
%title( [' Phase Error between Simulated and Measured Data, Pattern 32'])orient landscape
113
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114
APPENDIX C. PRINTED CIRCUIT BOARD CONSTRUCTION
The following is a list of steps that were used to create the printed circuit boards
for this thesis. These steps can streamline the construction process for someone who is
not familiar with the process. The instructions are only valid when using the Electronic
Workbench Multisim software package and the PCB milling machine operated by the
Physics Department at NPS.
1. Start Multisim. Create and test the circuit you would like to build. Be sure to include
all power sources and grounds.
2. Select the Transfer to Ultiboard option in the Transfer pull down menu. This will
automatically start the Ultiboard program and import a parts list and netlist that is
used by Ultiboard.
3. Setup the Ultiboard workspace for your design. To do this you will have to select a
design class, board size, number of layers, and trace size. Use the defaults for all the
other options.
4. You will notice a the outlines for all the components at the top of the screen. You
will have to manually place each of the components within the board outline. Each
component will have a line ending in a circle emanating from the part's center. This
is a placement, aid which will help you determine the optimum placement for each
component. The shorter the lead the better. As you place components in the board
outline you will also notice yellow lines connecting the pins of the selected
component and others. These are your pin connections. This can help you determine
the appropriate orientation of the components.
5. Ensure that all the power connections are on the board. These are the only parts that
are not included by the Multisim program. You will need to manually add the
connectors to the board and manually add each of the pins into the correct netlist.
6. Once all the parts are in their postions save the design file and transfer the layout to
the Ultiroute program. This program will automatically route all the traces for your
115
board. In most cases, the first attempt may no complete all the traces. If this
happens, close the program and go back to the Ultiboard program. You will need to
reconfigure the location of the parts for a second run. If this happens, ensure that you
check your grid size. Ultiroute sets the gridsize to 12.5 mils by default even if the
design file uses a different grid setting. Make sure that you change the grid setting
back to its original, otherwise the design will not transfer to Ultiboard for a second
run. You need to continue this process until the board is 100% routed.
7. After the board is routed, transfer it back to the Ultiboard program. Use this program
to check for continuity, power grids, pin connections and ground lines. One tip to
make the construction easier is making all pin connections on the bottom layer. This
will prevent you from having to solder underneath a component.
8. Once this is complete, it is time to generate a Gerber file. This is a standard computer
aided manufacturing (CAM) file type for all PCB milling machines. Under the File
menu select Post Processing. Here you will be prompted to the output device or file
type. Select the Gerber RS-274-D (2.3) file type in the Photoplotter menu. Next
double-click on each of the four layers to bring up the Plot Setting Parameters.
Unselect the Extended Borders and Board Outline option. These option will cause
the software used to run the milling machine to crash. The click on the (Jo! button.
The Gerber files *.G0 and *.G1 have now been created. The click on the Drill
Targets button and add that information to the processed file.
9. Copy the .GO, .Gl and .REP files to a 3 and a half inch disk and bring the disk down
to the milling machine.
10. The milling machine is running off a 486 computer using DOS 6.0. First read the
.REP file and copy down all the apertures that are in the design file. These will have
to be manually added to the Gerber file.
11. Rename the .GO and .Gl files to TOP.GBR and BOT.GBR respectively.
12. Copy these two files to the C:\CAM directory.
13. Start the Gerber editor by typing CAM.EXE.
14. Start a new design file and load the two .GRB files in it.
116
15. The next step is to edit the aperture list. The program will prompt you to do this. Just
add the apertures from the .REP file to the list.
16. Now it is time to edit the .GBR files themselves. Evaluate the design that was
transferred from the Ultiboard program and make sure that all the traces and pads are
present. At this point you will be able to modify the trace and pad sizes. I suggest
that you use 20 mil traces and 80 by 80 mil square pads. These are the easiest to
solder to.
17. Once you are satisfied with the .GBR files, save your work and exit the program.
18. Copy TOP.GBR and BOT.GBR to C:\PBOARD\INPUT.
19. Rename TOP.GBR and BOT.GBR to LI.GBR and L2.GBR respectively.
20. Using the EDIT program in DOS, open the LI and L2 Gerber files and delete the G01
from the third line and save.
21. Type PI.BAT to start the outline converter. This program will convert the Gerber
files to machine language that will control the milling machine. The outline converter
may take up to two hours to convert a large design.
22. Once the outline converter is done, type P3.BAT. This copies the output files to the
CAM directory.
23. Run the CAM program again. This time add LIOUT, L20UT and DIOUT files to
the original design file. You will be able to check the new Gerber files against the
originals to make sure the outline converter did its job properly. Most likely, the
outline converter will miss a trace or pad. You will need to manually complete the
trace in this program. If you need to change these files, make sure you go back and
edit them to remove the G01 from the third line. Then copy the new files back to
C:\PBOARD\OUTPUT.
24. You are now ready to start milling. Type P2.BAT to start the milling program. The
program will have prompts at the bottom of the screen to help you along.
25. Place board material in milling machine.
26. Start by setting the OPS Mode to Drill.
27. Select the layer DIOUT.
117
28. Go to the Manual option to change out the drill bit and set drill depth. Use a 32 mil
drill bit, and set the drill depth so that the bit completely goes through the board
material. Once this is set, quit and return to the main menu.
29. Turn on the drill and vacuum, and close the machine cover. The select Start. Follow
the prompts to start drilling all the holes.
30. Once the holes are drilled, it is time to cut the traces. To do this set the OPS Mode to
mill and select the LIOUT layer.
31. Go to manual to change the drill bit to a milling bit. Set the depth of cut so that the
channel is 10 mils wide. A couple of test cuts in the manual mode will be required to
do this.
32. Go to Start and follow the prompts to start milling the traces.
33. Once the top layer is complete you need to cut the bottom layer. Follow the same
procedure. The L20UT layer needs to be selected as well as Mirror is ON selected.
The bit and depth should be ok so go straight to Start and begin milling the bottom
layer.
34. Now that the board has been cut you need to check the board for milling defects.
Start by sanding both sides of the board with a very fine grit sandpaper.
35. Check for continuity and grounds. Do this using a multimeter. If a ground is
detected, clean the channels with an exacto-knife. There is probably a small filing
that was not completely removed by the drill bit that is causing the ground.
36. When the board has been completely checked, it is time to stuff and solder it. Start
by making the vias (through board connections). If there are not many vias, small
pieces of wire can be soldered to both sides of the board. Another method is using
small aluminum rivets. Put the rivets in the drill holes and turn the board upside
down on a completely flat working surface. Use a punch to secure the rivet to the
bottom of the board. Make sure that there is a good connection between the rivet and
both sides of the board; otherwise you will have continuity problems. If you have
trouble getting good contact with the rivets, a drop of solder on each side will correct
the problem.
118
37. Now that the vias are complete, finish stuffing the board and soldering the pins and
components into place. One hint: solder a few pins at a time and then check for
grounds. It is very easy to accidentally jump the channel with the solder causing a
ground. If check after a few pins it will be easier to find the mistake and correct it.
38. The board is now ready to be used.
119
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120
LIST OF REFERENCES
1. M.D. Zoltowski and K.T. Wong, "ESPRTT-Based 2-D Direction Finding with a
Sparse Uniform Array of Electromagnetic Vector Sensors," IEEE Transactions on
Signal Processing, Vol. 48, No. 8, pp. 2195-2204, August 2000
2. N. Dowlut and A. Manikas, "A Polynomial Rooting Approach to Super-Resolution
Array Design," IEEE Transactions on Signal Processing, Vol. 48, No. 6, pp. 1559-
1569, June 2000
3. Y.W. Wu, S. Rhodes, and E.H. Satorius, "Direction of Arrival Estimation Via
Extended Phase Interferometry," IEEE Transactions on Aerospace and Electronic
Systems, Vol. 31, No. 1, pp. 375-382, January 1995
4. Thomas Hatziathanasiou, "Optimum Symmetrical Number System Phase Sampled
Direction Finding Antenna Architectures," Naval Postgraduate School Master's
Thesis, June 1998.
5. D. Wickersham, "Application of the Robust Symmetrical Number System to High
Resolution Direction Finding Interferometry," Naval Postgraduate School Master's
Thesis, March 2000.
6. P.E. Pace, Advanced Techniques for Digital Receivers, Artech House Inc., NorwoodMA, 2000
7. P.E. Pace, D. Styer, "High resolution encoding process for an integrated optical
analog-to-digital converter," Optical Engineering, Vol. 33, pp. 2638-2645, August
1994.
8. D. Jenn, P. Pace, T. Hatziathanasiou, "High Resolution Wideband Direction Finding
Arrays Based On Optimum Symmetrical Number System Encoding," Electronics
Letters, Vol 34, No. 11, May 28, 1998, pp. 1062-1063.
9. P. E. Pace, D. Styer and I. A. Akin, "A folding ADC preprocessing architecture
employing a robust symmetrical number system with Gray-code properties," IEEETransactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol.
47, No. 5, May 2000.
10. J. Helszajn, Passive and Active Microwave Circuits, John Wiley & Sons, New York,
1976, pp. 215-230
121
11. P. Horowitz, and W. Hill, The Art of Electronics, Cambridge University Press, NewYork, 1989, pp.565-671
12. S.S. Sedra, and K.C Smith, Microelectronic Circuits, Oxford University Press, NewYork, 1998
13. C.H., Roth, Digital Systems Design Using VHDL, PWS Publishing Company, Boston,
1998, pp. 85-100
14. J.R Armstrong, and F.G. Gray, VHDL Design Representation and Synthesis, Prentice
Hall PTR, Upper Saddle River, NJ, 2000, pp 315-323
122
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Ft. Bel voir, VA 22060-6218
2. Dudley Knox Library
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411 DyerRd.
Monterey, Ca 93943-5101
3. Chairman, Code PH
Department of Physics
Naval Postgraduate School
Monterey, CA, 93943-5121
4. Professor Phillip E. Pace, Code EC/PC
Department of Electrical and Computer Engineering
Naval Postgraduate School
Monterey, CA, 93943-5121
5. Professor D. Scott Davis, Code PH/DV
Physics Department
Naval Postgraduate School
Monterey, CA, 93943-5121
123
6. Professor David C. Jenn, Code EC/JN 1
Department of Electrical and Computer Engineering
Naval Postgraduate School
Monterey, CA, 93943-5121
7. Director, Center for Reconnaissance Research 2
(Attention: Professor John Powers, Code EC/PO)
Naval Postgraduate School
Monterey, CA, 93943-5121
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9. Professor David Styer 1
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10. Lieutenant David Wickersham 1
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Norfolk VA 23507
11. Lieutenant Nathan S. York 1
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Belmont, MA, 02478
124
32 4T H8t11/02 22527-200 nlb