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This tutorial offers A short motivation for C based design flow A brief introduction to the most important SystemC 1.0.x
language elements A very short overview on refinement for synthesis A simple example program
This tutorial does not provide a complete treatment of the SystemC language cover system level modeling with SystemC 2.0
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SystemC Introduction1
TopicUnit
Language Elements of SystemC2
SystemC and Synthesis3
Simple Example4
Resources5
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Problems:Written specifications are incomplete and inconsistentTranslation to HDL is time consumingand error prone
C/C++C/C++
1. Conceptualize2. Simulate in C++
3. Write specification document
4. Hand over specification document HDLHDL
5. Understand6. (Re)Implement in HDL7. (Re)Verify
8. Synthesize from HDL
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C/C++C/C++
1. Conceptualize2. Simulate in C++3. Write specification document
4. Hand overExecutable specification
Testbench
Written specification
C/C++C/C++C/C++
5. Understand6. Refine in C++7. Verify reusing testbenches8. Synthesize from C++
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SystemC supports Hardware style communication
Signals, protocols, etc.
Notion of time
Time sequenced operations. Concurrency
Hardware and systems are inherently concurrent, i.e. they operate inparallel.
Reactivity Hardware is inherently reactive, it responds to stimuli and is in
constant interaction with its environment, which requires handling ofexceptions.
Hardware data types
Bit type, bit-vector type, multi-valued logic type, signed and unsignedinteger types and fixed-point types.
Integrated Simulation Kernel
All these features are not supported by C++ as is
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UTFUTF
TFTF
Partition
BehavioralBehavioral
RTLRTL
abstract
RTOS
abstractRTOS
target
code
target
code NetlistNetlist
Refine
Refine
Refine
Refine
System/ Architectural Levelnot synthesizableevent drivenabstract communication
abstract data types
Behavioral Levelsynthesizableclocked
I/O cycle accuratealgorithmic description
RT Levelsynthesizableclocked
FSMdata path
Software Hardware
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class libraryand
simulation kernel source files for systemand testbenches
yourstandardC/C++ development
environment
compiler
linker
debugger
libraries
header files
exec
utable
specificat
ion
.
.
.
....
.
.
.
.
executable = simulatorsim.x
ASIC
IP-Core
Interface
DSP
make
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Module
Algorithm
Channel (implements I/F)Channel (implements I/F)
InterfaceInterface
Port (accesses a channels I/F)Port (accesses a channels I/F)
Process (reads data from input portsand writes data to output ports)
Process (reads data from input portsand writes data to output ports)
SystemC 2.x
Module
Port
Interface
Channel Process
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main.cppmain.cpp
stimgen.cppstimgen.cpp
stimgen.hstimgen.h
algo.cppalgo.cpp
algo.halgo.h
monitor.cppmonitor.cpp
monitor.hmonitor.h
DUT
in1
in2out
Response
Monitorre
Stimulus
Generator
a1
a2
main.cpp
clk
in1 in2
out
Algorithm
DUT
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VHDL SystemC
Hierarchy entity module
Connection port port
Communication signal signal
Functionality process process
Test Bench object orientation
System Level channel, interface, event
abstract data types
I/O simple file I/O C++ I/O capabilities
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SystemC Introduction1
TopicUnit
Language Elements of SystemC2
SystemC and Synthesis3
Simple Example4
Resources5
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TopicUnit
Language Elements of SystemC2
Data Types2.1
Processes2.2
Hierarchy2.3
Modules, Ports and Signals2.1
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C++ built in data types may be used but are not adequate tomodel Hardware. long, int, short, char, unsigned long, unsigned int,
unsigned short, unsigned char, float, double, long double,
and bool.
SystemCTMprovides other types that are needed for Systemmodeling. Scalar boolean types: sc_logic, sc_bit Vector boolean types:sc_bv, sc_lv Integer types: sc_int, sc_uint,
sc_bigint, sc_biguint
Fixed point types: sc_fixed, sc_ufixed
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Hint: You may use a profiling tool, which tells you, how muchtime you spent in which function call, to control simulationspeed.
To get fast simulations, you have to choose the right data type
use builtin C/C++ data types as much as possibleuse sc_int/sc_uint integer with up to 64 bits model arithmetic and logic operations
use sc_bit/sc_bv arbitrary length bit vector
model logic operations on bit vectors two valued logic
use sc_logic/sc_lv 4 valued logic vectors model tri-state behavior
Fastest
Slowest
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Hint: You may use a profiling tool, which tells you, how muchtime you spent in which function call, to control simulationspeed.
To get fast simulations, you have to choose the right data type
use sc_bigint/sc_biguint integer with arbitrary length use to model arithmetic operations on large bit vectors ineffective for logic operations
use sc_fixed/sc_ufixed
arbitrary precision fixed point use to model fixed point artihmetic ineffective for logic operations
Fastest
Slowest
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TopicUnit
Language Elements of SystemC2
Data Types2.1
Processes2.2
Hierarchy2.3
Modules, Ports and Signals2.1
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A module is a container. It is the
basic building block of SystemC
Similar to VHDL entity
Module interface in the header file
(ending .h)
Module functionality in theimplementation file (ending .cpp)
Module contains: Ports
Internal signal variables
Internal data variables Processes of different types
Other methods
Instances of other modules
Constructor
main.cppmain.cpp
stimgen.cppstimgen.cpp
stimgen.hstimgen.h
algo.cppalgo.cpp
algo.halgo.h
monitor.cppmonitor.cpp
monitor.hmonitor.h
DUT
in1
in2
outResponseMonitor
reStimulusGenerator
a1
a2
main.cpp
clk
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Syntax:
SC_MODULE(module_name){
// body of module
};
Syntax:SC_MODULE(module_name){
// body of module
};
EXAMPLE:
SC_MODULE(my_module) {
// body of module
};
EXAMPLE:
SC_MODULE(my_module) {
// body of module
};
Code in header file:
my_module.h
Code in header file:my_module.h
Note: SC_MODULEis a macro for
struct module_name : sc_module
Note the semicolon at theend of the module definition
Note the semicolon at the
end of the module definition
SC_MODULE{
Ports
Signals Variables Constructor Processes
Modules};
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Module
Instance
Module
Instance
Module
Instance
Module
Instance
ProcessProcess
Other
Method
Other
Method
Signal connecting modules (declared inmodule)Signal connecting modules (declared inmodule)
Ports bound directly toeach other (no signal)
Ports bound directly toeach other (no signal)
PortsPorts
Process can read/write
ports and signals
Process can read/writeports and signals
Other methods canread/write ports and signalsOther methods canread/write ports and signals
MODULE
SC_MODULE{
Ports
Signals Variables Constructor Processes
Modules};
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Ports are the external interface of a module Pass information to and from a module
There are three different kinds of ports
input
output inout
Ports are always bound to signals
exception:port-to-port binding (explained later)
Ports are members of the module
Each port has a data type
passed as template parameter
DUT
in1
in2
outResponseMonitor
reStimulusGenerator
a1
a2
main.cpp
clk
SC_MODULE{
Ports
Signals Variables Constructor Processes
Modules};
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Ports have to be declared inside a module
The direction of the port is specified by the port type
input: sc_in
output: sc_out inout: sc_inout
The data type is passed as template parameter
Declaration as data members of the module:SC_MODULE(my_mod) {
sc_in port_name;
sc_out port_name;
sc_inout port_name;
};
t_data:
data type of the port
Declaration as data members of the module:SC_MODULE(my_mod) {
sc_in port_name;
sc_out port_name;
sc_inout port_name;
};
t_data:
data type of the port
SC_MODULE{
Ports
Signals Variables Constructor Processes
Modules};
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Signals are used for communication Exchange of data in a concurrent execution semantics
between modules
between processes
There is only one kind of signal Signals always carry a value
Signals need not necessarily be bound to ports
may also be used for communication between processes
Signals may be
members of a module (used for internal communication)
used at top-level to connect the modules
Each signal has a data type
passed as template parameter
SC_MODULE{
Ports
Signals Variables Constructor Processes
Modules};
DUT
in1
in2
outResponseMonitor
reStimulusGenerator
a1
a2
main.cpp
clk
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Signals are declared inside a module or at top level There is only one type of signal
sc_signal
The data type is passed as template parameter
Declaration as data members of the module:
SC_MODULE(my_mod) {sc_signal signal_name;
};
t_data:
data type of the signal
Declaration as data members of the module:
SC_MODULE(my_mod) {sc_signal signal_name;
};
t_data:
data type of the signal
SC_MODULE
{
Ports
Signals Variables Constructor Processes
Modules};
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SC_MODULE(module_name) {
// ports
sc_in a;sc_out b;
sc_inout c;
// signals
sc_signal d;
sc_signal e;
sc_signal f;
// rest
};
SC_MODULE(module_name) {
// ports
sc_in a;
sc_out b;
sc_inout c;
// signals
sc_signal d;
sc_signal e;sc_signal f;
// rest
};
Declaring ports and signals within a module ports and signals are data members of the module
good style to declare
ports at the beginning of the module
signals after port declaration
Note: a space isrequired by the C++compiler
Note: a space isrequired by the C++compiler
SC_MODULE
{
Ports
Signals Variables Constructor Processes
Modules};
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recommendedrecommended
To read a value from a port or signal use assignment use the .read() method (recommended)
To write a value to a port or signal use assignment use the .write() method (recommended)
The usage of .read()and .write()avoids implicit type conversion,
which is a source of many compile time errors
sc_signal sig;
int a;
...
a = sig;
sig = 10;
sc_signal sig;
int a;
...
a = sig;
sig = 10;
sc_signal sig;
int a;
...
a = sig.read();
sig.write(10);
sc_signal sig;
int a;
...
a = sig.read();
sig.write(10);
SC_MODULE
{
Ports
Signals Variables Constructor Processes
Modules};
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Example:
SC_MODULE(count) {
// ports & signals not shown
int count_val; // internal data stroage
sc_int mem[512] // array of sc_int
// Body of module not shown
};
Example:
SC_MODULE(count) {
// ports & signals not shown
int count_val; // internal data stroage
sc_int mem[512] // array of sc_int
// Body of module not shown
};
Data variables are member variables of a module any legal C/C++ and SystemC/user defined data type
internal to the module
should not be used outside of the module useful to store the internal state of a module
e.g. usage as memory
SC_MODULE
{
Ports
SignalsVariables Constructor Processes
Modules
};
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Each module has a constructor
Called at the instantiation of the module
initialize internal data structure (e.g. check port-signalbinding)
initialize all data members of the module to a known state
Instance name passed as argument
useful for debugging/error reporting
Processes are registered inside the constructor (morelater)
Sub-modules are instanciated inside the constructor(more later)
SC_MODULE
{
Ports
SignalsVariablesConstructor Processes
Modules
};
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TopicUnit
Language Elements of SystemC2
Data Types2.1
Processes2.2
Hierarchy2.3
Modules, Ports and Signals2.1
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Functionality of a SystemC model is described in processes.
Processes are member functions of a module. They are registered
to the SystemC simulation kernel. Processes are called by the simulation kernel, whenever a signal in
their sensitivity list is changing. Some processes execute when called and return control to the calling
function (behave like a function).
Some processes are called once, and then can suspend themselvesand resume execution later (behave like threads).
Processes are not hierarchical Cannot have a process inside another process (use module for
hierarchical design)
SC_MODULE
{
Ports
SignalsVariablesConstructorProcesses
Modules
};
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Processes use signals to communicate with each other. Dont use global variables- may cause order dependencies in
code (very bad).
Processes use timing control statements to implementsynchronization and writing of signals in processes (explainedlater).
Process and signal updates follow the evaluate-updatesemantics of SystemC.
Processes are registered to the simulation kernel within themodules constructor.
SC_MODULE
{
Ports
SignalsVariablesConstructorProcesses
Modules
};
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SC_METHOD (sc_async_fprocess)process executes everything and wakes up at next eventgood for modeling combinational logicsynchronous logic is sensitive to clock edge
SC_THREAD (sc_async_tprocess)execution is suspended on wait() until next event
SC_CTHREAD (sc_sync_tprocess)execution is suspended on wait()until next active clock edge
within one process can be only registers sensitive to one clockedge
SC_MODULE
{
Ports
SignalsVariablesConstructorProcesses
Modules
};
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Asynchronous Function Process SC_METHOD: Is sensitive to a set of signals
This set is called sensitivity list
May be sensitive to any change on a signal May be sensitive to the positive or negative edge of a boolean
signal
Is invoked whenever any of the inputs it is sensitive to changes. Once an asynchronous function processis invoked:
Entire body of the block is executed. Instructions are executed infinitely fast (in terms of internal simulation
time). Instructions are executed in order.
Processes
SC_METHODSC_THREADSC_CTHREAD
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Asynchronous Function Process SC_METHOD: Model combinational logic
multiplexing, bit extraction, bit manipulation, arith. operations...
Model sequential logic use a SC_METHODprocess sensitive to only on clock edge to update the
registers use another SC_METHODprocess sensitive to all values to be read within
this process to calculate new values
Monitor signals as part of a testbench
Use for RT level modeling
Model event driven systems (architectural level)
Processes
SC_METHODSC_THREADSC_CTHREAD
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To define the sensitivity list for any process type use sensitivewith the ()operator
takes a single port or signal as an argument e.g. sensitive(sig1); sensitive(sig2); sensitive(sig3);
sensitivewith stream notation (operator
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SC_MODULE( my_module ) { sc_in_clk clk;
sc_in reset_n;
sc_in in1;
sc_in in2;
sc_out out1;
sc_out out2;
sc_signal sig1;
sc_signal sig2;
int _internal;
void proc1();
SC_CTOR( my_module ) {
SC_METHOD( proc1 );
sensitive expression evaluates tosig2 = in1+sig1+6
each time the process is executed.
Processes
SC_METHODSC_THREADSC_CTHREAD
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Asynchronous Thread Process SC_THREAD: Is sensitive to a set of signals
This set is called sensitivity list
May be sensitive to any change on a signal May be sensitive to the positive or negative edge of a boolean signal
Is reactivated whenever any of the inputs it is sensitive to changes. Once an asynchronous thread processis reactivated:
Instructions are executed infinitely fast (in terms of internal simulationtime) until the next occurrence of a wait()statement.
Instructions are executed in order. The next time the process is reactivated execution will continue after thewait()statement.
Processes
SC_METHODSC_THREADSC_CTHREAD
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Implement synchronization and writing of signals in processes. wait() suspends execution of the process until the process is
invoked again.
If notiming control statement used: Process executes in zero time. Outputs are never visible.
To write to an output signal, a process needs to invoke a timing
control statement.
Multiple interacting synchronous processes must have at leastone timing control statement in every path.
Processes
SC_METHODSC_THREADSC_CTHREAD
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wait()may be used in both SC_THREADand SC_CTHREADprocessesbut NOT in an SC_METHODprocess (block).
wait()suspends execution of the process until the process isinvoked again.
wait()may be used to wait for a certain number ofcycles (SC_CTHREADonly).
In Synchronous process (SC_CTHREAD)
Statements before the wait()are executed in one cycle. Statements after the wait()are executed the next cycle.
In Asynchronous process (SC_THREAD)
Statements before the wait()are executed in last event. Statements after the wait()are executed the next event.
Examples:wait() ; // waits 1 cycle in synchronous process
wait(4); // waits 4 cycles in synchronous process
wait(4) ; //ERROR!! in Asynchronous process
Examples:wait() ; // waits 1 cycle in synchronous process
wait(4); // waits 4 cycles in synchronous process
wait(4) ; //ERROR!!in Asynchronous process
Processes
SC_METHODSC_THREADSC_CTHREAD
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SC_MODULE( my_module ) { sc_in_clk clk;
sc_in reset_n;
sc_in in1;
sc_in in2;
sc_out out1;
sc_out out2;
sc_signal sig1;
sc_signal sig2;
int _internal;
void proc2();
SC_CTOR( my_module ) {
SC_THREAD( proc2 );
sensitive the value of incis incremented by one
each time the process is reactivated.
Processes
SC_METHODSC_THREADSC_CTHREAD
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Synchronous process SC_CTHREAD: Sensitive only to one edge of one and only one clock
Called the active edge
Special case of a SC_THREAD process Cannot use multiple clocks with a synchronous process
Triggered only at active edge of its clock Therefore inputs are sampled only at the active edge.
It is not triggered if inputs other than the clock change.
Models the behavior of unregistered inputs and registered outputs
Processes
SC_METHODSC_THREADSC_CTHREAD
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Synchronous process SC_CTHREAD: Once invoked the statements execute until a wait()
statement is encountered. At the wait()statement, the process execution is suspended
At the next execution, process execution starts from thestatement after the wait()statement
Local variables defined in the process function are savedeach time the process is suspended.
Tip: Use wait();to wait for multiple clock cycles.
Processes
SC_METHODSC_THREADSC_CTHREAD
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1 35
13 18
14
in1
in2
out
clock
in2
in1
out
while (true) { out = in1 + in2; wait( );}
in1
in2
out
Processes
SC_METHODSC_THREADSC_CTHREAD
1 35
13 18
in1
in2
out
clock
14 53
SystemC 1.0.x SystemC 2.0
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Synchronous Thread Process SC_CTHREAD: Useful for high level synthesis.
Modeling of synchronous systems.
Modeling of sequential logic.
Models the behavior of a block with unregistered inputs and
registered outputs.
Useful for modeling drivers in test benches.
Processes
SC_METHODSC_THREADSC_CTHREAD
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SC_MODULE( my_module ) {
sc_in_clk clk;
sc_in reset_n;
sc_in in1;
sc_in in2;
sc_out out1;
sc_out out2;
sc_signal sig1;
sc_signal sig2;
int _internal;
void proc3();
SC_CTOR( my_module ) {
SC_CTHREAD( proc3, clk.pos() ); }
};
void my_module::proc3()
{
// start-up functionality goes here
int inc = 1;
while(1) {
out2.write(inc);
sig2 = sig2 + inc;
++inc;
wait();
}
}
State of internal variables is preserved =>the value of inc is incremented by at each
positive clock edge.
State of internal variables is preserved =>the value of inc is incremented by at each
positive clock edge.
Processes
SC_METHODSC_THREADSC_CTHREAD
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TopicUnit
Language Elements of SystemC2
Data Types2.1
Processes2.2
Hierarchy2.3
Modules, Ports and Signals2.1
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Systems are modeled hierarchically SystemC has to provide a mechanism for hierarchy
Solution
Modules may contain instances of other modules
in sub_a
top
sub_b
top
sub_a
sub_b
SC_MODULE
{Ports
SignalsVariables Constructor Processes
Modules
};
a_in a_out outb_in b_out
sig
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SC_MODULE
{Ports
SignalsVariables Constructor Processes
Modules
};
SC_MODULE(top)
{ sc_in in;
sc_out out;
sc_signal sig;
sub_a* inst1; sub_b* inst2;
....
};
SC_MODULE(top)
{ sc_in in;
sc_out out;
sc_signal sig;
sub_a* inst1; sub_b* inst2;
....
};
Define member variablesfor all the internal signalsthat are needed to connectthe child modules ports toeach other.
Note: a port of the parent
module is directly bound toa port of the child module(no signal needed).
Define member variablesfor all the internal signalsthat are needed to connectthe child modules ports toeach other.
Note: a port of the parent
module is directly bound toa port of the child module(no signal needed).
in sub_a
top
sub_ba_in a_out outb_in b_outsig
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SC_MODULE
{Ports
SignalsVariables Constructor Processes
Modules
};
SC_MODULE(top)
{ sc_in in;
sc_out out;
sc_signal sig;
sub_a* inst1; sub_b* inst2;
....
};
SC_MODULE(top)
{ sc_in in;
sc_out out;
sc_signal sig;
sub_a* inst1; sub_b* inst2;
....
};
Define member variablesthat are pointers to thechild modules class for allinstances
Define member variablesthat are pointers to thechild modules class for allinstances
in sub_a
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sub_ba_in a_out outb_in b_outsig
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SC_MODULE
{Ports
SignalsVariables Constructor Processes
Modules
};
SC_CTOR {
inst1 = new sub_a("inst_1");
inst2 = new sub_b("inst_2");
(*inst1).a_out(sig);
(*inst1).a_in(in);
(*inst2)(sig, b_out);
}
SC_CTOR {
inst1 = new sub_a("inst_1");
inst2 = new sub_b("inst_2");
(*inst1).a_out(sig);
(*inst1).a_in(in);
(*inst2)(sig, b_out);
}
Create the child moduleinstances within the parentmodules constructor usingthe C++ keyword new.
An arbitrary name is givento the module instances. It
is good practice to use thename of the instancevariable.
Create the child moduleinstances within the parentmodules constructor usingthe C++ keyword new.
An arbitrary name is givento the module instances. It
is good practice to use thename of the instancevariable.
in sub_a
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sub_ba_in a_out outb_in b_outsig
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SC_MODULE
{Ports
SignalsVariables Constructor Processes
Modules
};
SC_CTOR {
inst1 = new sub_a("inst_1");
inst2 = new sub_b("inst_2");
(*inst1).a_out(sig);
(*inst1).a_in(in);
(*inst2)(sig, b_out);
}
SC_CTOR {
inst1 = new sub_a("inst_1");
inst2 = new sub_b("inst_2");
(*inst1).a_out(sig);
(*inst1).a_in(in);
(*inst2)(sig, b_out);
}
Connect ports of childmodules to one another withinternal signals.
Connect ports of the parentmodule to ports of the childmodule using direct port-to-
port connection. A signalMUST NOT be used.
Connect ports of childmodules to one another withinternal signals.
Connect ports of the parentmodule to ports of the childmodule using direct port-to-
port connection. A signalMUST NOT be used.
in sub_a
top
sub_ba_in a_out outb_in b_outsig
Mapping by name isrecommended.
Mapping by position may alsobe used.
Mapping by name isrecommended.
Mapping by position may alsobe used.
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Why C-based Design Flow1
TopicUnit
Language Elements of SystemC2
SystemC and Synthesis3
Simple Example4
Resources5
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UTFUTF
TFTF
Partition
BehavioralBehavioral
RTLRTLabstract
RTOS
abstractRTOS
target
code
target
code NetlistNetlist
Refine
Refine
Refine
Refine
System/ Architectural Levelnot synthesizableevent drivenabstract communicationabstract data types
Behavioral Levelsynthesizable
clockedI/O cycle accuratealgorithmic description
RT Level
synthesizableclocked
FSMdata path
SoftwareHardware
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System/Architectural Level
channels, interfaces, events, master-slave comm. library (all beta)
Behavioral synthesis to netlist
RTL
synthesis to netlist
Software
abstract RTOS (not yet available)
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Refine Structure
use signals for I/F
partition into synthesizable blocks
restrict to synthesizable language subset
Refine Control
specify throughput/latency
specify I/O protocolRefine Data
restrict to physically meaningful datatypes (no abstract data)
specify bit width
Functional Description
Implementable Description
Structure Control Data
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CPU
Memory
I/O Board Disk
BusArbiter
algorithmic ClkdrivenBus IF
algorithmicClk
drivenBus IF
ClkdrivenBus IF
ClkdrivenBus IF
algorithmicClk
drivenBus IF
algorithmic
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CPU
Memory
I/O Board Disk
BusArbiter
CLKdriven
CLKdriven
CLK
driven
Interface cycle accurate
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SC_MODULE(fir) {sc_in_clk clk;
sc_in reset;
sc_in in;
sc_in in_data_valid;
sc_out out;
sc_out out_data_valid;...
sc_signal state_curr, state_nxt;
...
SC_CTOR(fir) {
SC_METHOD(fir);
sensitive
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Why C-based Design Flow1
TopicUnit
Language Elements of SystemC2
SystemC and Synthesis3
Simple Example4
Resources5
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main.cppmain.cpp
stimgen.cppstimgen.cpp
stimgen.hstimgen.h
adder.cppadder.cpp
adder.hadder.h
monitor.cppmonitor.cpp
monitor.hmonitor.h
Adderin1
in2
outResponseMonitor
reStimulusGenerator
a1
a2
main.cpp
clk
+
in1 in2
out
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// header file adder.htypedef int T_ADD;
SC_MODULE(adder) {// Input ports
sc_port in1;sc_port in2;
// Output portssc_port in2;
// ConstructorSC_CTOR(adder){
SC_THREAD(main);}
// Functionality of the processvoid main();
};
// header file adder.htypedef int T_ADD;
SC_MODULE(adder) {// Input ports
sc_port in1;sc_port in2;
// Output portssc_port in2;
// ConstructorSC_CTOR(adder){
SC_THREAD(main);}
// Functionality of the processvoid main();
};
main.cppmain.cpp
stimgen.cppstimgen.cpp adder.cppadder.cpp
adder.hadder.h
monitor.cppmonitor.cpp
monitor.hmonitor.hstimgen.hstimgen.h
Adder
in1
in2
outResponseMonitorre
StimulusGenerator
a1
a2
main.cpp
clk
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// Implementation file adder.cpp
#include systemc.h#include adder.h
void adder::main(){
while (true) {out->write(in1->read() + in2->read());// assign a run-time to process
wait(10, SC_NS);}
}
// Implementation file adder.cpp
#include systemc.h#include adder.h
void adder::main(){
while (true) {out->write(in1->read() + in2->read());// assign a run-time to process
wait(10, SC_NS);}}
main.cppmain.cpp
stimgen.cppstimgen.cpp adder.cppadder.cpp
adder.hadder.h
monitor.cppmonitor.cpp
monitor.hmonitor.hstimgen.hstimgen.h
Adder
in1
in2
outResponseMonitor
reStimulusGenerator
a1
a2
main.cpp
clk
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// header file adder.h
typedef sc_int T_ADD;
SC_MODULE(adder) {
// Clock introducedsc_in_clk clk;// Input portssc_in in1;sc_in in2;// Output portsc_out out;
// ConstructorSC_CTOR(adder){SC_CTHREAD(main, clk.pos());
}
// Functionality of the processvoid main();
};
main.cppmain.cpp
stimgen.cppstimgen.cpp adder.cppadder.cpp
adder.hadder.h
monitor.cppmonitor.cpp
monitor.hmonitor.hstimgen.hstimgen.h
Adder
in1
in2
outResponseMonitor
reStimulusGenerator
a1
a2
main.cpp
clk
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// Implementation file adder.cc#include systemc.h#include adder.h
void adder::main(){
// initializationT_ADD __in1 = 0;T_ADD __in2 = 0;T_ADD __out = 0;
out.write(__out);wait();
// infinite loopwhile(1) {
__in1 = in1.read();__in2 = in2.read();__out = __in1 + __in2;out.write(__out);wait();
}}
main.cppmain.cpp
stimgen.cppstimgen.cpp adder.cppadder.cpp
adder.hadder.h
monitor.cppmonitor.cpp
monitor.hmonitor.hstimgen.hstimgen.h
Adder
in1
in2
outResponse
Monitorre
Stimulus
Generator
a1
a2
main.cpp
clk
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// header file adder.h
typedef sc_int T_ADD;
SC_MODULE(adder) {// Clock introducedsc_in_clk clk;
// Input portssc_in in1;sc_in in2;// Output portsc_out out;
// internal signalsc_signal sum;
// ConstructorSC_CTOR(adder){
SC_METHOD(add);sensitive
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// Implementation file adder.cc#include systemc.h#include adder.h
void adder::add(){
T_ADD __in1 = in1.read();T_ADD __in2 = in2.read();
sum.write( __in1 + __in2 );}
void adder::reg(){
out.write( sum );}
main.cppmain.cpp
stimgen.cppstimgen.cpp adder.cppadder.cpp
adder.hadder.h
monitor.cppmonitor.cpp
monitor.hmonitor.hstimgen.hstimgen.h
Adder
in1
in2
outResponse
Monitorre
Stimulus
Generator
a1
a2
main.cpp
clk
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Why C-based Design Flow1
TopicUnit
Language Elements of SystemC2
SystemC and Synthesis3
Simple Example4
Resources5
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www.systemc.orgdownloadnews
forum (mailing list)FAQs
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For SystemC training in Munich, Erlangen, or on-site
look at:
http://www.iis.fhg.de/kursbuch/kurse/systemc.html
Next scheduled training: Nov 21-23 in Munich,
Germany
Covers SystemC 2.0