Dominance Fault Collapsing of Dominance Fault Collapsing of Combinational CircuitsCombinational Circuits

By Kalpesh ShetyeBy Kalpesh Shetye&&

Kapil GoreKapil Gore

ELEC 7250, Spring 2004ELEC 7250, Spring 2004

IntroductionIntroduction

A program is written in MATLAB for dominance fault collapsing of A program is written in MATLAB for dominance fault collapsing of combinational circuits. The resulting collapsed fault set is compared combinational circuits. The resulting collapsed fault set is compared with the equivalence collapsed fault set obtained from HITEC ATPG with the equivalence collapsed fault set obtained from HITEC ATPG software.software.

Input Files Input Files .bench & .name .bench & .name

Output File Output File .eqf .eqf

The program also counts the number of collapsed faults and The program also counts the number of collapsed faults and displays the time taken for computation.displays the time taken for computation.

Program is compatible with XOR & XNOR gates.Program is compatible with XOR & XNOR gates.

.bench file.bench fileInput .bench file is modified to SPICE format Input .bench file is modified to SPICE format

INPUT 1INPUT 1INPUT 2INPUT 2INPUT 3INPUT 3INPUT 6INPUT 6INPUT 7INPUT 7OUTPUT 22OUTPUT 22OUTPUT 23OUTPUT 23NAND 1 3 10NAND 1 3 10NAND 3 6 11NAND 3 6 11NAND 2 11 16NAND 2 11 16NAND 11 7 19NAND 11 7 19NAND 10 16 22NAND 10 16 22NAND 16 19 23NAND 16 19 23

AnalysisAnalysis

The program uses structural dominance fault collapsing.The program uses structural dominance fault collapsing.

The rules used are as follows:The rules used are as follows:

1.1. To collapse faults of a gate, all faults from the output can To collapse faults of a gate, all faults from the output can be be eliminated retaining one type of fault on each input of the eliminated retaining one type of fault on each input of the gate gate and the other type on any one of the inputs.and the other type on any one of the inputs.

2.2. The output faults of the NOT gate, the non-inverting buffer The output faults of the NOT gate, the non-inverting buffer and and the wire can be removed as long as both faults on the input the wire can be removed as long as both faults on the input are are retained.retained.

3.3. No collapsing is possible for fan-outs.No collapsing is possible for fan-outs.

4.4. No collapsing is possible for XOR and XNOR gates.No collapsing is possible for XOR and XNOR gates.

AlgorithmAlgorithm

The algorithm used is as follows:The algorithm used is as follows:

1.1. Assign tokens to all gates.Assign tokens to all gates.

2.2. Construct input, output and gate array.Construct input, output and gate array.

3.3. Construct fanout array.Construct fanout array.

4.4. Identify input fanout nodes and assign s-a-0 and s-a-1 faults.Identify input fanout nodes and assign s-a-0 and s-a-1 faults.

5.5. Consider the first gate and check if any of its inputs is the Consider the first gate and check if any of its inputs is the output of another gate. If yes, then set flag bit. output of another gate. If yes, then set flag bit.

6.6. Check the inputs of the same gate with the fanout array and Check the inputs of the same gate with the fanout array and check its flag bit. If flag bit is set and a match is found, check its flag bit. If flag bit is set and a match is found,

assign assign one stuck-at fault at thatone stuck-at fault at that input. If flag bit is not set and a input. If flag bit is not set and a match match is found, then assign two stuck-at faults and set flag bit.is found, then assign two stuck-at faults and set flag bit.

7.7. Repeat the above step for comparison with the input array Repeat the above step for comparison with the input array instead of the fanout array.instead of the fanout array.

8.8. Repeat steps 5 to 7 for all the remaining gates.Repeat steps 5 to 7 for all the remaining gates.

ResultsResults

Circuit Under Circuit Under Test Test

MATLAB programMATLAB program HITEC HITEC

11 c17 bench file c17 bench file Collapsed faults = 16Collapsed faults = 16

Detected faults = 16Detected faults = 16

Redundant faults = 0Redundant faults = 0

Fault Coverage = 100% Fault Coverage = 100%

Collapsed faults = 22Collapsed faults = 22

Detected faults = 22Detected faults = 22

Redundant faults = 0Redundant faults = 0

Fault Coverage = 100%Fault Coverage = 100%

22 74181 bench file 74181 bench file (with XOR) (with XOR)

Collapsed faults = 192 Collapsed faults = 192 No provision for XOR and No provision for XOR and XNOR gates XNOR gates

33 74181 bench file 74181 bench file (with each XOR (with each XOR replaced by 4 replaced by 4 NAND gates) NAND gates)

Collapsed faults = 232Collapsed faults = 232

Detected faults = 224Detected faults = 224

Redundant faults = 8Redundant faults = 8

Fault Coverage = 96.55% Fault Coverage = 96.55%

Collapsed faults = 301Collapsed faults = 301

Detected faults = 293Detected faults = 293

Redundant faults = 8Redundant faults = 8

Fault Coverage = 97.34% Fault Coverage = 97.34%

ConclusionConclusion

On the basis of the results, we make the following conclusions:On the basis of the results, we make the following conclusions:

1.1. For small circuits, both dominance as well as equivalence For small circuits, both dominance as well as equivalence fault fault collapsing result in identical fault coverage.collapsing result in identical fault coverage.

2.2. For large circuits, equivalence fault collapsing results in For large circuits, equivalence fault collapsing results in larger larger fault coverage than dominance fault collapsing.fault coverage than dominance fault collapsing.

3.3. Size of collapsed fault set obtained by dominance is smaller Size of collapsed fault set obtained by dominance is smaller than that obtained by equivalence.than that obtained by equivalence.

4.4. For large circuits, selection of either technique for fault For large circuits, selection of either technique for fault collapsing is essentially a trade-off between time taken for collapsing is essentially a trade-off between time taken for testing and fault coverage.testing and fault coverage.

Suggested Improvements Suggested Improvements Incorporate test vector generation routine and fault simulation Incorporate test vector generation routine and fault simulation routine.routine.

References References [1][1] HITEC/PROOFS User’s manual.HITEC/PROOFS User’s manual.

[2][2] Essentials of Electronic Testing for Digital Memory and Essentials of Electronic Testing for Digital Memory and Mixed-Mixed- Signal VLSI Circuits, Michael Bushnell and Vishwani Signal VLSI Circuits, Michael Bushnell and Vishwani Agrawal.Agrawal.

Questions?Questions?