documentation of timing tests for mountain storm instruments llc · 2018. 4. 17. · s2kb0001...

Documentation of Timing Tests ForMountain Storm Instruments LLC

Peter Parker and Tim HamlinLos Alamos National Laboratory

Prepared for John Battles

December 17, 2015

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1 Introduction

This report is to document the timing tests performed at Los Alamos Na-tional Laboratory (LANL) on behalf of Mountain Storm Instruments (MSI).These tests were completed between 1 November and 15 December 2015.The purpose of these tests was to characterize the error in the time tagsgenerated by two different receiver designs based on two different GPS chips.This testing was completed in two stages. In the first stage, MSI provideda module that would output a 1 pulse-per-second (PPS) from the on-boardGPS chip. This PPS signal was compared with the clock of a high-qualityGPS time reference owned by LANL. In the second stage of testing, MSIprovided a full data receiver that would provide a trigger time based on theincoming signal. A PPS signal from the LANL reference timing system wasinput into the MSI data receiver and time tags were recorded and comparedwith the time at which the reference pulse was sent. The remainder of thisdocument details these two tests including any calibrations used to accomo-date for cable delays, provides a description of data collected, and providesa cursory analysis of the data. The raw (uncalibrated) timing data are alsoprovided as a companion to this report. A summary of these files are inTable 1

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Table 1: Table of all data files, date each file was started, which test the fileis associated with, and any relevant notes about the file.

File name Start date Test Notes

M200 3Nov.txt 3 Nov. Test 1 Initial test

M200 4Nov.txt 4 Nov. Test 1 Power cycle


M300 17Nov.txt 17 Nov. Test 1 Initial test


ttlog s1kc0001 20151130 0delay.txt 30 Nov. Test 2 0 ms delay

ttlog s1kc0001 20151202 0delay.txt 2 Dec. Test 2 0 ms delay; power cycle

ttlog s1kc0001 20151202 0delay 2.t 2 Dec. Test 2 0 ms delay; power cycle

ttlog s1kc0001 20151203 250delay.t 3 Dec. Test 2 250 ms delay



ttlog s1kc0001 20151207 750delay.t 7 Dec. Test 2 750 ms delay; power cycle



ttlog s1kc0002 20151130 0delay.txt 30 Nov. Test 2 0 ms delay

ttlog s1kc0002 20151202 0delay.txt 2 Dec. Test 2 0 ms delay; power cycle

ttlog s1kc0002 20151202 0delay 2.t 2 Dec. Test 2 0 ms delay; power cycle







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Table 1 (cont.): Table of all data files, date each file was started, which testthe file is associated with, and any relevant notes about the file.

File name Start date Test Notes

ttlog s2kb0001 20151130 0delay.txt 30 Nov. Test 2 0 ms delay

ttlog s2kb0001 20151202 0delay.txt 2 Dec. Test 2 0 ms delay; power cycle

ttlog s2kb0001 20151202 0delay 2.t 2 Dec. Test 2 0 ms delay; power cycle

ttlog s2kb0001 20151203 250delay.t 3 Dec. Test 2 250 ms delay



ttlog s2kb0001 20151207 750delay.t 7 Dec. Test 2 750 ms delay; power cycle



ttlog s2kb0002 20151130 0delay.txt 30 Nov. Test 2 0 ms delay

ttlog s2kb0002 20151202 0delay.txt 2 Dec. Test 2 0 ms delay; power cycle

ttlog s2kb0002 20151202 0delay 2.t 2 Dec. Test 2 0 ms delay; power cycle







ttlog s2kb0001 20151214 0delay.txt 14 Dec. DMA 0 ms delay






S2KB0001 20151214.log 14 Dec. DMA Pressure/Temp/Humidity

S2KB0001 20151215.log 15 Dec. DMA Pressure/Temp/Humidity

ATS Test 8Dec.txt 8 Dec. CAL LANL clock calibration data

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2 Test 1

The purpose of the first test was to check the timing accuracy of the PPSsignal coming off of the GPS daughter card. In total, four different cardswith two different types of GPS chips were tested: two M200 GPS modules(denoted as M200#1 and M200#2), and two M300 GPS modules (denotedas M300#1 and M300#2).

The LANL owned GPS timing reference is a Symmetricom ATS-6501 T-Flex GPS time and frequency standard. This time reference also has a builtin Time Interval Counter (TIC) that was used to compare incoming pulses tothe internally generated PPS signal. This time reference was checked againstanother LANL time reference that was compared with a NIST time standard(see Fig. 1). This shows that the time reference used in all comparisons

Figure 1: Plot of LANL reference clock (ATS-6501) against Symmetricom#1. Symmetricom #1 clock was taken to NIST and compared well with theirclocks.

with MSI equipment is very stable, has low variance, and a negligible biascompared with the NIST compared clock.

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2.1 Test setup

The test setup used for Test 1 is shows in Fig. 2. This figure documentsall of the cable delays between the various systems and lists the expectedoffset between the reference PPS and the PPS of the devices under test.Fig. 3 shows the placement of the three antennas for Test 1. The distancebetween the ATS-6501 antenna and the MSI antennas was about 1 meter.Two configurations were used for this test. First, the two M200 GPS chipswere tested simultaneously, and then the two M300 GPS. Note that in eachtest, the data may have been collected while the GPS unit was still lockinginto a steady state position. Typically this took about 5 minutes. Thistransient is included in the recorded data.

Figure 2: Test 1 setup showing all relevant cable delays to calculate anexpected offset between devices.

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Figure 3: Photo of antenna placement for all tests. The distance betweenthe ATS-6501 and MSI antennas is about 1 meter.

2.2 Data

The ATS-6501 TIC counter outputs a line of data for each new input pulse.Below is an example of the data output by the ATS-6501 TIC:

Ch0 - Ch21 (1 event average): 8.971 ns 1446739037 S 234371 uS; sd: 0.000000 ns

The three pieces of relevant information are the second CHXY column, the ns

column, and the S column all denoted in red. The CHXY denotes which TICchannel the data are coming from. The X value denotes which slot the TICcard is in (always 2 for all of the tests) and the Y value denotes which TICchannel the data is reporting. Device 1 is always on channel 1 and device 2is always on channel 2. The ns column denotes the number of nanosecondsafter the internal PPS the input pulse was detected. The S column denotesthe number of seconds since 1 Jan 1970 of the reference PPS.

In the first configuration, with M200#1 and M200#2 under test, threedata files were recorded starting on 3, 4, and 5 November 2015. In-betweeneach file, the hardware was power cycled. The three files are: M200 3Nov.txt,

M200 4Nov.txt, M200 5Nov.txt. Figure 4 shows the time series of the tim-ing offset over each of these days as well as a histogram for each device andeach day. Note that the standard deviation of timing errors are about thesame for each device and each day. However, there is a different bias valueeach time the device is powered on.

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(a) Timing offset vs time of M200 devices

(b) Timing offset histogram of M200 devices

Figure 4: Time series and histogram of timing offset of M200 devices.

In the second configuration, with M300#1 and M300#2 under test, twodata files were recorded starting on 17 and 18 November 2015. In-betweeneach file, the hardware was power cycled. The two files are: M300 17Nov.txt,

M300 18Nov.txt. Figure 5 shows the time series of the timing offset over eachof these days as well as a histogram for each device and each day. For thesedevices, the timing offset bias is about the same after a power cycle. However,looking at the histogram (and closer inspection of the time series data) thereare a decent percentage of points for device two where the timing jumps byabout 40–50 ns.

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(a) Timing offset vs time of M300 devices

(b) Timing offset histogram of M300 devices

Figure 5: Time series and histogram of timing offset of M300 devices.

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Table 2 summarizes all of the data collected for Test 1 including a list ofmean and standard deviation of each file.

Table 2: Test 1 summary data.

Device Start date Mean (ns) Std. (ns)

M200#1 3 Nov. 30 14

M200#1 4 Nov. 56 14

M200#1 5 Nov. 42 10

M200#2 3 Nov. 30 18

M200#2 4 Nov. -18 15

M200#2 5 Nov. 38 18

M300#1 17 Nov. 12 13

M300#1 18 Nov. 10 13

M300#2 17 Nov. 25 18

M300#2 18 Nov. 17 23

3 Test 2

The purpose of the second test was to check the time stamp accuracy of theGPS disciplined radio receiver. Four receivers were tested. Two containingM200 GPS chips (chips #3 and #4 denoted as s1kc01 and s1kc02) and twocontaining M300 GPS chips (chips #1 and #2 denoted as s2kc01 and s2kc02).Two portions of this test were completed; one without DMA recorders, andone with DMA recorders operating and temperature, pressure, and humiditysensors recording values.

3.1 Test setup (no DMA)

The test setup used for the first part of Test 2 (without DMA) is shown inFig. 6. This figure documents all of the cable delays between the varioussystems and lists the expected offset between the reference PPS and thePPS of the devices under test. In addition to the equipment used in test 1,a 10 MHz referenced DG64 is used to provide a variable delay between theATS-6501 PPS and the radio receivers. Fig. 7 shows the physical placement

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Figure 6: Test 2 setup showing all relevant cable delays to calculate anexpected offset between devices.

of all test 2 equipment insid of the lap. This test consisted of a series ofcollections while changing the delay in the DG645. The delays used were:

• 100092ns

• 250100092ns

• 500100092ns

• 750100092ns.

After the delay test, each receiver was power cycled several times to test thetime offset stability from a clean startup.

3.2 Data (no DMA)

There are nine different data files for each device tested (36 total files). Thenaming convention for these files isttlog [device name] [YYYYMMDD] [coarse delay]delay.txt,where

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Figure 7: Photo of equipment used in test 2.

• [device name] is s1kc0001, s1kc0002, s2kb0001, or s2kb0002

– GPS chips are M200#3, M200#4, M300#3, and M300#4 respec-tively

• [YYYYMMDD] is the year, month, and day when the file started

• [coarse delay] is the rough time delay in milliseconds added by theDG645.

Also, an optional 2 at the end if two files with the same device and delaywere started on the same day.

There are thee power cycles of the devices at 0 ms delay, a single test at250 ms delay, a single test at 500 ms delay, and four tests (with power cyclesin-between) at 750 ms delay. For the last 0 ms data file through the first750 ms data file, the devices were left on and powered up. Occasionally, thedata collection GUI would need to be restarted (most often on s1kc02, butonce on s2kb02).

The mean and standard deviation of the calibrated timing offsets in eachdata file are summarized in Tables 3 and 4.

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Table 3: Test 2 summary data for s1kc devices.

Device Start date Delay (ms) Mean (ns) Std. (ns)

s1kc01 30 Nov. 0 -81 22

s1kc01 2 Dec. 0 -104 22

s1kc01 2 Dec. 0 -98 28

s1kc01 3 Dec. 250 -115 18

s1kc01 3 Dec. 500 -104 23

s1kc01 4 Dec. 750 -108 28

s1kc01 7 Dec. 750 -64 28

s1kc01 8 Dec. 750 -79 20

s1kc01 9 Dec. 750 -67 40

s1kc02 30 Nov. 0 -40 22

s1kc02 2 Dec. 0 -69 23

s1kc02 2 Dec. 0 -111 36

s1kc02 3 Dec. 250 -73 16

s1kc02 3 Dec. 500 -81 14

s1kc02 4 Dec. 750 -75 20

s1kc02 7 Dec. 750 -89 58

s1kc02 8 Dec. 750 -101 56

s1kc02 9 Dec. 750 -111 68

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Table 4: Test 2 summary data for s2kb devices.

Device Start date Delay (ms) Mean (ns) Std. (ns)

s2kb01 30 Nov. 0 -119 13

s2kb01 2 Dec. 0 -71 20

s2kb01 2 Dec. 0 -128 15

s2kb01 3 Dec. 250 -79 19

s2kb01 3 Dec. 500 -130 23

s2kb01 4 Dec. 750 -103 30

s2kb01 7 Dec. 750 -115 30

s2kb01 8 Dec. 750 -94 30

s2kb01 9 Dec. 750 -110 30

s2kb02 30 Nov. 0 -66 23

s2kb02 2 Dec. 0 -52 11

s2kb02 2 Dec. 0 -24 14

s2kb02 3 Dec. 250 -36 12

s2kb02 3 Dec. 500 -30 19

s2kb02 4 Dec. 750 -50 36

s2kb02 7 Dec. 750 -48 39

s2kb02 8 Dec. 750 -50 36

s2kb02 9 Dec. 750 -57 38

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A histogram of all timing errors (all power cycles and all time delays) foreach device tested is shown in Figure 8. The mean and standard deviationof calibrated errors for each device are:

• s1kc01: −81 ns mean and 22 ns standard deviation

• s1kc02: −40 ns mean and 22 ns standard deviation

• s2kb01: −119 ns mean and 13 ns standard deviation


This represents a worst case histogram for the tests completed by LANL.

Figure 8: Histogram of all calibrated timing error data for each device testedfor Test 2 (no DMA).

3.3 Test setup (with DMA) and Data

There were only two devices that had the software update to enable DMArecording. These were s2kb01 and s2kb02. For the first of these devices, the

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temperature, pressure, and humidity were recorded. Three separate record-ings were made (no power cycles through the recordings) at the followingdelays in the DG645

• 100092ns

• 500000092ns

• 750000092ns

Note the change in the 500ms and 750ms delays as they do not have an extramicrosecond delay.

There is no noticeable jump in timing error when comparing the differentDG645 errors. As each of these individual tests were completed in less thana single day, some diurnal variation due to the GPS constellation motion isimprinted on the individual data files. A histogram of timing errors for eachDMA enabled device tested is shown in Figure 9. The mean and standarddeviation of calibrated errors for each device are:



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Figure 9: Histogram of calibrated timing error data for each device testedfor Test 2 with DMA.

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