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DLD UNIT-6 Ramaiah Thalluri PACE Institute of Technology & Sciences, Ongole Andhra Pradesh, INDIA

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This PPT is prepared for JNTUK - II CSE students purpose only.Download this PPT from my blog manadld.blogspot.in

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Page 1: DLD UNIT-6

DLD UNIT-6

-Ramaiah Thalluri-PACE Institute of Technology & Sciences, Ongole

-Andhra Pradesh, INDIA

Page 2: DLD UNIT-6

PLD’s (Programmable Logic Devices)

An IC that contains large numbers of gates, flip-flops, etc. that can be configured by the user to perform different functions is called a Programmable Logic Device (PLD).

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PLD’S ...

PLDs are typically built with an array of AND gates (AND-array) and an array of OR gates (OR-array).

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PLD – General Structure :

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Types of standard PLDs:

PROMPALPLA

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IC’s (Integrated Circuits) A large number of components

fabricated on a single chip is called an IC.

Types of IC’s SSI - Small Scale Integration MSI – Medium Scale Integration LSI - Large Scale Integration VLSI – Very Large Scale Integration ULSI – Ultra Large Scale Integration

Page 7: DLD UNIT-6

ROM (Read Only Memory) ROM is a memory device in which

permanent binary information is stored.

Types of ROM’s MROM – Mask Programmable ROM PROM – Programmable ROM EPROM – Erasable PROM EEPROM – Electrically Erasable PROM

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Conventional & Array logic symbol

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Buffer/Inverter

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Programming by blowing fuses.

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OR - PLD Notation

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AND - PLD Notation

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Three Fundamental Types of PLDs:

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The ROM (Read Only Memory) or PROM (Programmable Read Only Memory):

The input lines to the AND array are hard-wired and the output lines to the OR array are programmable.

Each AND gate generates one of the possible AND products (i.e., minterms).

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ROM block diagram:

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PLA... The AND and OR gates inside the

PLA are initially fabricated with the links (fuses) among them.

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Block diagram of the PLA

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Block diagram of the PLA ... The product terms constitute a group

of k AND gates each of 2n inputs. Links are inserted between all n

inputs and their complement values to each of the AND gates.

Links are also provided between the outputs of the AND gates and the inputs of the OR gates.

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Another type-Block diagram of the PLA

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PLA . . .

In every PLA, we have to design the Personality matrix or Programming table of given example.

Example is shown below.

Consider an example & the outputs are shown below.

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PLA - Before Programming

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PLA - After Programming

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PLA - Alternate representation

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PLA as ROM :

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Programmable Logic Gate Arrays