DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

SHANMUGANATHAN ENGINEERING COLLEGEARASAMPATTI – 622 507

INTERNAL ASSESSMENT - IBranch : EEE Sub Code : EE6301 Year/Sem : II/III Sub Title : DIGITAL LOGIC CIRCUITSDate : 04/08/15 Q.P. Setter : A.RAMANATHAN AP/EEEDuration : 9.15a.m – 10.55a.m Max. Marks : 50

PART – A (5 x 2 = 10)

1. Give the classifications of binary codes.2. Convert the (153.513)10 to octal.3. What is the purpose of Hamming code?4. Define fan-in and fan-out.5. Give the classifications of digital logic families.

PART – B (40 Marks)

6. a (i) Covert the following numbers with the indicated base to decimala).(735)8 b).(16.5)16 c).(1010.1010)2 d). (525)6 (8)

(ii) Obtain the 1’s and 2’s compliment of the following numbers:a)10000000 b)11111111 c) 11011010 d)01110110 (8)

ORb (i) Perform each of the following decimal additions in BCD

a) 24 + 18 b) 48+58 (8)

(ii) a) Convert (10111011)2 into its equivalent gray code.b) Convert gray code 101011 into its binary equivalent

(4)(4)

7. a (i) Explain the operation of 2 input RTL NOR gate. (8)

(ii) Draw and explain the operation of 2 input DTL NAND gate. (8)OR

b (i) Draw and explain the operation of 2 input TTL totem pole NAND gate. (8)

(ii) Draw the circuit diagram of a CMOS two input NAND gate and explain its operation. (8)

8. a Compare the various digital logic families. (8)OR

b Perform (42)10-(68)10 using 2’s complement binary arithmetic. (8)

Staff in charge HOD/EEE