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TRANSCRIPT
DJ-190Service Manual
CONTENTS +SPECIFICATIONS 2
+CIRCUIT DESCRIPTION 3
+SEMICONDUCTOR DATA 9
+EXPLODED VIEW 15
+PARTS LIST 18
+ADJUSTMENT 21
+PCBOARD VIEW 26
+CIRCUIT DIAGRAM 36
+BLOCK DIAGRAM 43
ALINCO INCORPORATEDTWIN 21 M.I.D. TOWER BUILDING 23F, 1-61, 2-CHOME,SHIROMI CHUO-KU , OSAKA, 540-8580 JAPAN
Tel (81)6-6946-8150 fax (81)6-6946-8175e-mail: [email protected]
SPECIFICATIONSFrequency Coverage TX RX DJ-190T (u.s. Amateur version) 144.000 ~ 147.995MHz 135.000 ~ 173.995MHz DJ-190E (European Amateur version) 144.000 ~ 145.995MHz 144.000 ~ 145.995MHz DJ-190TA1 (commercial version VHFL) 135.000 ~ 155.000MHz 135.000 ~ 173.995MHz DJ-190TA2 (commercial version VHFH) 150.000 ~ 173.995MHz 135.000 ~ 173.995MHzChannel Step: 5, 10, 12.5, 15, 20, 25, 30kHzstepsMemory Channels: 40 ChannelsAntenna Impedance: 50ohm unbalancedFrequency Stability: +/-5 ppmMicrophone Input Impedance: 2kohm nominal.Signal Type: F3E (FM)Offset Range: 0 ~ 99.995MHzDeviation: 15kHz max.TX Output (supply voltage): 1.5W (4.8V) / 3.5W (7.2V) / 5W (9.6 ~ 13.8V)RX Sensitivity: 12dB SINAD better than - 16dBuRX Selectivity: -6dB/ +/- 12kHzI.F.: (1st) 21.25MHz / (2nd) 450kHzPower Supply Requirements: 4.8 ~ 13.8V DC (4.8V DC standard)Current Consumption Transmitting: Approx. 1.2 Amp. in High Power at 13.8V DC: Setting
Receiving: Squelched Approx. 24mA (BS on)Operating Temperature: -10 ~ +60*C, 14 ~ 140*FDimensions: 57(W) x 151(H) x 27(D) mm(with EBP-37N without projections) 2 1/4(W) x 6(H) x 1 1/16(D) inchesWeight: Approx. 300gSubaudible Tones (CTCSS) : Encoder installed (50 tones)
Page-2
CIRCUIT DESCRIPTION
1) Receiver System The receiver system is a double superheterodyne system with a 21.7 MHzfirst IF and a450 kHz second IF.
1. Front End The received signal at any frequency in the 130.00- to 173.995-MHz rangeis passed through the low-pass filter (L102, L103, L104, C113, C107, C116,and C114) and tuning circuit (L112 and D107), and amplified by the RFamplifier (Q107). The signal from Q107 is then passed through the tuningcircuit (L109, L110, L111, and varicapsi D104, D105 and D106) andconverted into 21.7 MHz by the mixer (Q106). The tuning circuit, whichconsists of L112, L109, varicaps D107 and D104, Ll110 L111, varicapsD105 and D106, is controlled by the tracking voltage from the CPU so thatit is optimized for the reception frequency. The local signal from the VCO ispassed through the buffer (Q108), and supplied to the source of the mixer(Q106). The radio uses the lower side of the superheterodyne system.
2. IF Circuit The mixer mixes the received signal with the local signal to obtain the sumof and difference between them. The crystal filter (XF101 , XF102) selects21.7 MHz frequency from the results and eliminates the signals of theunwanted frequencies. The first IF amplifier (Q105) then amplifies thesignal of the selected frequency.
3. Demodulator Circuit After the signal is amplified by the first IF amplifier (Q105), it is input to pin16 of the demodulator IC (IC104). The second local signal of 21.25 MHz(shared with PLL IC reference oscillation), which is oscillated by the internaloscillation circuit in IC102 and crystal (X101), is input through pin 1 ofIC104. Then, these two signals are mixed by the internal mixer in IC104and the result is converted into the second IF signal with a frequency of 450kHz. The second IF signal is output from pin 3 of IC104to the ceramic filter(FL101), where the unwanted frequency band of that signal is eliminated,and the resulting signal is sent back to the IC104 through pins 5 and 7.
The second IF signal input via pin 7 is demodulated by the internal limiteramplifier and quadrature detection circuit in IC104, and output as an audiosignal through pin 9.
4. Audio Circuit The audio signal from pin 9 of IC104 is compensated to the audiofrequency characteristics in the de-emphasis circuit (R162, R161, C172,C173) and amplified by the AF amplifier (Q109). The signal is then input topin 2 of the electronic volume (IC103) for volume adjustment, and outputfrom pin 1. The adjusted signal is sent to the audio power amplifier (1C105)through pin 2 to drive the speaker.
5. Squelch Circuit Part of the audio signal from pin 9 of IC104 is amplified by the noise filteramplifier consisting of R176, R186, R177, C179, C183, C191, and C194,and the internal noise amplifier in IC104. The desired noise of the signal isoutput through pin 11 of IC104, to be further amplified by the noise amplifier(Q115). The amplified noise signal is rectified by voltage doublers D109 andinput to pin 4 of CPU (IC5). Page-3
2) Transmitter System The audio signal is converted to an electric signal in either the internal or 1. Modulator Circuit external microphone, and input to the microphone amplifier (IC6). IC6
consists of two operational amplifiers; one amplifier (pins 1, 2, and 3) iscomposed of pre-emphasis and IDC circuits and the other (pins 5, 6, and 7)is composed of a splatter filter. The maximum frequency deviation isdetermined to its optimal value by switch circuits consisting of Q9 and Q10and input to the cathode of the varicap of the VCO, to change the electriccapacity in the oscillation circuit. This produces the frequency modulation.
2. Power Amplifier The transmitted signal is oscillated by the VCO, amplified by the pre-drive Circuit amplifier (Q102) and drive amplifier (Q101), and input to the power module
(IC101). The signal is then amplified by the power module (IC101) and ledto the antenna switch (D101) and low-pass filter (L102, L103, L104, C113,C107, C116, and C114), where unwanted high harmonic waves arereduced as needed, and the resulting signal is supplied to the antenna.
3. APC Circuit Part of the transmission power from the low-pass filter is detected by D103,converted to DC, and then amplified by a differential amplifier. The outputvoltage controls the bias voltage from pin 2 of the power module (IC101) tomaintain the transmission power constant.
3) PLL Synthesizer Circuit The dividing ratio is obtained by sending data from the CPU (IC5) to pin 21.PLL and sending clock pulses to pin 3 of the PLL IC (IC102). The oscillated
signal from the VCO is amplified by the buffer (Q117) and input to pin 6 ofIC102. Each programmable divider in IC102 divides the frequency of theinput signal by N according to the frequency data, to generate acomparison frequency of 5 or 6.25 kHz.
2. Reference Frequency The reference frequency appropriate for the channel steps is obtained by Circuit dividing the 21.25 MHz reference oscillation (X101) by 4250 or 3400,
according to the data from the CPU (IC5). When the resulting frequency is5 kHz, channel stepsof5, 10, 15, 20, 25 and 30 kHz are used. When it is6.25 kHz, the 12.5 kHz channel step is used.
3. Phase Comparator The PLL (IC102) uses the reference frequency, 5 or 6.25 kHz. The phase Circuit comparator in the IC102 compares the phase of the frequency from the
VCO with that of the comparison frequency, 5 or 6.25 kHz, which isobtained by the internal divider in IC102
4. PLL Loop Fitter Circuit If a phase difference is found in the phase comparison between thereference frequency and VCO output frequency, the charge pump output(pin 8) of IC102 generates a pulse signal, which is converted to DC voltageby the PLL loop filter and input to the varicap of the VCO unit for oscillationfrequency control.
Page-4
5. VCO Circuit A Colpitts oscillation circuit driven by Q301 directly oscillates the desiredfrequency. The frequency control voltage determined in the CPU (IC5) andPLL circuit is input to the varicaps (D301 and D304). This changes theoscillation frequency, which is amplified by the VCO buffer (Q302) andoutput from the VCO unit.
NoteThe oscillation frequency is determined by turning Q301 0N and OFF.
Displayed frequencies Q301TX: 130.00 - 139.995 MHz
OFFRX: 130.00 - 161.695 MHzTX: 140.00 - 173.995 MHz
ONRX: 161.70 - 173.995 MHz
4) CPU and Peripheral CircuitsThe CPU turns ON the LCD via segment and common terminals with 1/31. LCD Display Circuit the duty and 1/3 the bias, at the frame frequency is 85Hz.
2. Display Lamp Circuit When the LAMP key is pressed, "H" is output from pin 45 of CPU (IC5) tothe bases of Q1 then turn ON and the LEDs (D1, D3) Bight.
3. Reset and Backup When the power from the DC jack or external battery increases from 0 V to Circuits 2.5 or more, "H" level reset signal is output from the reset IC (IC2) to pin 35
of the CPU (IC5), causing the CPU to reset. The reset signal. however,waits at C6 and R98, and does not enter the CPU until the CPU clock (X1)has stabilized. When the external power drops to 3.2 V or below, the outputsignal from the backup IC (IC3), which has been input to pin 34 of the CPU,changes from "H" to "L" level. The CPU will then be in the backup state.
4. S(Signal)Meter Circuit The DC potential of pin 13 of IC104 is input to pin 3 of the CPU (IC5),converted from an analog to a digital signal, and displayed as the S-metersignal on the LCD.
5. Tone Encoder The CPU (IC5) is equipped with an internal tone encoder. The tone signal(67.0 to 254.1 Hz) is output from pin 11 of the CPU to the varicap of theVCO for modulation.
Page-5
5) CPU Terminal Functions: M38267M8L (XA413)
Page-6
No.
Pin
Nam
eS
igna
lI/
0L
ogic
Des
crip
tion
No.
Pin
Nam
eS
igna
1I/
0L
ogic
Des
crip
tion
1C
1C
1-
--
51P
15/S
EG
39F
/KE
YI
Act
ive
low
Fun
ctio
n ke
y in
put
2V
L1
VL
1I
A/D
LC
Dpo
wer
supp
ly52
P14
/SE
G38
K10
I-
3P
67/A
N7
SMT
IA
/DS
-met
erin
put
53P
13/S
EG
37K
11I
-
4P
66/A
N6
SQ
LI
A/D
Noi
se le
vel i
nput
for
squ
elch
54P
12/S
EG
36K
12I
-
5P
65/A
N5
BA
TI
A/D
Low
bat
tery
det
ecti
on in
put
55P
11/S
EG
35K
13l
-
6P
64/A
N4
BP
5I
A/D
Ban
d pl
an5
56P
11/S
EG
34K
14I
-K
ey m
atri
x in
put
7P
63/C
LK
22/A
N3
BP
4I
Ban
d pl
an4
57P
07/S
EG
33SF
TO
-V
CO
fre
quen
cy r
ange
cha
nge
8P
62/C
LK
21/A
N2
UL
IA
ctiv
ehig
hP
LL
unl
ock
sign
al in
put
58P
06/S
EG
32SD
OA
ctiv
e lo
wS
igna
det
ecti
on o
utpu
t
9P
61/S
OU
T2/
AN
1B
P1,
2I
A/D
Ban
d pl
ans
1 an
d 2
59P
05/S
EG
31A
FC
OA
ctiv
e hi
ghA
F to
ne c
ontr
ol o
utpu
t
10P
60/S
IN2/
AN
OM
OM
IA
ctiv
elow
Mon
itor
key
inpu
t60
P04
/SE
G30
DA
4O
-
11P
57/A
DT
/DA
2C
TO
UT
OD
/AC
TC
SS
tone
out
put
61P
03/S
EG
29D
A3
O-
12P
56/A
D1
DT
OU
TO
D/A
62P
02/S
EG
28D
A2
O-
DA
con
vert
er f
or e
lect
roni
c vo
lum
e an
d ou
tput
pow
er
13P
55/C
NT
R1
TSQ
DI
Act
ivel
owC
TC
SS
tone
det
ecti
on in
put
63P
01/S
EG
27D
A1
O-
14P
54/C
NT
RO
BE
PO
Pul
seB
eep
tone
out
put/
Ban
d pl
an 3
64P
00/S
EG
26D
A0
O-
15P
53/R
TP
1ST
B2
I/O
Act
ive
low
/pul
seC
TC
SS
uni
t det
ecti
on/S
trob
e si
gnal
to C
TC
SS
uni
t65
P37
/SE
G25
S25
O-
16P
52/R
TP
0M
UT
EI/
OA
ctiv
ehig
hM
icro
phon
e m
ute
66P
36/S
EG
24S
24O
-
17P
51/P
WM
1C
LK
OP
ulse
Ser
ial c
lock
out
put f
or P
LL
, CT
CS
S67
P35
/SE
G23
S23
O-
18P
50/P
WM
0D
AT
AO
Pul
seS
eria
l dat
a ou
tput
for
PL
L C
TC
SS
68P
34/S
EG
22S
22O
-
19P
47/S
RD
Y1
AC
KI/
0P
ulse
Ban
d pl
an 6
69P
33/S
EG
21S
21O
-
20P
46/S
CL
K1
STB
1O
Pul
seS
trob
e fo
r P
LL
IC
70P
32/S
EG
20S
20O
-
21P
45/T
XD
1U
TX
OP
ulse
UA
RT
dat
a tr
ansm
issi
on o
utpu
t71
P31
/SE
G19
S19
O-
22P
44/R
XD
1U
RX
IP
ulse
UA
RT
dat
a re
cept
ion
inpu
t72
P30
/SE
G18
S18
O-
23P
43/D
/TO
UT
TB
STO
Pul
seT
one
burs
t (17
50H
z) o
utpu
t (E
urop
ean
vers
ion)
73S
EG
17S
17O
-
24P
42/I
NT
2R
E2
IA
ctiv
elow
74S
EG
16S
16O
-
25P
41/1
NT
1R
E1
IA
ctiv
elow
Rot
ary
enco
der
lnpu
t75
SE
G15
S15
O-
26P
40
PTT
IA
ctiv
ehig
hP
TT
inpu
t76
SE
G14
S14
O-
27P
77
DSW
OA
ctiv
elow
77S
EG
13S
13O
-
28P
76
STD
I/O
Act
iveh
igh
Dev
iati
on a
djus
tmen
t dur
ing
tran
smis
sion
78S
EG
12S
12O
-L
CD
seg
men
t sig
nal
29P
75
DSD
IP
ulse
Dev
iati
on a
djus
tmen
t dur
ing
tran
smis
sion
79S
EG
11S
11O
-
30P
74
T3C
OA
ctiv
e lo
wT
X p
ower
ON
/OF
F o
utpu
t80
SE
G10
S10
O-
31P
73
P3
CO
Act
ive
low
PL
L p
ower
ON
/OF
F o
utpu
t81
SE
G9
S9O
-
32P
72
AF
PO
Act
ivel
owA
FA
MP
pow
er O
N/O
FF
out
put
82S
EG
8S8
O-
33P
71
R3C
OA
ctiv
elow
RX
pow
er O
N/O
FF
out
put
83S
EG
7S7
O-
34P
70/I
NT
0B
UI
Act
ivel
owB
acku
p si
gnal
det
ecti
on in
put
84S
EG
6S6
O-
35R
ES
ET
RST
IA
ctiv
elow
Res
etin
put
85S
EG
5S5
O-
36X
CIN
XC
IN-
--
86S
EG
4S4
O-
37X
CO
UN
TX
CO
UT
--
-87
SE
G3
S3O
-
38X
INX
IN-
-M
ain
cloc
k in
put
88S
EG
2S2
O-
39X
OU
TX
OU
T-
-M
ain
cloc
k ou
tput
89S
EG
1S1
O-
40V
SSG
ND
--
CP
U g
roun
d90
SE
G0
SOO
-
41P
27
PS
WI
Act
ivel
owP
ower
sw
itch
inpu
t91
VC
CV
DD
--
CP
U p
ower
term
inal
42P
26
SCL
OP
ulse
Ser
ial c
lock
for
EE
PR
OM
92V
RE
FV
RE
F-
-A
D c
onve
rter
pow
er s
uppl
y
43P
25
C3C
OA
ctiv
ehig
hC
3 po
wer
ON
/OF
F o
utpu
t93
AV
SSA
VSS
--
AD
con
vert
er g
roun
d
44P
24
SD
AO
Pul
seS
eria
l dat
a fo
r E
EP
RO
M94
CO
M3
CO
M3
--
-
45P
23
LM
PO
Act
iveh
igh
Lam
p O
N/O
FF
95C
OM
2C
OM
2O
-L
CD
CO
M2
outp
ut
46P
22
T/K
EY
IA
ctiv
elow
Ton
e bu
rst/
LP
TT
inpu
t96
CO
M1
CO
M1
O-
LC
D C
OM
1 ou
tput
47P
21
K00
I/O
-B
and
plan
BP
7 in
put
97C
OM
0C
OM
0O
-L
CD
CO
M0
outp
ut
48P
20
K01
O-
Key
mat
rix
outp
ut98
VL
3V
L3
I-
LC
D p
ower
sup
ply
49P
17
K02
O-
99V
L2
VL
2I
-L
CD
pow
er s
uppl
y
50P
16
K03
O-
100
C2
I-
-
Pag
e-7
Pag
e-8
PAR
TS
LIS
TC
PU U
nit/T
one
Uni
tR
ef.N
o.Pa
rtsN
o.D
escr
iptio
nPa
rts
Nam
eV
er.
Ref
.No.
Part
sNo.
Des
crip
tion
Part
s N
ame
Ver
.R
ef.N
o.Pa
rts
No.
Des
crip
tion
Part
s N
ame
Ver
.R
ef.N
o.Pa
rtsN
o.D
escr
iptio
nPa
rts
Nam
eV
er.
CPU
uni
tIC
5X
A04
02IC
M38
267M
8L-l
01FP
R35
RK
3058
Chi
p R
ER
J3G
SYJ4
73V
R10
01R
K30
46C
hip
RE
RJ3
GSY
J472
VC
1C
U30
35C
hip
CC
1608
JB1H
102K
TA
IC6
XA
0209
ICN
JM21
00M
T1
R36
RK
1018
Chi
p R
ER
J8G
EY
J101
VR
1002
RK
3048
Chi
p R
ER
J3G
SYJ6
82V
C2
CU
3035
Chi
p C
C16
08JB
1H10
2KT
AJ1
MA
CL
2GG
Wir
e#3
0A11
l-02
5-H
1R
37R
K30
38C
hip
RE
RJ3
GSY
J102
VR
1003
RK
3062
Chi
p R
ER
J3G
SYJ1
04V
C3
CS0
206
Chi
p T
anta
lT
MC
MD
0G10
7MT
RJK
1U
J001
9C
onne
ctor
HSJ
1493
-01-
010
R38
RK
3041
Chi
p R
ER
J3G
SYJ1
82V
R10
05R
K30
58C
hip
RE
RJ3
GSY
J473
VC
4C
U30
17C
hip
CC
1608
CH
1H33
0JT
-AS
JK2
UJ0
022
Con
nect
orH
SJ11
02-0
1-54
0R
39R
K30
38C
hip
RE
RJ3
GSY
J102
VR
1006
RK
3038
Chi
p R
ER
J3G
SYJ1
02V
C5
CU
3017
Chi
p C
C16
08C
H1H
330J
T-A
SL1
QC
0003
Coi
lM
LF3
216A
1R0K
-TR
40R
K30
68C
hip
RE
RJ3
GSy
J334
VR
1007
RK
3038
Chi
p R
ER
J3G
SYJ1
02V
C6
CS0
208
Chi
p T
anta
lT
MC
MA
0J47
5MT
RL2
QC
0003
Coi
lM
LF3
216A
1R0K
-TR
41R
K30
65C
hip
RE
RJ3
GSY
J184
VR
1008
RK
3001
Chi
p R
ER
J3G
SY0R
00V
C7
CU
3035
Chi
p C
C16
08JB
1H10
2KT
AL4
QC
0003
Coi
lM
LF3
216A
1R0K
-TR
42R
K30
61C
hip
RE
RJ3
GSY
J823
VR
1009
RK
3038
Chi
p R
ER
J3G
SYJ1
02V
C8
CU
3035
Chi
p C
C16
08JB
1H10
2KT
AL5
QC
0003
Coi
lM
LF3
216A
1R0K
-TR
43R
K30
58C
hip
RE
RJ3
GSY
J473
VR
1010
RK
3058
Chi
p R
ER
J3G
SYJ4
73V
C9
CS0
206
Chi
p T
anta
lT
MC
MD
0G10
7MT
RL6
QC
0442
Coi
lM
LF1
608A
1R0K
-TR
44R
K30
54C
hip
RE
RJ3
GSY
J223
VR
1011
RK
3038
Chi
p R
ER
J3G
SYJ1
02V
C10
CS0
373
Chi
p T
anta
lT
MC
MD
1C47
6MT
RL7
QC
0442
Coi
lM
LF1
608A
1R0K
-TR
47R
K30
52C
hip
RE
RJ3
GSY
J153
VR
1012
RK
3038
Chi
p R
ER
J3G
SYJ1
02V
C11
CS0
206
Chi
p T
anta
lT
MC
MD
0G10
7MT
RL8
QC
0442
Coi
lM
LF1
608A
1R0K
-TR
48R
K30
62C
hip
RE
RJ3
GSY
J104
VR
1013
RK
3001
Chi
p R
ER
J3G
SY0R
00V
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Tra
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Prot
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Ref
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152
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144E
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114
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3013
Chi
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168
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Chi
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Tan
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115
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Chi
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Tan
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101
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120
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Tra
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116
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Chi
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171
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3059
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103
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Chi
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173
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3053
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105
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Chi
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0
ADJUSTMENT1) Required Test Equipment
The following items are required to adjust radio parameters:1. Regulated power Supply voltage:5 ~ 14 VDC supply Current : 3 A or more
2. Digital multi meter Voltage range : FS = Approx. 20 V Current:10A or more Input resistance : High impedance
3. Oscilloscope Measurable frequency : Audio frequency
4. Audio dummy load Impedance: 8 ohm Dissipation: 1 W or more Jack:3.5 mm D
5. SSG Output frequency:200 MHz or more Output level : -20 dB/0.1 a V ~ 120dB/1V Modulation : AM/FM
6. Spectrum Analyzer Measuring range : Up to 2 GHz or more
7. Power meter Measurable frequency:Up to 200 MHz Impedance : 50 ohm unbalanced Measuring range : 0.1W ~ 10 W
Measurable frequency : Up to 100 kHz8. Audio voltmeter Sensitivity : 1 mV to 10 V
Output frequency : 67 Hz to 10 kHz9. Audio generator Output impedance : 600 ohm , unbalanced
Measurable frequency : 1 kHz10. Distortion meter Input level : Up to 40 dB /SINAD meter Distortion level : 1 % - 100%
Measurable frequency : Up to 200 MHz11. Frequency counter Measurable stability : Approx. +/-0. 1 ppm
Measurable frequency : Up to 200 MHz12. Linear detector Characteristics: Flat
CN:60 dB or more
Note* Standard modulation: 1 kHz +/-3.5 kHz/DEV* Reference sensitivity: 12dBSINAD*Specified audio output level : 200 mW at 8 ohm*Standard audio output level : 50 mW at 8 ohm*Use an RF cable (3D2W: 1 m) for test equipment.*Attach a fuse to the RF test equipment.*All SSG outputs are indicated by EMF.* Supply voltage for the transceiver: 13.8 VDC Page-21
D10
R1006
D3
R3R1
D1
LCD1
CN4
R1013
R1007
L10
SW402 SW404 SW401 SW403
D802
D804
R801D805
R802
D803
Q801
D801
