Discussed in class and on

Fridays

FSMs (only synchronous, with asynchronous reset)– Moore– Mealy– Rabin-Scott

Generalized register:– With D FFs,– With T FFs, transitions– Iterative circuits (using decomposition to one dimensional,

one-directional iterative circuits specified as FSMs)– Trade-off between FSM and iterative circuit– Parallel and serial adder– ALU with arithmetic and logic part.– Realization of all functions of 2 variables– Realization of all symmetric functions.

Generalization of generalized register to SIMD architecture– GAPP processor

Sequential Controller (SAT example) Pipelined architecture for vector processing Linear Systolic array for convolution Generate Statements

pipelined

Iterative circuit

(one dimensional)Finite state

machine

Iterative circuit

(general, n-dimensional)

systolicSequential

controller

Butterfly

combinational

Generalized

register

Data Path SIMD

Professor Perkowski

wants you to select

a good design pattern to get

an A in this class and become

a talented designer

Regular Regular StructuresStructures

Regular VHDL StructuresRegular VHDL Structures

Iterative Circuits Are Composed of Many Identical Circuits– Ripple-carry (RC) adder– RAM– Counters– Comparators

Generate Generate StatementStatement

Generate StatementGenerate Statement

Use Generate Statement to Reduce Coding Effort

Can Include Any Concurrent Statement Including Another Generate Statement

Does Not Execute Directly, But Expands into Code Which Does Execute

Generate Statement

Automatically Generates Multiple Component Instantiations

Two Kinds of Statements– Iteration

»FOR . . . GENERATE

– Conditional»IF . . . GENERATE

Iteration: FOR Generate

Instantiates Identical Components Syntax of FOR

identifier : FOR N IN 1 TO 8 GENERATE concurrent-statements END GENERATE name ;

– N is a constant and cannot be changed– “name” is required

Conditional: IF GENERATE

Takes Care of Boundary Conditions Syntax of IF

identifier : IF (boolean expression) GENERATE concurrent-statements END GENERATE name ;

– Cannot use “else” or “ifelse” clauses

4 Bit Ripple Carry Adder4 Bit Ripple Carry Adder

A B

S

Ci

Co

A B

S

Ci

Co

A B

S

Ci

Co

A B

S

Ci

Co Cin

A(0)

Cout

B(0)A(1) B(1)A(2) B(2)A(3) B(3)

C(0)C(1)C(2)C(3)C(4)

Sum(0)Sum(1)Sum(2)Sum(3)

Want to write a VHDL model for a 4 bit ripple carry adder. Logic equation for each full adder is: sum <=   a xor b xor ci; co     <=   (a and b) or (ci and (a or b));

ENTITYENTITY for Generate for Generate e.g., Ripple Carry e.g., Ripple Carry ((R-C) AdderR-C) Adder

ENTITY RCAdder_16 IS

PORT

( A, B : IN Bit_Vector (15 downto 0);

Cforce : IN Bit ;

Sum : OUT Bit_Vector(15 downto 0);

Cout : OUT Bit ) ;

END RCAdder_16 ;

This is an adder with 16 bits!!

Architecture and SIGNAL for Generate e.g., R-C Adder

ARCHITECTURE Generate_S OF RCAdder_16 IS

COMPONENT Full_Adder

--defined elsewhere

PORT ( A, B, Cin : IN bit ;

S, Cout : OUT bit );

END COMPONENT Full_Adder ;

SIGNAL Int_C : BIT_VECTOR (15 DOWNTO 0);

Use of Generate in R-C Adder for I = 0

BEGIN --RC Adder All_Bits: FOR I IN 15 DOWNTO 0 GENERATE LSB : IF (I = 0) GENERATE

BEGIN S0: Full_Adder

PORT MAP ( A(I), B(I), Cforce, Sum(I), Int_C(I) ); END GENERATE S0 ;

Generate e.g., R-C Adderfor Middle Bits

Middle_bits:

IF ( I < 15 AND I > 0 ) GENERATE

BEGIN

SI: Full_Adder

PORT MAP ( A(I), B(I), Int_C(I-1),

Sum(I), Int_C(I) );

END GENERATE SI;

Generate e.g., R-C Adder for Most Significant Bit

MSB:

IF ( I = 15 ) GENERATE

BEGIN

S15: Full_Adder

PORT MAP ( A(I), B(I), Int_C(I-1),

Sum(I), Cout );

END GENERATE MSB;

END GENERATE All_Bits

END Generate_S ;

But what we should do if we But what we should do if we want to have a parameterized want to have a parameterized design not for 16 but for some design not for 16 but for some parameter N?parameter N?

LENGTH and Unconstrained Ports

Entity Declarations Can Have Ports Defined Using Arrays Without Explicitly Including the Size of the Array

Leads to General Specification of Iterative Circuit

Uses Predefined Array Attribute ‘LENGTH

Using LENGTH and Generate for the R-C Adder

ENTITY RCAdder_N IS

PORT ( A, B : IN Bit_Vector ;

Cforce : IN Bit ;

Sum : OUT Bit_Vector ;

Cout : OUT Bit ) ;

END RCAdder_N ;

I am not specifying how long is this vector of bits

ARCHITECTURE Generate_S OF RCAdder_N IS

COMPONENT Full_Adder --defined elsewhere

PORT ( A, B, Cin : IN bit ;

S, Cout : OUT bit ) ;

END COMPONENT Full_Adder ;

SIGNAL Int_C : BIT_VECTOR

( (A’LENGTH - 1) DOWNTO 0);

Uses Predefined Array Attribute ‘LENGTH

Using LENGTH and Generate for the R-C Adder

This is local A from component

This is global A from entity

BEGIN --RC Adder All_Bits:FOR I IN (A’LENGTH -1) DOWNTO 0 GENERATE

LSB:IF (I = 0) GENERATE

BEGIN S0: Full_Adder

PORT MAP ( A(I), B(I), Cforce, Sum(I), Int_C(I) );

END GENERATE S0 ;

For primary input, not iterative carry

Please remember that FOR used here is for structure description. It is different than LOOP used in behavioral descriptions in future

Using LENGTH and Generate for the R-C Adder = LSB

Middle_bits:

IF ( I < ( A’LENGTH - 1 ) AND I > 0 ) GENERATE

BEGIN

SI: Full_Adder

PORT MAP ( A(I), B(I), C(I-1),

Sum(I), Int_C(I) );

END GENERATE SI ;

Using LENGTH and Generate for the R-C Adder = Middle Bits

Generate e.g., R-C Adder

MSB:

IF ( I = A’LENGTH - 1 ) GENERATE

BEGIN

SN: Full_Adder

PORT MAP ( A(I), B(I), INT_C(I-1),

Sum(I), Cout );

END GENERATE MSB;

END GENERATE All_Bits

END Generate_S ;

For primary output, not iterative carry out

Using LENGTH and Generate for the R-C Adder = Most Significant Bit

Problems for students to think aboutProblems for students to think about1. Generate statement for one dimensional combinational regular

structures.

2. Generate statement for two-dimensional combinational regular structures.

3. Generate statement for many dimensional circuits.

4. Generate statement for regular structures of finite state machines and generalized shift registers.

5. How to describe GAPP processor and similar FPGA structures using “Generate”.

6. Importance of the “generalized register” model as a prototype of many combinational, sequential, cellular and systolic circuits.

Slides used

Prof. K. J. Hintz

Department of Electrical and Computer Engineering

George Mason University