direct 100g connectivity with optoelectronic polymer-inp ... · direct 100g connectivity with...

POLYSYS D5.1: Modelling of POLYSYS packaging methodology

Direct 100G connectivity with optoelectronic POLYmer-InP integration for data center SYStems Grant Agreement no. 258846 Specific Targeted Research Project (STREP) Information & Communication Technologies (ICT)

Deliverable D5.1 Modelling of POLYSYS packaging methodology Lead beneficiary for this deliverable: TEO Contact Person: Address: Linkra, Agrate Brianza, Italy Phone: +39 039 6418 1 e-mail: [email protected] Date due of deliverable: 30 September 2011 Actual submission date: 14 November 2011 Authors: Lucio Cibinetto, Heinz-Gunter Bach,

Jung Han Choi, Detlef Pech, Thomas Rosin

Participants: TEO, HHI

Work-package: WP5

Dissemination level: Nature: Version: Total number of pages:

Public Report 1.0 25


Executive Summary:

In this document the preliminary definitions of the POLYSYS packaging methodology will be described. The methodology presented is the approach to the packaging of the 6 modules that will be combined to realize three systems. This methodology is based on the actual level of know-how and will be updated and detailed according to the evolving of the project. Packaging methodology described in this document constitutes the base for D5.2 – Delivery of 100 Gb/s transmitter module and the reference for future modules to be produced.

1 List of Acronyms

BCB Benzocyclobutene polymer

BER Bit Error Ratio

BG Bragg Grating

BPM Beam Propagation Method

CDR Clock & Data Recovery

CPW Coplanar transmission line

CW Continuous Wave

CWDM Coarse wavelength division multiplexing

DEMUX Demultiplexer

DFB Distributed Feedback Laser

DFF D Flip-Flop

DHBT Double Heterojunction Bipolar Transistors

EO Electro-Optic

ETDM Electrical Time Division Multiplexed

GPPO Gilbert Corning coaxial RF connector up to ~65 GHz

GbE Gigabit Ethernet

HBT HeteroJunction Bipolar Transistor


InP Indium Phosphide

MMI Multimode Interference

MS Microstrip line

MUX Multiplexer

MZ Mach Zehnder

MZI Mach Zehnder Interferometer

MZM Mach Zehnder Modulator

NRZ Non Return to Zero

OEIC OptoElectronic Integrated Circuit

OOK On-Off Keying

OSNR Optical Signal to Noise Ratio

PDL Polarization Dependent Loss

PIC Photonic Integrated Circuit

pin p-i-n photodiode

pinTWA pin photodiode with monolithically integrated travelling wave amplifier (i.e. an OEIC)

PLC Planar Lightwave Circuits

PMD Polarization Mode Dispersion

SMF Single Mode Fiber

TEC Thermo Electric Cooler

TIA TransImpedance Amplifier

TWA Travelling-wave Amplifier

VSR Very Short Reach

WDM Wavelength Division Multiplexing

WGL Waveguide Grating Laser


Table of Contents 1 List of Acronyms .......................................................................................................................2 2 Introduction ..............................................................................................................................5 3 Modeling and simulation studies .............................................................................................6

3.1 Electromagnetic Evaluation ................................................................................................6 3.2 Wire bonding and electrical interconnections ...................................................................9 3.3 Package design ................................................................................................................. 10 3.4 Thermoelectric design ..................................................................................................... 10 3.5 Optical design .................................................................................................................. 13

4 Methodologies for 100 Gb/s transmitter .............................................................................. 15 5 Methodologies for 4x100 Gb/s pin/pinTWA-DEMUX modules ............................................. 16

5.1 Main components constituting the 4-channel pin-or pinTWA-DEMUX modules ........... 16 5.2 Co-Packaging concept of InP-based pin/pinTWAs and InP-HBT-based DEMUX ICs ........ 19 5.3 Miscellaneous components and biasing protection circuitry .......................................... 22

6 Conclusion.............................................................................................................................. 23 List of Figures ................................................................................................................................. 24 List of Tables .................................................................................................................................. 25


2 Introduction

In POLYSYS project, the packaging of the photonic and electronic devices that will be developed

represents the final step in the fabrication chain.

During the packaging activities, many aspects must be considered for a proper design and

realization of such devices; the correct modeling of parts, through the electromagnetic

evaluation, the design of the electrical interconnections and the thermoelectric and the optical

design, is fundamental in order to achieve POLYSYS aims.

The packaging approaches here described will be based on well-established existing technology,

in order to be able to handle bit rates of up to 100 Gb/s required for the project.

Each one of the six packages that will be realized should be implemented considering several

design factors. The latter include the DC and RF inputs and outputs connections, the optical

mode size diameter optimization, in order to achieve a good coupling efficiency between fiber

and active devices, and, last but not least, the thermal management in order to ensure that the

device performance is not critically affected by temperature. The electrical connections will be

carefully designed to reduce or minimize any unwanted effects (crosstalk, loss), in particular for

the RF electrical paths.

Key design features will be described for each relevant section. Moreover, the example case of

the package for the 100 Gb/s transmitter (corresponding to deliverable D5.2) will be described

in short and the cases of the packages for the 4x100 Gb/s receivers (corresponding to a part of

the deliverable D5.4 and the deliverable D5.5) will be described in more detail..


3 Modeling and simulation studies

3.1 Electromagnetic Evaluation

One of the most critical issues of package integration and packaging process in general is the

design of high-speed wire bondings for the RF connections between the devices inside the

package.

Special care should be adopted designing the interconnections between active devices (DEMUX,

DRV, CDR, pinTWA) and the other components (MZM) and passive components (biasing-

decoupling RC, external output connectors).

Alumina substrates represent the best choice for matching the thermal expansion of package

material (KOVAR – CTE = 5.10 - 5.50 µm/m-°C, ALUMINA – CTE = 6.50 - 7.80 µm/m-°C). To

interconnect active devices to the output connectors, microstrip on 250µm thick Alumina

substrate will be adopted.

RF signals will be connected to the chip with wire/ribbon bonding. Coaxial output connectors are

directly mounted on package walls and brazed to microstrip. Coaxial connectors types will be

selected accordingly to HF specification between GPPO, 1mm-V connectors or coplanar output

stripline.

To interconnect MUXDRV/DEMUX chip to output connectors, a suitable AlO3-based stripline is

necessary. The stripline is designed around a 250 µm thick AlO3 substrate so as to exhibit 50 Ω

impedance characteristics.

The RF characteristics of the substrate are simulated with the simulation suite ANSYS HFSS™ (3D

Full-wave Electromagnetic Field Simulation). The examples below represent a typical set of

results for this type of simulations, and refer to an existing structure, which has not been

optimized for the frequency range requested by POLYSYS.

(a) (b)

Figure 1: (a) Design of AlO3 substrate, and (b) example of AlO3 substrate and DC block.


Figure 2: Parameters definition for HFSS simulation.


Figure 3: Simulation results

The set of parameters for the simulation of substrate of Figure 1a are indicated in Table 1.

Table 1: HFSS simulation parameters.

Sustrate Type AlO3

Substrate Thickness 10 mils

Line Material GOLD

Line Thickness 5 µm

Connectors Dielectric Material GLASS

Brazing Material INDIUM


3.2 Wire bonding and electrical interconnections

Critical wire-bondings are those between active chips and interface substrates. In order to keep

the length of wire as short as possible, each part must be mounted as close as possible

(maximum distance<50µm). To reduce the effects of inductive discontinuity, double or triple

parallel wire bonding can be adopted (reducing inductance). Double wire bonding (up to three)

with 18 µm gold wire provide good results when length is kept below 150µm. Ribbon wire

bonding can be used for DC biasing connections and low frequency connections. Particular care

should be taken to design the HF lines, output and clock input lines, in order to exhibit

comparable signal propagation delay times. The electro-magnetic environment within the

packaged device and high frequency wire bonding connections between output lines to external

connectors will be simulated with electro-magnetic simulator in order to identify the level of

cross-talk on high speed data paths. During the assembly procedure, any solder or epoxy reflow

under the dies should be avoided in order to limit unwanted regrowth of the bonding material.

(a) (b)

Figure 4: (a) Example of triple 18µm wire bonding, and (b) Example of RF and DC wire bondings.

Figure 5: Example of HF connectors brazed on substrate.


3.3 Package design

To guarantee good mechanical properties and the correct CTE matching of materials, package will be realized in KOVAR (FeNiCo). If thermal dissipation of active devices (MUXDRV, DEMUX, DFB LASER) will be an issue, the base of the package will be made of CuW in order to increase the relative low thermal conductivity of KOVAR.

All the electronic and optic components will lie on a suitable gold plated submount (CuW, AlNi). The submount will be designed to hold the chip in position, and to work as mechanical support for the optical parts (i.e. fiber) and for the DC coupling substrates as well.

The packaged device will be simulated to identify the RF and the thermal behavior, especially to estimate the level of cross-talk of high speed data paths. The contingency plan in case of high level of cross-talk, provides the use of proper RF absorbers inside the package.

The packages can be designed to have as many DC connections as needed. DC connections can be on ceramic or glass feed-through. The second option is preferable for low volumes production. The chip layout should follow the design rules to keep the DC connection pads on lateral sides.

RF connectors, should outstand, if needed, to a specific pitch depending on the connector type. DC connection pads on lateral sides. Design of hybrid circuits on Alumina substrates should outstand at following design rules, where dimensions and positions of bonding pads are defined.

Figure 6: General layout rules

3.4 Thermoelectric design

Thermal management in optoelectronics packaging is very critical. In fact, bad thermal design can lead to optical and mechanical failures that will generate long term reliability problems due to heat dissipation of active device. If the temperature inside the package reaches significant ly high values, two main options can be considered to proceed: the use of an integrated heat sink with flat heat pipes or the adoption of a thermo electric cooler device (TEC).

The first option implies that the package overall dimensions could increase significantly. This should not be an issue for prototypes and demonstration units.


Using a TEC, on the other hand, assembly process complexity should be considered (soldering materials, dimensions, number of electrical connections), together with the necessity of the use of an external TEC control unit or circuit.

For these applications, thermal analysis has been implemented using Pro-E Mechanica (3-D finite element modelling tool). The simulation software helps to estimate the device thermal dissipation behavior. To perform the thermal analysis, an initial set of material properties has been defined, as outlined in Table 2 below.

Table 2: Material properties

MATERIAL Si GaAs WCu InP KOVAR

Type Orthotropic Orthotropic Isotropic Orthotropic Isotropic

Density [kg/mm^3]

2.329e-06 5.316e-06 1.56e-05 4.787e-06 8.36e-06

Young's Modulus [kPa]

1.124e+08 6.11e+07 2.8e+08 6.11e+07 1.38e+08

Poisson's Ratio 0.28 0.3 0.3 0.3 0.317

Conductivity [mm kg /(sec^3 C)]

105000 50000 210000 80000 17300

Specific Heat [mm^2/(sec^2 C)]

7.13e+08 3.25e+08 1.95e+08 325 4.39e+08

2.49e-06 [/C]

5.4e-06 5.4e-06 8e-06 4.6e-06 5.86e-06

Shear Stiffness [kPa]

4.39062e+07 2.35e+07 1.07692e+08 2.35e+07 5.23918e+07

Failure Criteria None None None None None

3D FEA mesh is built on a simplified model of the whole package assembly.

(a) (b)

Figure 7: (a) 3D model, and (b) 3D FEA model.


Table 3: Mesh controls

Mesh Controls

Mesh Control AutoGEMControl1

AutoGEMControl2

AutoGEMControl3

AutoGEMControl4

AutoGEMControl5

Type Maximum Element Size

Maximum Element Size




References NONE-45973.PRT NONE-50170.PRT NONE-45569.PRT

NONE-45837.PRT SI_BOARD.PRT

SUBMOUNT_003.PRT

TX_PACKAGE_SOLID.PRT

Value 0.1 [mm] .4 [mm] 2 [mm] 5 [mm] 6 [mm]

Below the results of the thermal study made on first package design are presented.

Figure 8: Thermal simulation results.

Figure 9: Thermal simulation results (active devices)


Table 4: Measured values

Measures

energy_norm 9.7166e+007

max_flux_mag 9.61976e+006

max_flux_x -8.41555e+006

max_flux_y -8.49157e+006

max_flux_z -8.04748e+006

max_grad_mag 172.291

max_grad_x -108.787

max_grad_y 80.8721

max_grad_z 160.95

max_temperature 94.7277

min_temperature 60.8638

Simulation results can be verified on assembled devices using thermo-scanning of heat dissipative area: below an example of typical thermal map.

Figure 10: Example of a thermal map.

3.5 Optical design

The method on how the fibers are connected/aligned to the optical chip depends on the design approach. The fibers could be butt-coupled to the waveguides or in-air aligned to the waveguides. Waveguide optical profile characterization will define the best coupling method in order to achieve the best coupling efficiency. Lensed or reduced core fibers are the two possible options for pigtailing.

Table 5: Typical fiber characteristics

PM Reduced Core Fiber SM Reduced Core Fiber SM Lensed Fiber

OPERATING WAVELENGTH [nm] 1550 1550 1550

LENS ROC [µm] NA NA 1 4

MFD @ 1550 nm [µm] 4.8 +/- 0.5 4.0 4.5 ± 0.5 µm

NUMERICAL APERTURE 0.26 0.35

SECOND MODE CUTOFF [nm] 1330 +/- 50 1050 +/- 50 <1260


Figure 11: Lensed fiber characterization results.

The methodology for the alignment of the input/output fibers to the waveguides will use existing V-grooves present on the optical boards or properly designed fiber supports mounted on the optical submount. The fixing technology will be chosen between epoxy, solder or LASER welding. Components of the same system could so adopt different fiber fixing technology.

The minimum pitch between optical fibers is 500µm. The fibers, lensed or cleaved, are directly placed in front of the waveguide optical facet. No lenses are planned to be used in the optical path waveguide-air-fiber. Fibers can be mounted on a suitable bored block (i.e. BK7) in order to enable the butt-coupling between waveguides and fiber. According to the design, reduced core fiber could be used to match the mode field diameter of the waveguides. UV optical epoxy glue will be used to fill the transition waveguide-air-fiber and to realize the mechanical fixing of the parts. The output facet of the waveguides can be both straight or, in order to reduce the optical back-reflection, cleaved with a proper angle: angled chip will obviously increase the package dimensions since the optical output must be straightened to the fiber.

To guide the optical fiber through the wall of the package, optical feed through (tubes) are used. These tubes are necessary to guide the fiber through the wall of the package and to create the relevant hermetic transition. Every tube carry one single fiber.

(a) (b)

Figure 12: (a) Design of optical feed-through, and (b) Optical feed-through and hermetic sealing


4 Methodologies for 100 Gb/s transmitter

The results of the methodologies described before are represented in Figure 13, where the initial design of the 100 Gb/s transmitter module of Deliverable D5.2 is depicted.

The optical package is made of metalized FeNiCo (KOVAR). The RF connectors are GPPO, while DC output are glass feed through “dog leg” PIN. The main submount that holds both optical and electrical components is made of CuW. The output modulator waveguide is coupled to a lensed fibre. Enough space has been reserved into the package to handle the fibre during the alignment process. Particular care has been taken to keep the RF path as short as possible. The package and the relevant techniques and methodologies will be described in more detail in deliverable D5.2, which is planned for M18 of POLYSYS.

Figure 13: Initial design of the 100 Gb/s transmitter module.


5 Methodologies for 4x100 Gb/s pin/pinTWA-DEMUX modules

Co-packaging allows the significant reduction of RF losses between an optoelectronic frontend (pin or pinTWA OEIC) and subsequent electronics, e.g. DEMUX. Those losses at 100 GHz frequencies can be estimated to amount to 2 dB per interconnector and 2 dB for a Bias-T, often needed between separate modules. Thus about 6 dB of passive interconnection losses is addressed to be avoided by co-packaging and direct dc-coupling of 100G O/E components, in this case for a chain of chips forming a 100/107 Gbit/s 1:2 demultiplexing photoreceiver.

For co-packaging of pin-diode or pinTWA-OEIC arrays and subsequent DEMUX ICs into a common housing, to form the 4-channel “4x100 Gb/s pin/pinTWA-DEMUX-Photoreceiver Modules” HHI employs self-fabricated 100 Gbit/s pin-diode or pinTWA-OEIC arrays (4x) and 4 digital 100 Gbit/s DEMUX chips supplied by ATL. Packaging experience inhouse and from the preceding GIBON project are employed to extend the housing concept to an arrayed receiver type with 4 channels. Only one RF critical electrical interface between the pin- or pinTWA chips and the DEMUX chips has to be cared by multiple wire bonding.

The 50 Gb/s DEMUX outputs are to be connected tentatively via quartz-based combined coplanar and microstrip lines to GPPO connectors, to provide the 8x 50 Gb/s data outputs (400 Gb/s as the sum data rate). Further, non-critical RF connectors (GPPO) for 50 Gb/s rates will be provided for the 4 clock input signals. Thus, a total of 12 GPPO connectors each carrying 50 Gb/s signals are scheduled in the receiver module.

Packaging of 4x pin-DEMUX and 4x pinTWA-DEMUX receivers will be done employing a common fiber array concept defining a 1mm pitch of fibres regards optical coupling to the receiver chips and co-packaging with the DEMUX chips within the same housing:

- Module 4a (4x pin-PD – DEMUX array receiver module) M30

- Module 4b (4x pinTWA-PD – DEMUX array receiver module) M32

In the following different basic aspects of co-packaging work will be addressed.

5.1 Main components constituting the 4-channel pin-or pinTWA-DEMUX modules

A) 4x 100 G pin diode and pinTWA photoreceiver arrays: HHI develops and fabricates in POLYSYS 4-channel waveguide-integrated photodiode arrays and monolithically integrated pinTWA receiver arrays, comprising 4 travelling-wave amplifiers (TWA) with pin diode frontends.

Concerning the photodiode arrays Figure 14 shows 4-channel pin diode receiver arrays in double column from maskset POLY-PD-01. It is planned to couple a fibre array with 1 mm optical pitch to the facet of the receiver array. This concept holds for pin and for pinTWA, in the latter case the width of the single receiver chip is challenging to place all components of the HEMT-based TWA within this measure. It was agreed with ATL that the same 1mm pitch will be obeyed also for the subsequent DEMUC ICs.

As far as the mounting is concerned, the PD and receiver chips may be glued to a conductive base inside the module due to the insulating properties of the InP:Fe semi-insulating substrate.


Figure 14: 4-channel pin diode receiver array in double columns from maskset POLY-PD-01 (left) 4-channel pinTWA receiver array in single column from maskset POLY-WARP-01 (right).

The concept of fibre array coupling to the receiver OEICs (pin or pinTWA) is depicted in Figure 15. This arrangement guarantees ultra short bond wire interconnections between optical frontends and digital circuits, to allow good receiver sensitivities.

Figure 15: Fibre array coupling (from below) to the pin or pinTWA receiver OEICs; the subsequent DEMUX ICs obey the same pitch. An array from Adamant is shown on the right hand side.

For the fibre arrays elements of Adamant company will be considered, which offer arrays with 0.5 micron precision of the 1mm pitch distance of the four fibres. On the semiconductor side the pitch will be controlled by e-beam writing of the masks with adequate precision.

From recent EC projects GIBON and HECTO some single-channel 100 Gb/s photoreceiver OEICs were selected and packaged and given to ICCS/NTUA for characterization purposes and for system setup tests (pinTWA receiver modules C05-W45 and C05-W50).

Figure 16 shows typical single-channel pinTWA receiver OEICs from a bar of receivers.


Figure 16: Fabricated TAPTWA100 pinTWA photoreceiver OEICs from WARP100 maskset.

Figure 17: Packaged pinTWA photoreceiver OEIC within module C05-W50, given to NTUA for system setup and test purposes; the o/e conversion properties (25 V/W) are depicted at the right hand side.

From this pinTWA packaging work, cf. to Figure 17, a bunch of experiences was gained regards gluing the chips into a brass housing, coupling single-mode fibres in front of the tapered input waveguides of photodetectors and doing ultra short multiple wire bonding on small coplanar RF outputs pad (see picture in the middle) to achieve low-loss interconnections between InP chips and coplanar lines on quartz substrates. These experiences have been started to share with TEO, due to their planed use of HHI’s receiver OEICs.

B) InP-HBT-based DEMUX ICs for 100 Gb/s: In POLYSYS advanced InP-HBT-based high-input-sensitivity DEMUX ICs will be developed by ATL. Preliminary experience with co-packaging of HHI InP-based receiver OEICs and the digital DEMUX ICs from ATL has been gained through preceding collaborations of HHI with ATL, where receiver OEICs where co-packaged together with decision D flip-flop (DFF) integrated circuit. The IC circuit design approach is described within the paper reported in /ECOC 2009 (Wien), paper 9.2.6/, but modified to accommodate the need of bitrates up to 107 Gb/s. The decision circuit IC (micrograph of the IC shown in Figure 18) comprises an input for the clock signal at the bottom side and differential data outputs at the right side.

Figure 18: Microphotograph of a ½-DEMUX in 0.7 µm HBT technology by ATL.


The total power consumption is 0.7… 0.8 W. These chips are fabricated on semi-insulating substrate and can be directly glued to a conductive base like the receiver OEICs.

5.2 Co-Packaging concept of InP-based pin/pinTWAs and InP-HBT-based DEMUX ICs

The co-packaging of preliminary DEMUX-IC (cf. to Figure 19) with the pinTWA OEIC gave insight and practical results regards the thermal management of a single-channel 100 Gb/s demultiplexing receiver, where operation of a passively cooled pinTWA-DEMUX module was carried out successfully.

Figure 19: Microphotograph of a co-packaged pinTWA-DEMUX photoreceiver module; the critical 100G interface between pinTWA chip and DEMUX IC applying multiple wire bonding is shown on the right.

The experiences from a single-channel demuxing receiver will be expanded to POLYSYS, where a 4-channel chain of pinTWA and DEMUX (OE)ICs is projected. Actually it is expected, that even a 4-channel Rx module consuming around 4W may be operated with passive cooling, but mounting the module to an additional external heat sink.

The concept of the 4-channel (4x 100G) pin-DEMUX or pinTWA-DEMUX photoreceiver is shown in Figure 20. From bottom to top the 4 fibres are coupled via a fibre array into a monolithic block of 4 pin photodiodes or 4 pinTWA photoreceivers, obeying a pitch of 1mm between adjacent fibres. The DEMUX ICs fit within this 1mm pitch, too and will be provided tentatively in blocks of two DEMUXs, which are closely mounted aside to each other, to support ultra short wire bonding between the RF output pads of the frontend OEICs and the demultiplexing digital ICs.

The output facets of the DEMUXs ICs (right hand side picture within fig. HHI-08) will carry the interfacing of (4x) demuxed dual single-ended 50 Gb/s tributaries, and between the output tributaries feeding the individual clock signals into the DEMUX ICs from outside.

Figure 20: Concept of 4-channel (4x 100G) pin-DEMUX or pinTWA-DEMUX receiver packaging; the right hand side viewgraph depicts a foreseeable DEMUX chip with its 100 G input at the left and its two demuxed tributaries and the 50 G clock input at the right hand sides.


The biasing of the optical frontend OEICs and the DEMUX ICs will be managed applying a cross bar concept from two sides (north and south biasing), where mirrored bias pads will be provided on both sides of the (OE)ICs to have a feed-through of DC bias signal, thus avoiding uncontrolled longer bonding wiring. The delay times of at least three adjacent I/O lines of the four DEMUC ICs will be kept identical, leading to a circular arrangement of the 12 GPPO connectors, each carrying 50 Gb/s resp. 50 GHz signals.

The concrete design of the interconnection lines between DEMUXs 50G I/Os and the GPPO connectors is elucidated in more detail in Figure 21.

Figure 21: Concept of interfacing the 50 G I/Os of the 4 DEMUX ICs to the 12 GPPO connectors.

The detailed transitions between both coplanar and microstrip lines are under investigation. Coplanar lines fit well to the ICs, while microstrip lines may exhibit lower losses over several mm and may be well fitted to the GPPO connectors, too.

In order to better assess the different interconnection concepts, the Table 6 comprises several combinations of 50 Ohm designed coplanar (CPWG) and microstrip lines (MSL) interfacing to e.g. GPPO connectors, based on a quartz substrates of different thicknesses carrying Au electroplated MSL or CPW lines, which have to obey standard G-S-G pitch of the (OE)ICs and the mechanical constraints of the connectors.

Table 6: Study of MSL and CPW lines on quartz substrates interfacing between ICs and different connector types, espec. to GPPO connectors.


Table 6 will be completed by adding estimated loss values for the different geometries. The reason preferring quartz against simple alumina is motivated by relatively low losses of quartz-based MS oder CPW transmission lines. One example is given from a preliminary test structure investigation.

Quartz-based coplanar (CPW) lines were designed to fit the DEMUX to interconnect with two V-connectors. The coplanar lines were fabricated on 100 µm thick quartz substrate with

dimensions to exhibit 50 characteristics. The CPW lines are shown below in Figure 22 (left) designed and (right) fabricated. The length of the line is 13.8mm, comparable to the size needed for the packaging of the DEMUX. This is only chosen for on-wafer characterization of the CPW lines. Via holes serve to suppress parallel plate mode resonances. The RF characteristics of these lines are shown in Figure 23.

The insertion (S21) and return loss (S11, S22) were < 0.14 dB/mm and 15 dB respectively. During

the packaging of the chips, the substrate will be cut at the dashed lines.

Figure 22: CPW lines on quartz-substrate, left: designed and right: fabricated.

Figure 23: S-parameter measurements of the fabricated CPW lines on quartz-substrate.

Fairly low output interconnection losses of ~1.5 dB are expected for the demultiplexed data outputs as well as for the half-rate clock input (50 GHz). Nevertheless the radius of the interconnection lines between DEMUX ICs and GPPO connectors should be decreased further. As the NRZ coded data exhibit a zero in the spectrum at the frequency according to the data rate, the notch after 60 GHz should not be detrimental for 50..56 Gb/s operation.

The final elaborated layout, adapted to the 4-channel approach, will be given in a subsequent report and update of the packaging methodology. Figure 24 provides a provisional 3D sketch of the main constituting parts of the 4-channel 400 Gb/s demultiplexing photoreceiver.


Figure 24: 3-D sketch of chip arrangement, optical coupling and output network to GPPO connectors (w/o sidewalls of receiver module) of the planned 400 Gb/s demultiplexing photoreceiver module.

5.3 Miscellaneous components and biasing protection circuitry

Further components constituting the pinTWA-DEMUX module are bias protection elements, fiber coupling components, filtered bias-feed-through elements, GPPO connectors and the fiber feedthrough of the coupling array.

The ESD protection of the pinTWAs with its photodiode and the DEMUX chips is typically achieved by using circuitries according to Figure 25, already proven in previous receiver packaging activities. Each bias terminal is filtered by a parallel combination of an RF blocking capacitor of 100 nF and an appropriately dimensioned zener diode. The zener diode is designed for protecting the terminal without adding unwanted DC leakage. Thus, the currents to be measured at the terminals for a certain supply voltage swing are representative for the chip data.

Figure 25: ESD protection of the pinTWA and DEMUX biasing terminals of the pinTWA-DEMUX module.


6 Conclusion

In this document the packaging methodology that will be adopted in POLYSYS project has been described. Many aspects have been covered (modelling of parts, electromagnetic and thermoelectric evaluation, electrical interconnections and optical path, RF fan outs).

The packaging methodology described is based on the actual technology and is appropriate to guarantee the realization of the 6 modules required by the project.

Considering the high level of integration and the special properties/characteristics of some of the devices to be produced, this methodology can be updated and improved according to the project evolution.

First device that refer to the general packaging methodology described in the first part of this document is the 100 Gb/s transmitter module, which will be reported in deliverable D5.2. Beyond this general methodology, specific steps that will be used for the fabrication of the arrayed receiver modules (to be reported in D5.4 and D5.5) have been described in more detail in section 5 of the present report.


List of Figures Figure 1: (a) Design of AlO3 substrate, and (b) example of AlO3 substrate and DC block. ..............................6 Figure 2: Parameters definition for HFSS simulation. ......................................................................................7 Figure 3: Simulation results .............................................................................................................................8 Figure 4: (a) Example of triple 18µm wire bonding, and (b) Example of RF and DC wire bondings. ...............9 Figure 5: Example of HF connectors brazed on substrate. ...............................................................................9 Figure 6: General layout rules ........................................................................................................................10 Figure 7: (a) 3D model, and (b) 3D FEA model. ..............................................................................................11 Figure 8: Thermal simulation results. ............................................................................................................12 Figure 9: Thermal simulation results (active devices) ....................................................................................12 Figure 10: Example of a thermal map. ..........................................................................................................13 Figure 11: Lensed fiber characterization results. ...........................................................................................14 Figure 12: (a) Design of optical feed-through, and (b) Optical feed-through and hermetic sealing .............14 Figure 13: Initial design of the 100 Gb/s transmitter module. ......................................................................15 Figure 14: 4-channel pin diode receiver array in double columns from maskset POLY-PD-01 (left) 4-channel pinTWA receiver array in single column from maskset POLY-WARP-01 (right). ............................................17 Figure 15: Fibre array coupling (from below) to the pin or pinTWA receiver OEICs; the subsequent DEMUX ICs obey the same pitch. An array from Adamant is shown on the right hand side. .....................................17 Figure 16: Fabricated TAPTWA100 pinTWA photoreceiver OEICs from WARP100 maskset. ........................18 Figure 17: Packaged pinTWA photoreceiver OEIC within module C05-W50, given to NTUA for system setup and test purposes; the o/e conversion properties (25 V/W) are depicted at the right hand side. ................18 Figure 18: Microphotograph of a ½-DEMUX in 0.7 µm HBT technology by ATL. ...........................................18 Figure 19: Microphotograph of a co-packaged pinTWA-DEMUX photoreceiver module; the critical 100G interface between pinTWA chip and DEMUX IC applying multiple wire bonding is shown on the right. ......19 Figure 20: Concept of 4-channel (4x 100G) pin-DEMUX or pinTWA-DEMUX receiver packaging; the right hand side viewgraph depicts a foreseeable DEMUX chip with its 100 G input at the left and its two demuxed tributaries and the 50 G clock input at the right hand sides. .........................................................19 Figure 21: Concept of interfacing the 50 G I/Os of the 4 DEMUX ICs to the 12 GPPO connectors. ...............20 Figure 22: CPW lines on quartz-substrate, left: designed and right: fabricated. ...........................................21 Figure 23: S-parameter measurements of the fabricated CPW lines on quartz-substrate. ...........................21 Figure 24: 3-D sketch of chip arrangement, optical coupling and output network to GPPO connectors (w/o sidewalls of receiver module) of the planned 400 Gb/s demultiplexing photoreceiver module. ...................22 Figure 25: ESD protection of the pinTWA and DEMUX biasing terminals of the pinTWA-DEMUX module. ..22


List of Tables Table 1: HFSS simulation parameters. .............................................................................................................8 Table 2: Material properties ..........................................................................................................................11 Table 3: Mesh controls ..................................................................................................................................12 Table 4: Measured values ..............................................................................................................................13 Table 5: Typical fiber characteristics .............................................................................................................13 Table 6: Study of MSL and CPW lines on quartz substrates interfacing between ICs and different connector types, espec. to GPPO connectors. ................................................................................................................20

direct 100g connectivity with optoelectronic polymer-inp ... · direct 100g connectivity with...

Documents