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Effective and Efficient Approach for PowerReduction by Using Multi-Bit Flip-Flops

Name :B.DINESH KUMARRoll No : 2451-13-744-011Branch : ME –VLES (II sem)

MVSR ENGINEERING COLLEGE, HYDERABAD

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Presentation Outline

I. INTRODUCTIONII.MULTI BIT FLIP-FLOPCONCEPTIII.NOTATIONSIV.CONSTRAINTSV.ALGORITHMVI.COMPUTATIONAL COMPLEXITYVII.EXPERIMENTAL RESULTSVIII.CONCLUSIONIX.REFERENCES

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Introduction

• As the technology advances the size of the chip decreases and the no.of devices on it increases which leads to high power density.

• Power consumed by clocking has taken a major part of the whole design.

• This can be reduced by using multiple bit flipflops where the no.of clocks required is less.

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MULTIPLE BIT FLIPFLOPS

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TRUTH TABLE OF MULTI BIT FLIP FLOP

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MERGING FLIPFLOPS

Input

Divide chip into subregions

REPLACE filp-flopsin each subregion

Combine subregions andreplace flip-flops

De-replace and replace flip-flopsbelongs to pseudo combination

Output

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PROBLEMS FACED DURING MERGING OF FLIP-FLOP

• Combination of flip flops increases the wire length in the layout.

• Combination of flipflops also changes the density

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CONTINUE

• To avoid wasting time in finding impossible combinations of flip-flops, we first build a combination table before actually merging two flip-flops. For example, if a library only provide a 4 bit flipflop then a combination of 3 flipflops is impossible.

• We partition a chip into several subregions and perform replacement in each subregion to reduce the complexity.

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ALGORITHM

START

IDENTIFY THE MERGABLE FLIP-FLOP

BUILD A COMBINATION TABLE

MERGE FLIP-FLOP

END

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NOTATIONS

1)Let fi denote a flip-flop and bi denote its bit width.2) Let A( fi ) denote the area of fi .3) Let P( fi ) denote all the pins connected to fi .4) Let M(pi , fi ) denote the Manhattan distance between a pin pi and fi, where pi is an I/O pin that connects to fi .5) Let S(pi ) denote the constraint of maximum wirelength for a net that connects to a pin pi of a flip-flop.6) Given a placement region, we divide it into several bins.7)Let RA(Bk) denote the remaining area of the bin Bk thatcan be used to place additional cells.8) Let L denote a cell library which includes differentflip-flop types (i.e., the bit width or area in each type isdifferent).

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CONSTRAINTS

• Timing Constraint for a Net Connecting to a Flip-Flopf j from a Pin pi : To avoid that timing is affected after the replacement, the Manhattan distance between pi and f j cannot be longer than the given constraint S(pi ) defined on the pin pi [i.e., M(pi , f j ) ≤ S(pi )].

• Capacity Constraint for Each Bin Bk : The total area of flip-flops intended to be placed into the bin Bk cannot be larger than the remaining area of the bin Bk

(i.e., A( fi ) ≤RA(Bk)).

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OVERCOMING MECHANISM

To facilitate the identification of mergeable flip-flops, we transform the coordinate system of cells.

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COMBINATION TABLE

Combination Table Tn1 n2 n3 n4 n5

1-bit 4-bit 2-bit 3-bit 4-bitn1 n1 n3

+ + +n1 n3 n3

3 42 1 2 2 2

1 4 1 1 1 1 1 1 1 1 1

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RECOMBINATOIN NEAR SUB REGION BOUNDARIES

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EFFICIENCY

• Efficiency is calculated by the following formulas

PR_Ratio(%) =poweroriginal−powermerged * 100% poweroriginal

WR_Ratio(%) = wire_lengthmerged * 100% wire lengthoriginal

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EXPERIMENTAL ANALYSIS

Power analysis

Power Before After Percentage

Merging Merging Reduction

in power

Proposed Dynam

Counter- -ic 66mW 48mW 27.27%

measure Power

circuit Total

Power 143mW 125mW 12.59%

Power consumption of flipflops

Flip-flop Power Powerconsumption consumptionusing single bit using multi bitflip-flop flip-flop

1 bit flip-flop0.52 0.52




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CONCLUSION

• The proposed algorithm is used to merge the flip-flops for power reduction.

• Power reduction in turn reduces the chip area and the total power consumption of multi bit flip-flop is less when compared to the set of single bit flip-flop.

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References

[1]P. Gronowski, W. J. Bowhill, R. P. Preston, M. K. Gowan, and R. L. Allmon, “High-performance microprocessor design,” IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 676–686, May 1998.[2] W. Hou, D. Liu, and P.-H. Ho, “Automatic register banking for lowpowerclock trees,” in Proc. Quality Electron. Design, San Jose, CA, Mar. 2009, pp. 647–652.[3] D. Duarte, V. Narayanan, and M. J. Irwin, “Impact of technology scalingin the clock power,” in Proc. IEEE VLSI Comput. Soc. Annu. Symp.,Pittsburgh, PA, Apr. 2002, pp. 52–57.[4] H. Kawagachi and T. Sakurai, “A reduced clock-swing flip-flop (RCSFF)for 63% clock power reduction,” in VLSI Circuits Dig. Tech. PapersSymp., Jun. 1997, pp. 97–98.[5] Y. Cheon, P.-H. Ho, A. B. Kahng, S. Reda, and Q. Wang, “Power-awareplacement,” in Proc. Design Autom. Conf., Jun. 2005, pp. 795–800.

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Thank You

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