digitallab ecce 2008

8/20/2019 DigitalLab ECCE 2008

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TABLE OF CONTENTS

Acknowledgments

Introduction

Objectives

The Digital Kit

1. Prototying board

!. Power "uly

#. $%Ds

&. "witches

'. ()"egment Dislay

*. Digital +locks

$aboratory %,ercises

-. Discrete ates

1. $ogic ates

a. /asic $ogic ates

b. $ogic ates Alications

!. Digital 0eets Analog $ab %,ercise

#. ull)Adder 2 ull)"ubtractor

a. +onstruction o3 ull)Adder

b. +onstruction o3 ull)"ubtractor

&. Decoders

a. /asic Decoders b. Decoder Alications

'. 0ultile,er

*. P$D

(. "e4uential +ircuit

5. +ounters

6. "hi3t 7egisters

1-. 0ini)Projects

a. Thunderbird Taillights

b. $am Ping)Pong

c. Other Proosal

11. I+ "ymbols 2 Pin)outs


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ACKNOWLEDGMENTS

The laboratory e,ercises contained within this document have evolved 3rom a set o3

e,ercises that have been taken 3rom the Digital Design "ystem $aboratory 0anual !--'.

8el3ul comments have been made by 0r. 9ose +laro 0onje and Dr. 7osula 7eyes who have

used the e,eriments in their teaching o3 Digital $ogic Design and "witching Theory.

INTRODUCTION

The goal o3 this e,eriment manual is to introduce the 3undamentals o3 digital electronic

comonents :basic gates; decoders; multile,ers; 3li)3los; counters; shi3t registers< in a

manner suitable 3or %ngineering students. /readboard rototying will be er3ormed to

actuali=e digital circuits. 8oe3ully; this manual can serve as a systematic guide to >hands)

on? e,erience with digital electronic concets and devices taught in the lecture course.

OBJECTIVES

The course will rovide the student with a 3irm 3oundation o3 the rinciles o3 digital design

by building a working knowledge o3 digital electronics and its alications.

/y the end o3 the semester; the student shall have ac4uired the basic skill in using the digital

design kit@

● se o3 rototying board.

● se o3 basic gates; decoders and multile,ers.

● se o3 P$Ds

● se o3 3li)3los; counters and shi3t registers.

● se o3 logic robe.


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he Digital Kit

1. Prototyping/BreadboardThe breadboard is used to create a circuit without the need 3or soldering circuit

elements together. The uer and lower halves o3 the breadboard contain *# vertical rowso3 ' interconnected contacts. There are also & long hori=ontal rows o3 connectors :1-

grous o3 ' contacts each< along the uer and lower edges. These long rows o3

connectors are re3erred to as ower bus stris because they will be connected to the

ower sulies to rovide ower connections over the entirety o3 the breadboard. This

breadboard socket is designed to accet integrated circuits; most common wire terminal

comonents; and wire interconnections.


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5. 7SEGMENT DISPLAY

Th e t wo sev en seg me nt dis pl a! s are dr iv en b! 3443 6-7 to7sev en7 seg me nt dis pl a!

de co d er)dr i v e rs . T he sai d d ri v e r has 4 i np u ts c or r es p o nd i n g t o t he b in ar ! c od e o f t he des ir e d

dec im al out pu t on the seve n seg me nt dis pl a! . 8np ut s not co nn ec te d to an! val ue are

c on si d er e d as #f lo at i n g# 89 t hu s ca us i n g t he d is p la ! t o t ur n o ff wh en n ot i n u se.

!. DIGITAL CLOCKS Two f i x ed c lo c s are pr ov i d ed b ! the bo ar d o ne ha vi n g a f re :u en c ! o f 1 00 ; a nd the

ot he r 1 ;. T he fr e: ue n c! o f c l oc 1 /6, < 1 ca n b e c ha ng ed b! pu tt i ng acr os s ca pa ci t or s

i n 6 1 an d = . A ca pa ci t or v al ue of 43 u > w i l l dec re as e t he f re :u en c ! t o ar ou n d 2 ; . T he

f re : uen c! o f c l o c 2 /6,


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Laboratory Exercises

". D#s$%&'& G('&s

This laboratory e,ercise aims to relate logic gates with discrete electronic elements

such as diodes and transistors. /y using a truth table; determine the logic 3unction er3ormed

by the circuits below. Assume that a voltage o3 - to -.5B is a logic $OC and a voltage o3

!.&B to 'B is a logic 8I8. %,lain why you are getting the outut voltage levels 3or each

circuit. Are these the e,ected values 3or the given circuit


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1. LOGIC GA ES

ObjectiveT o f am i l i a r i ; e t he st ud en t s w i t h t he us e o f TT , /trans is t or7 t ra ns i st o r l og i c 9AT' ( an d t he

t ruth tab le.

Logic GatesA logic gate p er f orm s a lo gi c al op er at i on o n on e or m or e lo gi c in pu ts an d pr od u ce s a si ng lel og i c o ut p ut . ( in c e t he o ut p ut i s a ls o a lo gi c7 l ev el v al u e an o ut p u t o f o ne l og i c ga te ca n be

co nn ec te d to the inp ut of one or m or e ot he r lo gi c gates. T he lo gi c nor m al l ! per fo r m ed is

oo l ea n lo gi c an d i s m os t c ommo n l ! f ou nd i n d ig it al ci rc u it s

T he m os t c ommo n l og i c op er at i on s are %$T $& an d A%- .

NOTTh is lo gi c oper at io n out pu ts the co mp l i m e nt of the oper an d. >or exa mp l e %$ T 1 ? 0 and

%$T 0 ? 1 . T he s!m bo l s us ed t o r ep re se nt th e %$T op er at i on are the t il de @B b ef or e the

operan d / a m in us sign @ @ bef or e t he operan d / a pr i me s! mb ol @ @ / afte r t he

ope ra nd o r a bar o ve r the o pe ra nd /

'xamp l e s C

or

or

OR Th is l og i c o pe ra t i o n o ut p ut s 1 i f at l eas t o ne o pe ra n d i s e: ua l t o 1 . > or e xamp l e 1

$ & 0 $& 1 $ & 0 ? 1. T he s! mb ol used to represen t the $ & opera t io n is a p l us sign @ B

between operands / .

'xamp l e C

1

ANDT hi s l og i c o pe ra ti o n ou tp ut s 1 i f a nd on l! i f a ll o pe ra nd s are e :u al to 1 . > or ex am p l e 1 A%-

0 A%- 1 A%- 1 ? 0. T he s!m bo l s us ed to r ep re se nt the A %- op er at i on are t he am pe rs an d @

B or t he d ot p ro d uc t @ ” between operands / .

'xamp l e C

or


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Trt! tablesA tr ut h ta bl e is a t ab le tha t des cr i be s t he beh av i o r of a l og i c gate. 8t l is ts t he v al ue of the

ou tp u t f or ev er ! p os si b le c om b i n at i o n of t he i np ut s. T ab le 1 sh ow s the tr ut h tab le f or a %$T

o pe ra t i on T ab l e 2 sh ows t he t r ut h ta bl e f or a two7 i np u t A%- o pe ra t io n an d t ab le D sh ows t he

t ru t h t ab l e f or a two7 i n pu t $& ope rat i o n .

Table 1. NOT" AND and OR Trt! TablesA NOT )A*

- 1

1 -

A B A AND B

- - -

- 1 -

1 - -

1 1 1

A B A OR B

- - -

- 1 1

1 - 1

1 1 1

Logic #y$bol

a. Bas ic Logic Gate %&erciseThe logic gates that we will use are integrated chis :I+s< that use transistors to er3orm

logical oerations; thus they are called transistor)transistor logic :TT$< I+s. The I+s that you

will be using are 4uad !)inut logic gates@ there are 3our logic gate units in each I+ taking in

two searate inuts each.

%ach grou will be rovided with two o3 the 3ollowing I+sE (&$"--; (&$"-!; (&$"-5;

and (&$"#!. These are the AFD; O7; FAFD :FOT AFD< and FO7 :FOT O7< 4uad gates

:not resectively or not necessarily in that order


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FoteE

1A; 1/ are the inuts and 1G is the outut 3or the 3irst logic gate in the I+@

!A; !/ are the inuts and !G is the outut 3or the second logic gate in the I+@

and so on...

Bcc is the suly voltage o3 the I+.

or TT$; Bcc should be H'B ± ' ;i.e.; &.('B to '.!'B.

FD is the ground in or -B.

Two volts :!B< to 3ive volts :'B< alied to an inut o3 the I+ is considered a high signal

:logic 1


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%,haust all ossible combinations o3 inuts and check the oututs o3 each.

SW" + ,A SW, + ,B ,Y - 74""

- -

- 1

1 -

1 1

/ased on your truth table; the logic 3unction o3 (&-- is JJJJJJJJJJJJJJJJ

SW" + ,A SW, + ,B ,Y - 74"2

- -

- 1

1 -

1 1

/ased on your truth table; the logic 3unction o3 (&-! is JJJJJJJJJJJJJJJJ

SW" + ,A SW, + ,B ,Y - 74"/

- -

- 1

1 -

1 1

/ased on your truth table; the logic 3unction o3 (&-5 is JJJJJJJJJJJJJJJJ

SW" + ,A SW, + ,B ,Y - 7432

- -

- 1

1 -

1 1

/ased on your truth table; the logic 3unction o3 (! is JJJJJJJJJJJJJJJJ


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b. Application1. The truth table below imlements a #)bit majority one circuit i.e. the outut is 1 when

the number o3 1s in the inut is a majority : ! or more 1s


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#. /asic +ombinational +ircuit $ab. %,ercise

AFD)O7)FOT. This laboratory e,ercise re4uires the design o3 a simle combinational

circuits using AFD)O7)FOT gates :i.e. (&,,-5; (&,,#! 2 (&,,-&


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G%-01 3

---- - 1--- 1

---1 - 1--1 1

--1- 1 1-1- 1

--11 - 1-11 1

-1-- - 11-- -

-1-1 - 11-1 -

-11- 1 111- 1

-111 1 1111 1

G%-01 4

---- 1 1--- 1

---1 - 1--1 -

--1- 1 1-1- 1

--11 - 1-11 1

-1-- - 11-- -

-1-1 1 11-1 1

-11- - 111- 1

-111 1 1111 1

G%-01 5

---- 1 1--- 1

---1 - 1--1 -

--1- - 1-1- -

--11 - 1-11 -

-1-- 1 11-- 1

-1-1 1 11-1 1

-11- 1 111- -

-111 1 1111 -


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G%-01 !

---- 1 1--- -

---1 1 1--1 -

--1- 1 1-1- -

--11 1 1-11 1

-1-- - 11-- 1

-1-1 - 11-1 1

-11- - 111- 1

-111 1 1111 1

G%-01 7

---- - 1--- ----1 1 1--1 1

--1- - 1-1- -

--11 - 1-11 -

-1-- 1 11-- -

-1-1 1 11-1 1

-11- 1 111- -

-111 1 1111 1

G%-01 /

---- - 1--- -

---1 1 1--1 1

--1- - 1-1- 1

--11 1 1-11 1

-1-- 1 11-- 1

-1-1 - 11-1 -

-11- 1 111- 1

-111 - 1111 1


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&. FAFD ates. This laboratory e,ercise re4uires the design o3 a simle combinational

circuits using FAFD gates :i.e. (&,,--; (&,,1- or (&,,!-


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s&' C

)(ss#6&8 '- 6%-01s 3 9 7*

---- - 1--- -

---1 1 1--1 -

--1- - 1-1- -

--11 1 1-11 1

-1-- - 11-- 1

-1-1 1 11-1 1

-11- - 111- 1

-111 1 1111 1

s&' B)(ss#6&8 '- 6%-01s 4 9 5*

---- - 1--- 1

---1 - 1--1 1

--1- - 1-1- 1

--11 1 1-11 1

-1-- - 11-- -

-1-1 - 11-1 1

-11- - 111- -

-111 1 1111 1

Paer Design :to be included in the lab reort


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2. D#6#'(: M&&'s A(:-6 L(; E&%$#s&

S&(' B&:' W(%#6 Ss'&


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3. Fulla!!er " #ullsubtractor

Objective'T o fam il i a r i; e the stu de nt s w it h the c on st r uc t i o n and v ar i ou s im pl em e n ta t i o ns of A d de r an d

(ub t r ac t o r c i rc u i t s .

(al)*AdderA !al)*Adder is a comb i n a t i o n a l l og i c c ir c u it t ha t i s ab le t o pe rf o rm t he a d di t i o n o f two bi ts .8 t t a e s two i n pu t s ig n al s E and F adds t hem and out p u t s a sum /( and car r ! /6. Th i s ad7

d it i o n c on si s ts o f f ou r p os si b l e c omb i n a t i o n s o f i np u ts an d o ut p ut s namel ! 0+0?0 0+ 1? 1

1+0? 1 an d 1+ 1? 10 . T he f ir s t t hr ee o pe ra t io n s ha ve a sum wh os e le ng t h is o nl ! 1 b it b ut th e

f ou r t h has a sum t ha t c on si s ts o f two di g it s. T he ca rr ! i s th e h i gh e r s ig ni f i c a n t b it o f t he two

d ig i ts i n t he f ou r t h p os si b l e c omb i n a t i o n .

T he tr ut h ta bl e be low is d er i v e d f rom t hi s des cr i p t i o n.

+NP,T O,TP,T- 0arry #0#$0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

T he o ol e a n ex p re ss i o n f or eac h o ut p u t c an be d er i v e d f rom t he tr ut h ta bl eC

T he t w o im pl em e n ta t i o ns sh ow n bel o w of t he hal f7 ad de r ci rc u it are the sum o f pr od u ct s and

pr o du c t o f sums n ot at i o n ta e n f rom th e t ru th tab le ab ov e.

( um of "r od u ct s "r od u ct of ( um s

%o te t ha t ( i s t he e x c lu s i v e7$& o f E an d F . T he comp l eme n t o f ( i s t he e : ui v a l e nc e /exc lu 7

s ive7%$& o f x and !.


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(um of "rodu c ts "roduc t of (ums

T he ha lf7 ad de r be low is imp l eme n t e d us in g an e x cl u s i v e7$& /E$& an d an A %- ga te.

(. C-s'%0$' ( F0::A88&% C#%$0#'.

A 3ull)adder is a combinational circuit that 3orms the arithmetic sum o3 three inut

bits. It consists o3 three inuts and two oututs. Two o3 the inut variables denoted by , and

y; reresent the two signi3icant bits to be added. The third inut; =; reresents the carry 3rom

the revious lower signi3icant osition. Two oututs are necessary because the arithmetic

sum o3 three binary digits ranges in value 3rom - to #; and binary ! or # needs two digits.

The two oututs are designated by the symbols " 3or sum and + 3or carry. The binary

variable " gives the value o3 the least signi3icant bit o3 the sum. The binary variable + gives

the outut carry. :C>S + ? @ Y @


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"hown below is an MO7 gate I+; (&$"5*.


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;. C-s'%0$'#- - ( F0::S0;'%($'-% C#%$0#'

A 3ull)subtractor is a combinational circuit that er3orms a subtraction between two

bits; taking into consideration that a 1 may have been borrowed by a lower signi3icant stage.

This circuit has three inuts and two oututs. The three inuts; ,; y and =; denote the

minuend; subtrahend and revious borrow; resectively. The two oututs; D and /; reresentthe di33erence and the outut borrow; resectively. :B>D + ? Y


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$. Deco!ers

ObjectiveT o f am i l i a r i ; e t he st ud en t s w i t h t he us e a nd ap pl i c a ti o n o f de co d er s i n d i g it a l c ir c u it s.

DecodersA decoder i s a mu l ti p l e7 i n pu t mu l ti p l e7 o u tp u t l og i c c ir c u it t ha t c on v e rt s c od ed i np u ts i nt oc od ed o ut p u ts wh er e t he i np u t an d o ut p u t c od es ar e d i f f er e n t s uc h as n7t o72 n i na r! 6 od ed

-ec ima l /6- de co d er s. -ec o d e rs ha ve an e na bl e p in wh i c h nee ds t o b e t ur ne d o n f o r th e

de co de r to f un ct i o n ot he r w i se its out p ut s ass um e a s in gl e Gdi sa bl e dG out p ut c od e w or d.

- ec o di n g is nec es sa r! in ap pl i ca t io n s suc h as data m ul t i pl e x i n g 3 s egme n t d is pl a! an d

memo r! add ress de cod i n g .

,e t us cons ide r n7to72n t ! pe b in ar ! de co d er s. T he se de co d er s are c omb i n a t i o n a l c ir c ui t s t ha t

con ver t bi na r ! in f or m at i on fr om #n# nu mb er of coded inp uts to a m ax i m u m nu mb er of 2 n

un i :u e outp ut s. H e sa! a maximum number of 2 n o ut p ut s bec au se i f t he #n# bi t c od ed

inf or m a ti o n has unus ed bit co mb i na t io ns the dec od er w ou l d ha ve less than 2 n ou t p ut s .

Ava i l ab le decoders are the 27to74 decoder /34xx1D I D7to7J decoder /34xx1D J and 47to71

de code r /34xx 154. He can fo rm a D7to7J de code r f r om two 27to74 decode rs /w it h enab le

s igna ls. He can fo rm a 47to71 decode r f rom two D7to7J decode rs /with enab le s igna ls.

'xamp l e C A 27to74 ,i n e -ecoder /w it h o u t an enabl e l i ne


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' xa m pl e of T T , 86s :a< dual !)to)& decoders with enable :(&$"1#6


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+onnect inuts !/; !A; 1; +; / and A to switches sw'; sw&; sw#; sw!; sw1 and sw-

resectively. +onnect the oututs G-; G1; G!; G#; G&; G'; G* and G( to $%D- to $%D(

resectively.

IF IF IF IF IF IF OT OT OT OT OT OT OT OT

G2B G2A G, C B A Y" Y, Y2 Y3 Y4 Y5 Y! Y7M M - M M M

M 1 M M M M

1 M M M M M

- - 1 - - -

- - 1 - - 1

- - 1 - 1 -

- - 1 - 1 1

- - 1 1 - -

- - 1 1 - 1

- - 1 1 1 -

- - 1 1 1 1

;. A11:#$('#-

4'-,! 8&$-8&%. Imlement the 3ollowing truth table using #)to)5 decoders

:(&,,1#5< and a &)inut FAFD gate :(&,,!-


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s&' B )6%-01s 2> ! 9 ,"*

8$;( C-'. 8$;( C-'.

---- - 1--- -

---1 1 1--1 -

--1- - 1-1- 1

--11 - 1-11 -

-1-- - 11-- -

-1-1 - 11-1 -

-11- 1 111- -

-111 - 1111 1

s&' C )6%-01s 3 9 7*

8$;( C-'. 8$;( C-'.

---- 1 1--- 1

---1 - 1--1 -

--1- - 1-1- ---11 - 1-11 -

-1-- - 11-- 1

-1-1 1 11-1 -

-11- - 111- -

-111 - 1111 -

s&' D )6%-01s 4 9 /*

8$;( C-'. 8$;( C-'.

---- - 1--- -

---1 - 1--1 -

--1- 1 1-1- -

--11 - 1-11 -

-1-- - 11-- 1

-1-1 - 11-1 -

-11- 1 111- -

-111 - 1111 1

8intE +onstruct a &)to)1* decoder with two #)to)5 decoders :(&$"1#5


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%. &ulti'lexers

A digital multile,er or mu, is a device that er3orms multile,ing@ it selects one o3 many

digital inut signals and oututs that into a single line.

%,amle o3 !)to)1 0ultile,er :symbol shown above< without an enable signal.

%,amle o3 TT$ I+sE :a< dual &)to)1 multile,er with enable :(&$"1'#< and

:b< 5)to)1 multile,er with enable line :(&$"1'1


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A11:#$('#-

T(#: L#6='s. Gou are to con3igure two multile,ers :(&,,1'1 or e4uivalent< into a tail light

system. It consists o3 3our inut variables and two outut variables. The 3our inut variables

are describe as 3ollowsE :1< blinker and :#< selectors. The blinker inut is connected to the

+$O+K outut o3 the digital kit. se an aroriate 3re4uency setting :one where blinkingo3 $%Ds can be observed< 3or the +$O+K outut. The blinker is used to make the oututs

turn on and o33 :$%Ds blinkdonNt care? i.e. may take the values o3 - or 1.

FoteE or better outut dislay; connect two $%Ds er outut i.e. two $%Ds 3or le3t signal

and two $%Ds 3or right signal.


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2. PLD

Ce will be using a PA$PA$+%A$1*B5A :P$D with 1* rogrammable ins; 5 o3

which are inuts and the other 5 as inutoutut


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sing PA$PA$+%A$1*B5A :say saved in 3ile e,amle.ld<

s-: ,

Q A$1*B5A inE :,;y;=


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e,amle.lst )) contains the 3ollowing

original 3ile

the sum o3 roduct 3orm o3 the e4uation or truth table

in assignments W

3use 3ile :9%D%+ 3ormat<

e,amle.jed )) contains the 3use 3ile in 9%D%+ 3ormat that will be the inut 3ile

o3 the P$D rogrammer

e,amle.vec )) the vector 3ile containing the check vectors

I3 there is an error the .lst 3ile will tell you where the error occurred.

W The in assignment by de3ault is as 3ollows

in 1 is reserved 3or the clock ulse in !)6 3or the inuts resectively

in 1- is ground :gnd<

in 11 is 3or 3li)3lo enable :not used at the moment<

in 16)1! 3or oututs resectively

in !- is 3or Bcc :H' B<

A'&% 6&&%('#6 '=& .&8 #:&> %0 '=& PLD 1%-6%(


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T!e Lab. %&ercise

1. B#(%'-s&&s&6


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(. FLI)FLO)S a*!

SE+,E- IAL CIC,I

ObjectiveT o fam i li a r i ;e the stu de nt s w i th the co ns tr u ct i o n and us e o f di f fe re n t t! pe s of f li p7 f lo ps i n

d ig i t a l c i rc u i t s .

3lip*3lopsA )lip*)lop ma i n ta i n s a b in ar ! st at e i nd e f in i t e l ! /as l on g as t he c ir c u it i s p ower e d u n ti l i tre ce i v es an i n p ut si gn al t o sw i tc h st at es. T he r e ar e v ar i o us t !p es o f f li p f lo p s t ha t d if f e r i n t h e

n umb e r o f i np u ts t he ! p os se ss an d h ow th e i n p ut s a ff ec t t he b in ar ! sta te.

Basic 3lip*3lop/#R Latc!Th e basic )lip*)lop o r t he #R latc! has two inpu ts the se t/( and rese t/&. The schemat ic fo r

a bas ic f li p7 f lo p is s ho w n bel o w. A %$& gat e o ut pu ts a lo gi c l ow whe n t he re is at l eas t o nel og i c h ig h i np u t. 8 t o nl ! o ut p u ts l og i c h ig h wh en al l i n p ut s ar e ;e ro .

Hhen l og i c h ig h i s app l i e d t o t h e set/( in pu t and a l og i c l ow i s f ed t o t h e reset/& inpu t t he

bo tt o m %$& gate ou tp u ts a lo gi c l ow due to th e l og ic hi gh of the ( i np ut rega rd l es s o f w h a t

is t he va lu e o f t he ot he r i np ut . T he l og ic l ow ou tp ut of the b ot to m %$& gat e i s t he n f ed t o t he

up pe r %$& gate toget he r w it h the log ic lo w of the & in pu t. Th e res ul ti ng out pu t fr om the(? 1 &?0 i np ut c om b i n at i o n is K ? 1 K L?0. T he op po si t e ha pp en s w he n &? 1 and (?0 th e

res ul t in g out p ut is K ?0 an d K L? 1 . Hh e n K? 1 and K L?0 it is sai d to be i n t he set stat e a nd

when K?0 and K L?1 i t i s in t he c le ar s ta te.

%A% - ga te s c an als o be u se d to c on st r uc t a bas ic f li p7 f l op . 8 ts d if f e re n c e i s th at t o ac ti v a te

t he set mo d e a 0 mus t be f e d t o t he i np u t ( wh i l e i np u t ti n g a 1 t o t h e i np u t & o p po s it e o f t h e

%$& im pl em e n ta t i o n.

%&ercise>or the %$& i mp le m e nt at i on of the bas ic f l ip7 fl op do the co mb i na t io n of in pu ts ( a nd &

be low i n o r de r an d r ec o rd t he o ut p u t i nt o t he t ru t h ta bl e. 6on n e ct i np u ts ( a nd & t o sw it c h es

sw 1 and sw0 respec ti ve l! . 6 on ne ct out pu ts K and KL to , '- 1 and , '- 0 respec ti ve l! .

-et erm i n e wh i c h c omb i n a t i o n o f i n pu t s sh ou l d be a v oi d e d be ca us e o f i ts o u tp u ts .


35/47

( & K KL

1 0 1 0

0 0 1 0

0 1 0 1

0 0 0 1

1 1 0 0

R# 3lip*3lopThe R# )lip*)lop is a m od i f i e d bas ic f li p7 f lo p w he re an add it i o na l i np ut co nt r ol s w he n thes ta te s o f t he f l i p7 f l o p change . The bas i c f l i p7 f l o p changes st at es as soon as t h e i n p u ts change

wh i l e an &( f li p7 f l op c ha ng es sta tes at t he ne xt c lo c p ul se. T he t ru t h ta bl e f or t he c ha ng i n g

stat e o f t he K o ut p ut o f t he &( f li p7 f lo p is s hown be low .

4 # R 40t510 0 0 0

0 0 1 0

0 1 0 1

0 1 1 8nde te rm i n a t e

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 8nde te rm i n a t e

Hhe re K i s t he p re sen t st at e and K/t+1 is t h e ne x t st at e o f t he out p u t . %o t e t ha t whene ve r (

and & a re bo t h h i gh t he nex t s ta te i s i n d et e rm i n a t e because i t p la ces ;ero es i nt o t he i n pu t s o f

the bas ic f li p7 f lo p us ed an d ma es o ut p ut s K an d K L b ot h hi gh w h ic h is av oi d ed bec au se

b ot h mus t be comp l eme n t s o f eac h ot he r.

%&ercise6 on st ru ct an & ( >l ip7 f l op b! add in g t wo m or e % A%- gates to t he % A %- i mp le m e nt at i on of

t he bas ic f li p7 f l op c ir c u it . 6o nn e c t t he t hr ee i np u t el eme nt s 6"/c lo c p ul se (/set an d

&/res et t o t he p ul se r sw 1 an d sw0 o f t he d ig i t al i t res pe ct i v e l ! . 6o nn e c t o ut p u ts K an d K L

to , '- 1 an d , '-0 res pe ct i v el ! . M a e the pu ls er Ls spee d lo w en ou g h t o o bs er v e the c lo c

p ul se. T he momen t th e c lo c p ul se go es hi g h t he l og i c h ig h o f e it he r th e ( o r & i np u t s ho ul d

be f ed i nt o th e i n pu t s o f th e b as ic f li p7 f lo p. Ve ri f ! t ha t t he c lo c c on t ro l s t he stat e c h an g e b !

obse r v i n g when the ou t p u t s change s ta te .

D 3lip*3lop

The D )lip*)lop ad dr es ses th e p ro bl e m of the &( f li p7 f lo p ab ou t bo th in pu ts be in g 1 at thesame ti m e. T he so le i np ut - is c on ne ct e d to the ( i np ut w h il e its in ve rt ed v al ue is fe d i nt o

t he res et i np u t o f t he &( f li p7 f l op t o e ns ur e t ha t o nl ! o ne i np u t i s hi g h an d th e o th er l o w at a

t im e. 8 f - is 1 t he ne x t st at e o f t he o ut p ut K g oe s t o 1 an d wh e n - i s 0 th e n ex t stat e o f t he

o ut p ut K be come s 0.


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%&ercise6 on st ru ct the - fl ip7 f l op f ro m the % A%- i mp l em e nt at i on of the & ( fl ip7 f l op. 6 om p l et e the

tr ut h ta bl e o f t he - f li p7 f l op be low .

4 D 40t510 0 0

0 1 1

1 0 0

1 1 1

67 3lip*3lopT he N< f li p7 f lo p is a no th er m od i f i c at i o n of t he &( f li p7 f lo p w h ic h has i ts o w n wa! of dea li n g

w i t h t he &( f li p7 f l op L s u nd es i r ab l e i np u t c omb i n a t i o n /whe n (? 1 an d &?1. T he N< f li p7 f l op

has 2 in pu ts N an d < eac h A %-e d w i th the c lo c p ul se and its co rr es po n d i n g %$& out p ut .

T he sc hema t ic f or t he N< f li p7 f lo p is s hown be low .

%&ercise6on st r uc t t he N < f li p7 f lo p ci rc u it . $ bs er v e w ha t hap pe n w he n t he i np ut s are N? 1 an d


37/47

T 3lip*3lopT he T f li p7 f lo p is a mo di f i c a t io n o f the N < f li p7 f lo p bu t i t has on l! o ne in pu t in st ea d o f t w o

i np u ts t ha t t he N< f li p7 f l op has. T h e ne xt st at e i s d ep en d e nt o n t he v al u e o f t he i np u t T. Hhe n

T?0 t he ne xt st at e o u tp u t i s re ta in e d b ut wh en T? 1 t he ne xt sta te o ut p u t i s th e o p po s it e o f

the presen t sta te.

K T K/t+1

0 0 0

0 1 1

1 0 1

1 1 0

%&ercise- ra w and cons tr uc t the sche ma ti c for the T fl ip7 f l op based on the in fo r m at i o n ! ou hav e

ga th er e d f rom t he N< f li p7 f l op an d t he d es cr i p t i o n o f t he T f li p7 f lo p. Ve r i f ! ! ou r c ir c ui t us in g

t he T f l i p7 f l o p L s t ru t h ta bl e.


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#%4,%NT +AL +R,+T %-%R +#%#

"et ,5A. Design a counter using D 3li)3los. The circuit counts -)1)#)()1')()#)1)-)1)#)etc.

a. give the state diagram 2 the transition table

b. the e,ressions 3or the D inutsc. the e,ression 3or the outut i3 any

d. the logic diagram

e. do the actual circuit imlementation

))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))

"et 2!,"+. Design a counter using D 3li)3los. The circuit counts -)5)1!)1&)1')1&)1!)5)-)5)1!)

etc.

a. give the state diagram 2 the transition table b. the e,ressions 3or the D inuts

c. the e,ression 3or the outut i3 any



))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))

"et 37,,

%. Design a counter using D 3li)3los. The circuit counts -)1)#)()1')-)1)#)()1')-)1)etc.

a. give the state diagram 2 the transition table

b. the e,ressions 3or the D inuts




))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))

"et 4/,2. Design a counter using D 3li)3los. The circuit counts -)5)1!)1&)1')-)5)1!)1&)1')-)5)

etc.a. give the state diagram 2 the transition table

b. the e,ressions 3or the D inuts




GI; The D)3li)3lo I+ is (&$"(&; shown below.


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PRE CLR CLK D

- 1 M M 1 -1 - M M - 1

- - M M 1 1

1 1 PO" - - 1

1 1 PO" 1 1 -

1 1 - M Z- Z-

$%%FDE

- L logic low

1 L logic high

M L dont care

PO" L ositive edge o3 clock; low to high transition. Z-; Z-; means revious values o3 Z i.e. retain old value :8O$D


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/. CO,- ES

+onstruct a digital circuit that counts 3rom -- to 66 using two /+D counters :! , (&$"16-<

and necessary gates. se the ()segment dislay o3 the digital design kit to show the counter

outut. se the digital kit variable clock 3or the clock inut o3 the counter. se an

aroriate 3re4uency. Gou can connect +T%F inut to sw- to make it an u or downcounter.

CTEN DU CLK LOAD A B C D A B C D RCO MA?

MIN

- M M - a b c d a b c d W WW

- 1 PO" 1 M M M M +ountdown

+ountdown

+ountdown

+ountdown

W WW

- - PO" 1 M M M M +ount

u

+ount

u

+ount

u

+ount

u

W WW

1 M M M M M M M ZA- Z/- Z+- ZD- W WW

$%%FDE

- L logic low

1 L logic high

M L dont care

PO" L ositive edge o3 clock; low to high transition.

ZA-; Z/-; Z+-; ZD- means revious values o3 Z i.e. retain old value

+ount down means i3 revious count is (; new count is *

+ount u means i3 revious count is (; new count is 5

W L during the P count 0AM0IF goes 8I8 at count 6; during the DOCF count

0AM0IF goes 8I8 at count -.

WW L during the P count 7+O goes $OC at count 6; during the DOCF count 7+O

goes $OC at count -.


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0. SIF EGIS E

+onstruct a digital circuit that counts -;1;#;(;1';#1;*#;1!(;!'' then back to =ero using two

universal shi3t registers :! , (&$"16&< and necessary gates. se the 5 $%Ds to dislay

outut. se the digital kit variable clock 3or the clock inut. se an aroriate 3re4uency.

0OD% IFPT" OT) PT"

CLR S, S" CLK SL SR A B C D A B C D

- M M M M M M M M M - - - -

1 M M - M M M M M M ZA- Z/- Z+- ZD-

1 1 1 PO" M M a b c d a b c d

1 - 1 PO" M 1 M M M M 1 Zan Zbn Z+n

1 - 1 PO" M - M M M M - Zan Zbn Z+n

1 1 - PO" 1 M M M M M Zbn Zcn Zdn 1

1 1 - PO" - M M M M M Z/n Z+n Zdn -

1 - - M M M M M M M ZA- Z/- Z+- ZD-

$%%FDE

- L logic low

1 L logic high

M L dont care

PO" L ositive edge o3 clock; low to high transition.

ZA-; Z/-; Z+-; ZD- means revious values o3 Z i.e. retain old value


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,". M##PROJECTS *

P-ss#;:& P%-&$'s

(. TBIRD TAILIGHTS

The design o3 a circuit that emulates the oeration o3 the taillights o3 a Thunderbird is

carried out in this roject.

L(;. E&%$#s&

Gou are to design and build a circuit that controls the eight taillights on a

Thunderbird. se eight $%Ds to simulate the eight taillights :3our on each side o3 the car


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;. LAMP PING PONG

The design o3 the Ping)Pong machine 3or two human layers is carried out in this

roject. The machine is an amusing alication o3 shi3t registers as well as an e,osure to

control logic.

Design and construct a circuit that allows two eole to lay Ping)Pong using eight

indicator lams in a row to dislay the moving ball and using two ush button :or toggle

switches< 3or addles.

se two cascaded &)bit shi3t registers containing a single turned on $%D to reresent

the ball. se one ush button :toggle switch< 3or the right)hand user; one 3or the le3t)hand

user. The ball should be moved by a clock source that causes a shi3t once every 4uarter

second or so. Chen the ball is moving to the right; the right)hand layer must deress his

ush button :toggle switch< at the time the ball is in its rightmost osition. :The circuit

should be sensitive only to the leading edge o3 the ush button signal or toggle switch


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11. IC Sy2bol " )i*Outs


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digitallab ecce 2008

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