digital voltage restorer

7/28/2019 Digital voltage restorer

1/14

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010 1975

Implementation and Performance Evaluationof a Fast Dynamic Control Scheme for

Capacitor-Supported Interline DVRCarl Ngai-Man Ho, Member, IEEE, and Henry Shu-Hung Chung, Senior Member, IEEE

AbstractThe implementation of a fast dynamic control schemefor capacitor-supported interline dynamic voltage restorer (DVR)is presented in this paper. The power stage of the DVR consistsof three inverters sharing the same dc link via a capacitor bank.Each inverter has an individual inner control loop for generatingthe gate signals for the switches. The inner loop is formed by aboundary controller with second-order switching surface, whichcan make the load voltage ideally revert to the steady state in twoswitching actions after supply voltage sags, and also gives outputof low harmonic distortion. The load-voltage phase reference is

commonto allthree innerloopsand is generated by anouter controlloop forregulating the dc-link capacitorvoltage. Suchstructure canmake the unsagged phase(s) and the dc-link capacitor to restorethe sagged phase(s). Based on the steady-state and small-signalcharacteristics of the control loops, a set of design procedures willbe provided. A 1.5-kVA, 220-V, 50-Hz prototype has been built andtested. The dynamic behaviors of the prototype under differentsagged and swelled conditions and depths will be investigated. Thequality of the load voltage under unbalanced and distorted phasevoltages, and nonlinear inductive loads will be studied.

Index TermsBoundary control, dynamic voltage restoration(DVR), inverters, power quality, voltage sag.

I. INTRODUCTION

ELECTRONIC systems operate properly as long as the sup-

ply voltage stays within a consistent range. There are sev-

eral types of voltage fluctuations that can cause the systems to

malfunction, including surges and spikes, sags, harmonic dis-

tortions, and momentary disruptions. Among them, voltage sag

is the major power-quality problem [1]. It is an unavoidable

brief reduction in the voltage from momentary disturbances,

such as lightning strikes and wild animals, on the power system.

Although most of them last for less than half a second, this is

often long enough for many types of loads to drop out. Typical

Manuscript received February 4, 2010. Date of current version June 25,2010. This work was supported by a grant from the Research Grants Councilof the Hong Kong Special Administrative Region, China, under Project CityU112407. This paper was presented in part at the Applied Power ElectronicsConference andExposition 2007, Anaheim,CA, Feb. 25Mar.1. Recommendedfor publication by Associate Editor J. HR Enslin.

C. N.-M. Ho is with ABB Corporate Research, Ltd., 5405 Baden-Dattwil,Switzerland (e-mail: [email protected]).

H. S.-H. Chung is with the Centre for Power Electronics, City University ofHong Kong, Kowloon, Hong Kong (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2010.2044587

examples include variable speed drives, motor starter contac-

tors, control relays, and programmable logic controllers. Such

an unplanned stoppage can cause the load to take a long time to

restart and can lead to high cost of lost production [2].

Dynamic voltage restorer (DVR) is presently one of the most

cost-effective and thorough solutions to mitigate voltage sags

by establishing proper quality voltage level for utility cus-

tomers [3]. Its function is to inject a voltage in series with the

supply and compensate for the difference between the nominaland sagged supply voltage. The injected voltage is typically pro-

vided by an inverter, which is powered by a dc source [4][7],

such as batteries, flywheels, externally powered rectifiers, and

capacitors.

Voltage restoration involves determining the amount of en-

ergy and the magnitude of the voltage injected by the DVR.

Conventional voltage-restoration technique is based on inject-

ing a voltage being in-phase with the supply voltage [7][10].

The injected voltage magnitude will be the minimum, but the

energy injected by the DVR is nonminimal.

In order to minimize the required capacity of the dc source,

a minimum energy injection (MEI) concept is proposed in

[10][13]. It is based on maximizing the active power deliv-ered by the supply mains and the reactive power handled by the

DVR during the sag. Determination of the injected-voltage mag-

nitude is based on a real-time iterative method to minimize the

active power injection by the DVR. This can then enhance the

ride-through capability. However, the operation of each phase

is individually controlled. There is no energy interaction be-

tween the unsagged phase(s) and the sagged phase(s), in order

to enhance the voltage restoration [14], [15]. Moreover, as the

computation method is purely based on sinusoidal waveforms,

the implementation is complicated in distribution network with

nonlinear load. A sliding window over one line cycle of the fun-

damental frequency is proposed in [13] to determine the activeand reactive power at the fundamental frequency. The lengthy

computation time of the injected voltage phasor will cause out-

put distortion after a voltage sag.

Instead of using an external energy storage device, the meth-

ods in [16] and [17] take the active power for the inverter from

the transmission system via a shunt-connected rectifier. The se-

ries inverter by its self has the capability to provide real-series

compensation to the line.

The rectifier-based source requires a separate service supply,

while the battery-based source requires regular maintenance and

is not environment friendly. A theoretical study of the capacitor-

supported DVR for unbalanced and distorted loads is recently

0885-8993/$26.00 2010 IEEE


2/14

1976 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010

Fig. 1. Structure of the proposed interline DVR and its connection to theutility.

proposed in [18]. No external source is required in the DVR.

The required phase and magnitude of the inverter load-voltage

phasor are derived by considering the energy balance between

the supply and the load, but the advantage is offset by the lengthy

digital transformation and inversion of symmetrical components

and calculation of the power consumption. The waveshape of

the load voltage will be distorted and will take a relatively long

settling time. As the supply voltage is assumed to be sinusoidal

in the calculation, the load voltage will be affected and distorted

with nonsinusoidal supply voltage and load current [18].A single-phase capacitor-supported DVR is proposed in [19].

The load voltage can ideally be reverted to the steady state in two

switching actions after voltage sags. By extending the concept,

an analog-based three-phase capacitor-supported interline DVR

is presented. It features the following operational characteristics.

1) By extending the fast transient control scheme proposed

in [19][21], the load voltage can ideally be restored in

two switching actions after a voltage sag. This can assure

near-seamless load voltage and power.

2) The load voltage balance and quality can be maintained,

even if the supply is unbalanced and/or has harmonic dis-

tortion, and the load is nonlinear and/or unbalanced.

3) As the three inverters share the same dc link and the con-

troller acts on the three inverters together, the unsagged

phase(s) will help restore the sagged phase(s) during the

voltage sag.

A 1.5-kVA, 220-V, 50-Hz prototype has been built and tested.

The steady-state and dynamic behaviors of the prototype will

be provided.

II. PRINCIPLES OF OPERATION

Fig. 1 shows the circuit schematic of the DVR with three-

phase transmission system. It consists of inverters, output LC

filters, and injection transformers. The dc side is connected to

a capacitor bank, formed by two capacitors. Each capacitor

has the value of Cdc . The inverter shown in Fig. 1 is a half-bridge configuration. However, the operation is similar in the

full-bridge configuration. The DVR is operated as a controllable

voltage source vd, n , where n represents either phase a, b, or c. Itis connected between the supply and the load. The relationship

among the supply voltage vs, n , the load voltage vo, n , and vd, nis

vd, n (t) = vs, n (t) vo, n (t). (1)

Fig. 2 shows the phasor diagrams of vs, n , vo, n , vd, n , andthe load current io, n in voltage sag and unbalanced conditions.Fig. 3 shows the control block diagram of proposed control

scheme. The control scheme consists of two main loops. The

first control loop, namely inner loop, is formed in each phase.

It is used to generate the gate signals for the switches in the

inverter, so that vd, n will follow the DVR output reference vd, n .

This loop has fast dynamic response to external disturbances. Its

operating principle is based on extending the boundary controltechnique with second-order switching surface in [19][21].

The second loop, namely outer loop, is used to generate vd, n .Based on (1)

vd, n (t) = vs, n (t) vo, n (t) (2)where vo, n is the load-voltage reference and is generated by thephase-lock loop (PLL).

The outer loop is used to regulate the dc-link voltage by

adjusting the phase of the inverter load voltage with respect to

the load current. Its bandwidth is set much lower than the line

frequency. The purpose is to attenuate the undesirable signals,

which are due to the ac component on the dc-link voltage andthe load current, getting into the loop. Since the inner and outer

loops have different dynamic behaviors, the controller will react

differently in the voltage sags of short and long durations.

If the duration of the voltage sag is short [22][25], typi-

cally less than 0.5 s, the inner loop will react immediately and

maintain the waveshape of the load voltage. The outer loop is

relatively inert during the period. The sagged phase(s) will be

supported purely by the capacitor bank. The capacitor voltage

will decrease. After the voltage sag, the outer loop will start

reacting to the decrease in the capacitor voltage. The capacitor

will be charged up from the supply by adjusting the phase angle

of the inverter output.

If the duration of the voltage sag is long, the inner loop willkeep the waveshape of the load voltage and the outer loop will

regulate the dc-link voltage. Thus, the sagged phase(s) will be

supported by the dc link, while electric energy will also be

extracted from the unsagged phase(s) through the dc link.

In the steady-state operation, as the frequency response of the

inner loop is very fast, the waveshape of the load voltage can

be kept sinusoidal, even if there are harmonic distortions in the

supply voltage and the load current. Moreover, with the interline

energy flow in the outer-loop control, the output quality can be

maintained, even if there is an unbalanced supply voltage.

At any time, the amplitude of vo, n is fixed because the load

voltage is regulated at the nominal value. vo, n has the same


3/14

HO AND CHUNG: IMPLEMENTATION AND PERFORMANCE EVALUATION OF A FAST DYNAMIC CONTROL SCHEME 1977

Fig. 2. Steady-state vector diagrams with different sagged conditions.(a) vs, a is changed from 220 to 120 Vrm s . (b) Unbalanced three-phase voltageswith vs, a = 210 Vrm s , vs, b = 190 Vrm s , and vs, c = 240 Vrm s .

frequency as vs, n , and the phase angle between vo, n andvs, n is controlled by the signal v shown in Fig. 3. The supplyvoltages can be expressed as follows:

vs, a (t) = Vsm,a cos t (3a)

vs, b (t) = Vsm,b cos(t 120) (3b)

vs, c (t) = Vsm,c cos(t + 120) (3c)

Fig. 3. Block diagram of the proposed controller.

where Vsm , a , Vsm , b , and Vsm,c are the peak values of the supplyvoltages of the phases a, b, and c, respectively, and is theangular line frequency.

III. REVIEW OF INNER LOOP

The inner-loop control strategy is by using boundary control

with second-order switching surface. The control concept has

been well documented in [19]. A brief review will be given in

this section.

In one leg of the three-phase half-bridge inverter, which is

shown in Fig. 1, as S1 ,n and S2,n are operated in antiphase andthe outputinductor current is continuous, twopossible switching

modes are derived, and their state-space equations are shown as

follows.When S1,n is OFF and S2,n is ON

xn =

0 1/L1/C 1/RL ,n C

xn +

1/2L 00 1/RL ,n C

un

(4a)

vd, n = [ 0 1 ]xn . (4b)

When S1,n is ON and S2,n is OFF

xn =

0 1/L1/C 1/RL ,n C

xn +

1/2L 00 1/RL ,n C

un

(5a)

vd, n = [ 0 1 ]xn (5b)

where xn = [iL, n vC ,n ]T, un = [vdc vs, n ]

T ,and RL ,n is thefictitious resistance showing the ratio between the load voltage

and load current.

Fig. 4(a) and (b) shows the equivalent circuits of the two

modes corresponding to (4) and (5). By solving (4) and (5)

with different initial values, families of state-plane trajectories

shown in Fig. 5 can be derived. The solid lines are named

as the positive trajectories, while the dotted lines are named

as the negative trajectories. The positive trajectories show the

trajectories of the state variables when S1,n is ON and S2,n is


4/14


Fig. 4. Equivalent circuits of one phase in the inverter system. (a) S1 ,n is OFFand S2 ,n is ON. (b) S1 ,n is ON and S2 ,n is OFF.

Fig. 5. State-plane trajectories of the inverter.

OFF. The negative trajectories show the trajectories of the state

variables when S1,n is OFF and S2,n is ON.

As discussed in [20] and [21], the tangential component ofthe state-trajectory velocity on the switching surface determines

the rate at which successor points approach or recede from

the operating point in the boundary control of the switches.

An ideal switching surface i that gives fast dynamics shouldfollow the only trajectory passing through the operating point

[31][33]. Although i can ideally go to the steady state intwo switching actions during a disturbance, its shape is load-

dependent and requires sophisticated computation to determine

the only positive and negative trajectories that pass through the

operating point.

A second-order switching surface 2 , which is close to i

around the operating point, is derived. The concept is based

on estimating the state trajectory after a hypothesized switch-

ing action. As the switching frequency of the switches is much

higher than the signal frequency, the load current io is relativelyconstant over a switching cycle. The gate signals to the switches

are determined by the following criteria. For the sake of sim-

plicity and without loss of generality, vc, n and vd, n in Fig. 1 areassumed to be equal [19].

A. Criteria for Switching S1 ,n OFF andS2,n ON

S1,n and S2,n are originally ON and OFF, respectively. S1,nand S2,n are going to switch OFF and ON, respectively. Thus,according to [19], the criteria for switching S1,n OFF and S2,nON are as follows:

vd, n (t1 ) vd,n,m ax L2C

1

(vdc (t1 )/2) + vd, n (t1 )i2C ,n (t1 )

(6)

and

iC ,n (t1 ) 0. (7)B. Criteria for Switching S1 ,n ON andS2,n OFF

S1,n and S2,n are originally OFF and ON, respectively. S1,nand S2,n are going to switch ON and OFF, respectively. Thus,according to [19], the criteria for switching S1,n ON and S2,nOFF are as follows:

vd, n (t3 ) vd,n,m in + L2C

1

(vdc (t3 )/2) vd, n (t3 ) i2C ,n (t3 )

(8)

and

iC ,n (t3 ) 0. (9)Based on (6)(9) and vd,n,mi n = vd,n,m ax = v

d, n , the general

form of2 is defined as follows:

2 [iL ,n (t), vd, n (t)] =1

k

vd, n (t) vd, n (t)

vdc (t)

2+ sgn[iC, n (t)]vd, n (t)

+ sgn[iC ,n (t)]i2C ,n (t) (10)

where k = L/2C.Fig. 5 shows the load line and the second-order switch-

ing surface (2127 V ) when the required output voltage of theDVR is 127 V. Fig. 6 shows the simulated state-plane trajec-tory of the DVR for compensating vs, n changing from 220 to130 V. The states of the first and the second switching actions are

labeled. The switching surface described in (10) is implemented

with analog circuitry.

IV. CHARACTERISTICS OF OUTER LOOP

A. Steady-State Characteristics

The function of the outer loop is to regulate vdc at the refer-ence value ofVdc . By applying the conservation of energy [26],

the DVR will ideally have zero-average real power flow at the


5/14


Fig. 6. Simulated state trajectory of the DVR for vs, n changing from 220 to130 V.

steady state. Thus

Ps, a + Ps, b + Ps, c = Po, a + Po, b + Po, c (11)

Pa + Pb + Pc = 0 (12)

Ps, n = vs, n io, n cos(n ) (13)Po, n = vo, n io, n cos n (14)

Pn = vd, n io, n cos n (15)

where Ps, n , Po, n , and Pn are the input, output powers, andpower transferred of the each phase, respectively, io, n is the

load current of each phase, n is the phase angle between vo, nand io, n , is the phase angle between vs, n and vo, n , and n isthe phase angle between vd, n and io, n .

Under supply-voltage interruption, the outer loop will adjust

the value of . The DVR will generate the required magnitudeand phase of vd, n in each phase individually. The DVR willthen absorb (deliver) electric energy from (to) the dc link. As

the adjustment of is common to the three phases, the saggedphase(s) will be supported by the capacitor bank and the un-

sagged phase(s). The corresponding equations of vo, n are asfollows:

vo, a (t) = Vo m , a cos(t

) (16a)

vo, b (t) = Vo m , b cos(t 120 ) (16b)vo, c (t) = Vo m , c cos(t + 120

) (16c)where Vo m , n is the peak load voltage of phase n.

Fig. 2 shows the steady-state phasor diagrams with one-phase

sagged and three-phase voltage balancing, respectively. The pa-

rameters used are based on Tables IIII.

In Fig. 2(a), vs, a is reduced to 120 V, while the other phasesare at the nominal value of 220 V. By increasing the value of,vd, a is established by the DVR and vo, a can be kept at 220 V.Thus, part of the energy supplied to phase-a load is supported

by phases b and c.

TABLE ISPECIFICATIONS OF THE DVR

TABLE IIPARAMETERS OF THE PLL AND TRANSDUCER GAINS

TABLE IIICOMPONENT VALUES OF THE DVR

In Fig. 2(b), all three phases are unbalanced, where vs, a =210 V, vs, b = 190 V, and vs, c = 240 V. Again, by adjusting the

value of, vo, a , vo, b , and vo, c are regulated at 220 V.For the phase transformation between and n

n = ( n n ) (17)where n is the phase difference between vs, n and vd, n .

Based on Fig. 2(a) and byusing (15) and (17), it can be shown

that the steady-state power-transfer equation can be expressed

as follows:

Pn = io, n

v2o, n + v

2s, n 2vo, n vs, n cos

cos

n +cos1

vs, nvo, n cos

v2o, n +v2s, n2vo, n vs, n cos

.

(18)

Detailed derivation of (18) is given in the Appendix.

The values of vs, n , vo, n , io, n , and n are different in eachphase. Thus, the power flow of each phase inverter is different.

is controlled by the outer loop in order to achieve powerequilibrium in the system, and thus, satisfy (11) and (12).

B. Small Signal Modeling

Fig. 7 shows the small-signal model of the outer loop. It

consists of the transfer characteristics of the inner loop, inverter,


6/14


Fig. 7. Small-signal model of the outer loop.

PLL, and power-flow controller. As the inner loop has much

faster dynamic response than the outer loop, the small-signal

transfer function of the inner loop is unity. The transfer function

of the inverter describes the small-signal behaviors between and vdc . The functional blocks of power stage and controller arederived as follows.

1) Relationship Between vdc andpdc : The small-signal dc-link voltage to dc-power-transfer function Tp (s) is as follows:

Tp (s) =vdc (s)

pdc (s)=

2

sCdc Vdc(19)

where Vdc is the steady-state values ofvdc .2) Relationship Between Power Flow and the Phase of vd

With Respect to io, n in Each Phase: The small-signal DVR-phase-to-power transfer function Tr,n (s) equals

Tr,n (s) = pn (s)

n (s)= Vd, n io, n (20)

where Vd is the steady-state values ofvd .3) Phase Transformation Between and in Each Phase:

The transfer function Tpt ,n (s) representing the transformationbetween and is

Tpt ,n (s) =n (s)

(s)=

Vs, nVd, n

Vs, n Vo, n cos BV2o, n + V

2s, n2Vo, n Vs, n cos B

(21)

where Vs , Vo , and B are the steady-state values of vs , vo , and

, respectively.4) Phase Transformation Between and vdc in Inverter:

The transfer function Tinv (s) of the inverter is as follows:

Tinv (s) =vdc (s)

(s)= 2

sCdc Vdc(Vs, a io, a cos a

+ Vs, b io, b cos b + Vs, c io, c cos c ). (22)

Detailed derivation of (19)(22) are given in the Appendix.

Fig. 8. Circuit schematic of the power-flow controller.

5) PLL: The PLL consists of three components, including

the phase detector (PD), loop filter (LF), and the voltage-

controlled oscillator (VCO) [27]. Based on [19], thesmall-signal

model of the PLL is as follows:

TPL L (s) =(s)

v(s)=

Tvc o (s)FC(s)

1 Tvc o (s)Tp d (s)FL (s)

= A2n

s2 + 2n s + 2n (23)

where A = (Rl /Rc Kp d ), = 1/2

Kp d Kl Kvc o , and

n =

Kp d Kl Kvc o /, Kp d , Kl , Kvc o are the constant gainsof PD, LF and VCO, respectively.

6) Power-Flow Controller: The function of the power-flow

controller is to regulate vdc at the reference voltage Vdc , whichis determined by the voltage ratings of the capacitor and the

switches. Charging or discharging the capacitor Cdc is achievedby adjusting n in three phases individually. The regulationaction is performed by the error amplifier shown in Fig. 8. The

transfer function TC(s) can be shown in (24), at the bottom of

the page.

V. SIMPLIFIED DESIGN PROCEDURES

The values ofL, C, and Cdc in the inverter, R1 , R2 , C1 , andC2 in the power-flow controller are designed as follows.

A. Design of L andC in the Inverter

The values of L and C in the output filters are determinedby considering the maximum voltage drop across the inductor

vL, D at the maximum line current Io, ma x , angular line frequency, maximum ripple current Iripple , and angular switching fre-quency sw . As most of the load current is designed to flowthrough L, the value ofL is determined by considering that itsvoltage drop vL, D is small at the maximum line current Io, m ax .Thus

LIo, m ax < vL ,D L < vL, DIo, m ax

. (25a)

As the inverter output consists of high-frequency harmonics,

the fundamental component of the ripple current through the

filter is designed to be less than Iripple . For the sake of simplicity

TC(s) =vvdc

= s2 + ((1/R2 C2 ) + (1/R2 C1 ) + (1/R1 C2 ))s + (1/R1 R2 C1 C2 )

s (s + (C1 + C2 )/(R2 C1 C2 )). (24)


7/14


Fig. 9. Small-signal characteristics, TO L (s).

in the calculation, the load impedance at the switching frequency

is assumed to be infinite. Thus2vdc

1

sw L (1/sw C) < Iripple

C > 1sw (sw L (2vdc /Iripple ) . (25b)

The nominal switching frequency is chosen to be a few hun-

dred times the line frequency. vL, D is chosen to be 1% of theline voltage, and Iripple is chosen to one half of the peak of theline current. As shown in Table I, sw = 300 , vL, D = 2 V,and Iripple = 2.6 A for the designed prototype. Based on (25)and stated criteria, the values ofL and Cin the output filters are

determined.

B. Design of Cdc in the Inverter

The value ofCdc is determined by

Cdc

=4 (vo, no rvs, m in ) (io, a cos a +io, b cos b +io, c cos c ) tre s

v2dc ,re f 8 (vo, no r vs, mi n )2

(26)

where vo, no r and vs, m in are nominal value of load voltage andminimum voltage of supply voltage in specification, respec-

tively, tre s is duration of restoration.Detailed derivation of (26) is given in the Appendix.

C. Design ofR1, R2, C1, andC2 in the Power-Flow Controller

The pole and zeros are designed as follows:

log p = log z 2 20

(27)

Detailed derivation of (27) is given in the Appendix.

Typically, = 20 is chosen, and the ratio of z 1 and z 2 ischosen to be at least 100, in order to avoid overlapping in the

two zeros. Therefore

log z 1 = log z 2 2. (28)Fig. 10. Waveforms at three sagged conditions. (a) vs, a is changed from 220

to 120 Vrm s . (b) vs, a , vs, b , and vs, c are changed from 220 to 150 Vrm s .


8/14


Fig. 11. Enlarged transient waveforms in the three sagged conditions shownin Fig. 10. (a) Single-phase sag in Fig. 10(a). (b) Three-phase sag in Fig. 10(b).

Based on (24), we have

z 1 + z 2 =1

R2 C2+

1

R2 C1+

1

R1 C2(29)

z 1 z 2 =1

R1 R2 C1 C2(30)

P =C1 + C2

R2 C1 C2. (31)

Fig. 12. Dynamic behaviors ofvd c in the three sagged conditions shown inFig. 10. (a) Single-phase sag in Fig. 10(a). (b) Three-phase sag in Fig. 10(b).

Based on (29)(31), R1 , R2 , C1 , and C2 are designed byputting a value into one of them. Fig. 9 shows the loop gain

TO L (s), it is based on thespecifications anddesignedcomponentvalues listed in Tables II and III. The bode plot shows operation

range, the frequency between cross,mi n , and cross,m ax withinthe stable regions.

VI. EXPERIMENTAL VERIFICATIONS

A 1.5-kVA, 220-V, 50-Hz prototype has been built and

tested. The system is supplying to nonlinear inductive loads,

P F (power factor) = 0.5. The specifications and the compo-nent values are tabulated in Tables IIII. The values of the com-

ponents are designed by the procedures described in Section V.

The prototype has been tested with four different types of volt-

age disturbances, including voltage sags, voltage swells, supply

voltage distortion, and three-phase voltage unbalancing.

A. Voltage Sags

Voltage sags are programmed to occur during the supply volt-

age at the peak value in the following tests. Fig. 10(a) shows the


9/14


Fig. 13. Waveforms at three swelled conditions. (a) vs, a is changed from 220to 260 Vrm s . (b) vs, a , vs, b , and vs , c are changed from 220 to 260 Vrm s .

Fig.14. Enlarged transientwaveformsin thethree swelled conditions shown inFig. 13.(a) Single-phaseswell in Fig. 13(a). (b) Three-phase swell in Fig. 13(b).

waveforms of the DVR when there is a single-phase sag. vs, ais sagged from 220 to 120 V (45% sag). Fig. 2(a) shows the

phasor diagram of Fig. 10(a) in steady state. Fig. 10(b) shows

the waveform when there is three-phase sag. The three-phase

voltage sources arechanged from 220to 150 V. Fig. 11 shows the


10/14


Fig. 15. Dynamic behavior ofvd c in three voltage-swell conditions shown inFig. 13.(a) Single-phaseswell in Fig. 13(a). (b)Three-phaseswell in Fig. 13(b).

enlarged load-voltage transients in the corresponding sagged.

The transients should ideally settle into the steady state in two

switching actions. However, as the second-order switching sur-

face has discrepancies with the ideal switching surface [31],

the transients require taking three to four switching actions be-

fore settling into the steady state. The transition times are 250

and 180 s, respectively, in the aforementioned two cases. Nev-ertheless, the transition duration is shorter than some recently

proposed control schemes [4], [6], [28][30] in similar voltage-

sag conditions. The responses of inner loop were evaluated in

the aforementioned experimental results. Fig. 12 shows the dy-

namic responses of outer loop, power-flow controller, and the

dc-link voltage variations in the two aforementioned cases. The

voltage sags start at t1 . The capacitor bank releases energyto the load until t2 . Finally, vdc is regulated to 380 V at t3 . InFig. 12, (t2 t1 ) = 310 ms and (t3 t1 ) = 3.8 s. In Fig. 12(b),(t2 t1 ) = 250 ms and (t3 t1 ) = 7.1 s.

B. Voltage Swells

Fig. 13(a) and (b) shows the waveforms of the DVR in single-

phase and three-phase swells, respectively. The swelled phase(s)

Fig. 16. Waveforms with all three phase voltages distorted.

Fig. 17. Harmonic content of the distorted supply voltage and load voltage inFig. 16

is (are) changed from 220 Vrm s to 260 Vrm s . Fig. 14 shows

the enlarged load-voltage transients in the two cases. The loadvoltage can be restored to the steady state in two switching

actions, taking about 180 s in the two cases.Fig. 15 shows the dc-link voltage variations in the two afore-

mentioned cases. The voltage swells start at t1 . The capaci-tor bank absorbs energy from the grid until t2 . Finally, vdc isregulated to 380 V at t3 . In Fig. 15(a), (t2 t1 ) = 170 msand (t3 t1 ) = 1.5 s. In Fig. 15(b), (t2 t1 ) = 190 ms and(t3 t1 ) = 2.7 s.

C. Harmonic Distortions

Fig. 16 shows the waveforms of the DVR, when vs, a , vs, b ,and

vs, c are seriously polluted which contain third-, fifth-, seventh-,


11/14


Fig. 18. Waveforms with unbalanced three-phase voltages.

and ninth-order harmonic components. The DVR acts as a

series-type harmonic-voltage compensator to filter out the har-

monic components and provide quality voltage at the output.

The waveforms ofvo, a , vo, b , and vo, c are all sinusoidal. Fig. 17shows the harmonic contents of the supply voltage and the load

voltage up to 19th harmonics. Even if the phase voltages have

the total harmonic distortion (THD) over 42%, the THD of vo, a ,vo, b , and vo, c are less than 6%. This confirms the function of theDVR for compensating the supply voltage distortion.

D. Voltage Unbalance

Fig. 18 shows the waveforms of the DVR, when three phase

supply voltage are unbalanced. In this study, vs, a = 210 V(95%), vs, b = 190 V (86%), and vs, c = 240 V (110%). Fig. 2(b)

shows the phasor diagram of the situation. The system is oper-ating in the steady state and the load voltages are all regulated at

the nominal value. All these results are in good agreement with

the theoretical predictions.

The proposed control scheme is for DVR supplying to at least

one phase-inductive load, it is equally applicable for resistive

load if the dc side of the inverter is powered by an external

source for compensating the inverter energy loss.

Moreover, the proposed method can be implemented by pro-

gramming the switching function in the digital controller. Fur-

ther research will be investigated into the digital implementation

of the power-flow controller [35]. This will increase the flexi-

bility of the proposed method.

VII. CONCLUSION

A control scheme for three-phase capacitor-supported inter-

line DVR hasbeen presented. By integrating a recently proposed

boundary-control method with second-order switching surface

(inner loop), the dynamic response has been minimized to two

switching actions. The voltage sag, swell, and voltage harmonic

distortion have been compensated by this DVR. Moreover, byusing series bidirectional inverter as DVR, capacitor banks are

used to support the dc link and the sagged phase(s) could be sup-

ported by the unsagged phase(s). Long-duration voltage sags,

swell, and three-phase voltage unbalance could be overcome by

the proposed power-flow controller (outer loop). The method

has been verified with a 1.5-kVA system. The performances

of the DVR have been demonstrated and evaluated with dif-

ferent power-quality disturbances. Experimental measurements

are favorably verified with theoretical results.

APPENDIX

A. Derivation of (18)

By using the cosine law, we have

v2d, n = v2o, n + v

2s, n 2vo, n vs, n cos (A1)

v2o, n = v2d, n + v

2s, n 2vd, n vs, n cos n . (A2)

Based on (A1) and (A2), we have

cos n =vs, n vo, n cos

v2o, n + v2s, n 2vo, n vs, n cos

. (A3)

By substituting (A1), (A3), and (17) into (16), (18) can be

obtained.

B. Derivation of (19)

The energy EC stored in the dc capacitors is equal to

EC =1

2

Cdc2

v2dc . (A4)

The power flow of the capacitors in the steady state is equal

to

pdc (t) =1

2Cdc vdc

dvdcdt

. (A5)

By introducing small-signal perturbations into pdc and vdc ,we have

pdc (t) = Pdc + pdc (t) (A6)

and

vdc (t) = Vdc + vdc (t) (A7)

where Pdc and Vdc , are the steady-state values of pdc and vdc ,respectively.

By substituting (A6) and (A7) into (A5), it can be shown that

pdc =1

2Cdc Vdc

dvdcdt

. (A8)

After taking the Laplace transformation of (A8), (19) can be

obtained.


12/14


C. Derivation of (20)

By introducing small-signal perturbations into pn , vd, n , andn , we have

pn = Pn + pn (A9)

vd, n = Vd, n + vd, n (A10)

and

n = n + n (A11)

where Pn , Vd, n , and n are the steady-state values of pn , vd, n ,and n , respectively.

By substituting (A9)(A11) into (15) and taking the Laplace

transformation, (20) can be obtained.

D. Derivation of (21)

As the PLL adjusts the phase angle of vo, n , it results invarying n . As depicted in Fig. 2(a), the phase relationshipbetween and n can be shown to be

vo, n sin n = vd, n sin n + vs, n sin(n ). (A12)By differentiating (A12), we have

0 = sin ndvd, n

dt+ vd, n cos n

dndt

vs, n cos(n ) ddt

.

(A13)

By using cosine law, we have

v2s, n = v2d, n + v

2o, n 2vo, n vd, n cos( n n ). (A14)

By using (A1) and (A14), we have

vo, n = vs, n cos

vd, n cos(n + n ). (A15)

By differentiating (A15), we have

0 = cos(n + n ) dvd, ndt

+vd, n sin(n + n )dndt

vs sin ddt

. (A16)

By using (A13) and (A16), it can be shown that

dnd

=vs, nvd, n

cos( n n ). (A17)

By considering the small-signal variations and taking the

Laplace transformation, the transfer function of the phase trans-

formation Tpt ,n (s) is

Tpt ,n (s) =n (s)

(s)=

Vs, nVd, n

cos(B n n ) (A18)

where Vs, n , and B are the steady-state values of vs, n and ,respectively.

By substituting (A3) into (A18), (21) can be obtained.

E. Derivation of (22)

By combining (20) and (A18), it can be shown that

pn (s)

(s)=

Vs, n io, n cos n . (A19)

On the ac side of the inverter, the power flow pac is equal tothe sum of power in each phase

pac = pa +pb +pc (A20)

pac = pa + pb + pc . (A21)

By using the conservation of energy, we have

pdc = pac (A22)

and combining (19) and (A19), (22) can be obtained.

F. Derivation of (26)

The design of Cdc value is based on the restoration dura-tion, load characteristics, and voltage rating of the DVR. The

amount of energy delivered from the capacitors in tre s is thedifference between the three-phase total load energy and total

supply energy. By using the conservation of energy, we have

1

2

Cdc

2v2dc ,re f

v2dc ,m in= [(vo, a vs, a ) io, a cos a + (vo, b vs, b ) io, b cos b

+ (vo, c vs, c ) io, c cos c ] tre s . (A23)By considering the worst case, the three-phase supply volt-

ages are sagged to the minimum voltage, as defined in the spec-

ification.

Based on (1), in order to avoid generating distorted sinusoidal

waveform at the output, when vdc is higher than the peak valueofvd . Otherwise, the situation will be similar to overmodulationin standard pulsewidth modulation (PWM) that gives distorted

output [34]. vdc ,mi n is designed to be equal to the peak value of

the injecting voltage, i.e.,

vdc ,m in = 2

2 (vo, no r vs, mi n ) . (A24)By combining (A23) and (A24), (26) can be obtained.

G. Derivation of (27)

As the transfer function of T1 (s) in load-dependent, it isnecessary to design a controller that can ensure the stability

within the operating range. According to Fig. 7, the loop gain

TO L (s) of the control loop with power-flow controller is equalto

TO L (s) = TC(s)T1 (s) (A25)where T1 (s) = TP L L (s)Tinv (s)KT (s) is the transfer functionof the inverter and PLL in Fig. 7. KT (s) is the transfer functionof the transducer shown in Fig. 7.

In order to ensure TO L (s) has the phase margin of 30 within

the designed operating range, the error amplifier is designed to

have one pole at p and two zeros at the frequencies ofz 1 andz 2 , respectively. The circuit schematic and TC(s) are shownin Fig. 8.

By considering the upper bound ofT1 (s), TU1 (s), cross,m ax

is chosen to be the frequency at which |TU1 (jcross,ma x )| 0 dB and lower than the line frequency. As the phase ofTOL (s),

O L , at cross,m ax must be larger than 150 for achieving


13/14


sufficient phase margin, it is determined by

OL = 1 + C + 360 (A26)

z 2 is chosen to be the frequency by

log z 2 = log cross,m ax C(jcross,m ax ) C(jz 2 )Phase Slope

(A27)where the typical value of phase slope in bode plot is 45/decade,and the phase at zero is 135 for controller shown in Fig. 8.

By considering the lower bound of T1 (s), TL

1 (s), cross,mi nis chosen to be the frequency at which

TL1 (jcross,m in ) = dB. By considering the phase characteristic of TC(s), therelationship among cross,m in , p , and z 1 is

z 1 < cross,m in < p (A28)

p is determined by considering that |TC(p )| = dB. Thus,(27) can be obtained.

REFERENCES[1] M. Bollen, Understanding Power Quality Problems, Voltage Sags and

Interruptions. New York: IEEE Press, 2000.[2] M. Sullivan, T. Vardell, and M. Johnson, Power interruption costs to

industrial and commercial consumers of electricity, IEEE Trans. Ind.App., vol. 33, no. 6, pp. 14481458, Nov. 1997.

[3] N. Woodley, L. Morgan, and A. Sundaram, Experience with an inverter-based dynamic voltage restorer, IEEE Trans. Power Del., vol. 14, no. 3,pp. 11811186, Jul. 1999.

[4] R. R. Errabelli, Y. Y. Kolhatkar, and S. P. Das, Experimental investigationof DVR with sliding mode control,in Proc. IEEEPower IndiaConf., Apr.2006, paper 117.

[5] S. Lee, H. Kim, and S. K. Sul, A novel control method for the compen-sation voltages in dynamic voltage restorers, in Proc. IEEE APEC 2004,vol. 1, pp. 614620.

[6] G. Joos, S. Chen, and L. Lopes, Closed-loop state variable control of

dynamicvoltagerestorerswith fastcompensationcharacteristics,in Proc.IEEE IAS 2004, Oct., vol. 4, pp. 22522258.

[7] P. Ruilin andZ. Yuegen, Slidingmode control strategyof dynamicvoltagerestorer, in Proc. ICIECA 2005, Nov./Dec., p. 3.

[8] T. Jauch, A. Kara, M. Rahmani, and D. Westermann, Power quality en-sured by dynamic voltage correction, ABB Rev., vol. 4, 1998, pp. 2536.

[9] C. S. Chang, S. W. Yang, and Y. S. Ho, Simulation and analysis of seriesvoltage restorer (SVR) for voltage sag relief, in Proc. IEEE PES Winter

Meeting, Jan, 2000, vol. 4, pp. 24762481.[10] C. Meyer, R. W. De Doncker, Y. W. Li, and F. Blaabjerg, Optimized

control strategy for a medium-voltage DVRTheoretical investigationsand experimental results, IEEE Trans. Power Electron., vol. 23, no. 6,pp. 27462754, Nov. 2008.

[11] S. S. Choi, B. H. Li, and D. M. Vilathgamuwa, Dynamic voltage regula-tion with minimum energy injection, IEEE Trans. Power Syst., vol. 15,no. 1, pp. 5157, Feb. 2000.

[12] D. M. Vilathgamuwa, A. A. D. R. Perera, and S. S. Choi, Voltage sagcompensation with energy optimized dynamic voltage restorer, IEEETrans. Power Del., vol. 18, no. 3, pp. 928936, Jul. 2003.

[13] K. Piatek, A new approach of DVR control with minimized energy in-jection, in Proc. PEMC2006, Aug., pp. 14901495.

[14] D. M. Vilathgamuwa, H. M. Wijekoon, and S. S. Choi, Interline dynamicvoltage restorer: A novel and economical approach for multiline powerquality compensation, IEEE Trans. Ind. Appl., vol. 40, no. 6, pp. 16781685, Nov./Dec. 2004.

[15] D. Vilathgamuwa, H. M. Wijekoon, and S. S. Choi, A novel technique tocompensate voltage sags in multiline distribution systemThe interlinedynamic voltage restorer, IEEE Trans. Ind. Electron., vol. 53, no. 5,pp. 16031611, Oct. 2006.

[16] R. J. Nelson and D. G. Ramey, Dynamic power and voltage regulatorfor an ac transmission line, U.S. Patent 5 610 501, Mar. 1997.

[17] A. van Zyl, R. Spee, A. Faveluke, and S. Bhowmik, Voltage sag ride-through for adjustable-speed drives with active rectifiers, IEEE Trans.

Ind. Appl., vol. 34, no. 6, pp. 12701277, Nov./Dec. 1998.

[18] A. Ghosh, A. K. Jindal, and A. Joshi, Design of a capacitor-supporteddynamic voltage restorer (DVR) for unbalanced and distorted loads,

IEEE Trans. Power Del., vol. 19, no. 1, pp. 405413, Jan. 2004.[19] C. Ho, H. Chung, and K. Au, Design and implementation of a fast dy-

namic control scheme for capacitor-supported dynamic voltage restorers,IEEE Trans. Power Electron., vol. 23, no. 1, pp. 237251, Jan. 2008.

[20] K. Leung and H. Chung, Derivation of a second-order switching surfacein the boundary control of buck converters, IEEE Power Electron. Lett.,vol. 2, no. 2, pp. 6367, Jun. 2004.

[21] K. Leung and H. Chung, A comparative study of the boundary control ofbuck converters using first- and second-order switching surfaces, IEEETrans. Power Electron., vol. 22, no. 4, pp. 11961209, Jul. 2007.

[22] D. O. Koval and M. B. Hughes, Canadian national power quality survey:Frequency of industrial and commercial voltage sags, IEEE Trans. Ind.

Appl., vol. 33, no. 3, pp. 622627, May/Jun. 1997.[23] A. El Moftyand K. Youssef, Industrialpower quality problems, in Proc.

IEE Conf. Electr. Distrib., Part 1: Contrib., Jun. 2001,vol. 2, pp.139139.[24] E. W. Gunther and H. Mebta, A survey of distribution system power

qualityPreliminary results, IEEE Trans. Power Del., vol. 10, no. 1,pp. 322329, Jan. 1995.

[25] M. H. J. Bollen, Voltage sags: Effects, mitigationand prediction, PowerEng. J., vol. 10, no. 3, pp. 129135, Jun. 1996.

[26] B. M. Weedy and B. J. Cory, Electric Power System, 4th ed. New York:Wiley, 1998.

[27] H. M. Berlin, Design of Phase-Locked Loop Circuits with Experiments,

1st ed. Indianapolis, IN: Sams, 1985.[28] H. Kim and S. K. Sul, Compensation voltage control in dynamic voltagerestorers by use of feed forward and state feedback scheme, IEEE Trans.Power Electron., vol. 20, no. 5, pp. 11691176, Jan. 2005.

[29] B. Wang,G. Venkataramanan, andM. Illindala,Operation andcontrolof adynamic voltage restorer using transformer coupled H-bridge converters,

IEEE Trans. Power Electron., vol. 21, no. 4, pp. 10531061, Jun. 2006.[30] H. Awad, J. Svensson, and M Bollen, Mitigation of unbalanced volt-

age dips using static series compensator, IEEE Trans. Power Electron.,vol. 19, no. 3, pp. 837846, May 2004.

[31] Y. Chiu, K. Leung, andH. Chung, High-order switchingsurfacein bound-ary control of inverters, IEEE Trans. Power Electron., vol. 22, no. 5,pp. 17531765, Sep. 2007.

[32] M. Ordonez, J. E. Quaicoe, and M. T. Iqbal, Advanced boundary controlof inverters using the natural switching surface: Normalized geometricalderivation, IEEE Trans. Power Electron., vol. 23, no. 6, pp. 29152930,Nov. 2008.

[33] S. Chen, Y. M. Lai, S. C. Tan, and C. K. Tse, Boundary control withripple-derived switching surface for DCAC inverters, IEEE Trans.Power Electron., vol. 24, no. 12, pp. 28732885, Dec. 2009.

[34] M. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rded. Englewood Cliffs, NJ: Prentice-Hall, 2004.

[35] C. Ho,K. Au,and H. Chung, Digital implementationof boundarycontrolwith second-order switching surface, in Proc. IEEE PESC2007, Jun.,pp. 16581664.

Carl Ngai-Man Ho (M07) received the B.Eng. andM.Eng. double degrees and the Ph.D. degree in elec-tronic engineering from the City University of HongKong, Kowloon, Hong Kong, in 2002 and 2007, re-spectively.

From 2002 to 2003, he was a Research Assistantat the City University of Hong Kong. From 2003 to2005, he was an Engineer at e.Energy TechnologyLtd., Hong Kong. Since May 2007, he has been aScientist at ABB Corporate Research, Ltd., Baden-Dattwil, Switzerland. His Ph.D. work focused on the

development of dynamic voltage regulation and restoration technology. Hiscurrent research interests include power electronics, power quality, modelingand control of power converters, and characterization of wide bandgap (WBG)power semiconductor devices andtheirapplications. He holdstwo U.K. andoneU.S. patents in the area of lighting applications.

Dr. Ho was a Reviewer for the IEEE TRANSACTIONS ON POWER ELEC-TRONICS, the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, the IEEE

TRANSACTIONS ON CIRCUITS AND SYSTEMS, and several conferences.


14/14


Henry Shu-Hung Chung (M95SM03) receivedthe B.Eng. degree in electrical engineering and thePh.D. degree from Hong Kong Polytechnic Univer-sity, Kowloon, HongKong, in 1991 and 1994, respec-tively.

Since 1995, he has been at the City Univer-sity of Hong Kong (CityU), where he is currently aProfessor in the Department of Electronic Engineer-ing and Chief Technical Officer of e.Energy Technol-ogy Ltd.an associated company of CityU. His re-search interests include time- and frequency-domain

analysis of power electronic circuits, switched-capacitor-based converters,random-switching techniques, control methods, digital audio amplifiers, soft-switching converters, and electronic ballast design. He has authored or coau-thoredsix research book chapters andmore than 260technical papers, including120 refereed journal papers in his research areas. He holds 12 patents.

Dr. Chung was IEEE Student Branch Counselor and was a Track Chair of thetechnical committee on power electronics circuits and power systems of IEEECircuits and Systems Society in 19971998. He was an Associate Editor andthe Guest Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSPARTI: FUNDAMENTAL THEORY AND APPLICATIONS in 19992003. He is currently anAssociate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS. He wasthe recipient of the Grand Applied Research Excellence Award in 2001 fromthe CityU.

digital voltage restorer

Documents