DIGITAL SYSTEMS

Read Only– and Random Access Memory ( ROM – RAM)

2.12.04Rudolf Tracht and A.J. Han Vinck

content• Read Only Memory

– Structure

• Random Access Memory– SRAM– DRAM

Read Only Memory (ROM)

• Storage of bits in a structured way:– Two dimensional 2n x b

– Every address specifies a pre-programmed output

2n addressesb-bits wide output

Content „non-volatile“• Non-volatile: Content stays on chip, even without power

• Several types:• mask ROMROMs content programmed by manufacturer• PROMPROM: Programmable ROM. All bits are pre-programmed to

be 1. Bits (specified by address location) can be set to be equal to 0 by customer

• EPROMEPROM „erasable PROM“: Ultraviolet light „resets“ all bits equal to 1

• EEPROMEEPROM "electrically erasable PROM“: individual bits can be reset to 1. (application smart-cards)

Some ROM applications

• CPU primitive instruction set• CD-ROM • ROM for logic functions, it stores a truth table

– Structured design methods: simplification is not needed – Standardized building block: all ROMs are manufactured in

identical steps except for the final customization phase– Example: Simple pre-programmed multiplier

example

• Multiply 2 x 2 bit words:

A*B = C A*B = C00 00 0000 10 00 000000 01 0000 10 01 001000 10 0000 10 10 010000 11 0000 10 11 011001 00 0000 11 00 000001 01 0001 11 01 001101 10 0010 11 10 011001 11 0011 11 11 1001

2n × b ROM organization•n address inputs specify 2n unique data words

decoder

b - outputs

ROM-array

Implementation with MOSTo store a 1 at a location:connect row j line to column iline with a MOSFET

To include a minterm to output: connect row j line to column i line with a transistor

R

invertor

L

L

H

H

H

L

•••j

i

i

decoder

H

L

j

L

L

L

•••

basic 2n x b ROM structures

decoder

select 1-out-of

2 m rows

array

select 1-out of

2n-m words

address

address

CS

OE

m-bits

n-m-bits

1

1

0

1

2n-m x b bits wide

Chip select

Output enable

- output enable when

CS. NAND. OE = 0

multiplexer

b bits

•••

Column multiplex

four 8 x 1 multiplexer

Cascading memory modules

• example 256 X 8 ROM using 256 X 4 parts:

F0 = A' B' C + A B' C' + A B' CF1 = A' B' C + A' B C' + A B CF2 = A' B' C' + A' B' C + A B' C'F3 = A' B C + A B' C' + A B C'

example

• Combinational logic implementation (two-level canonical form) using a ROM

A

B

C

F0F1 F2 F3

8 x 4

RAM- write or read information

2n x b RAM

•••b-bits wide input

•••

n-bits wide address

••• b-bits wide output

control

CS OE WECS: Chip select

OE: Output enable

WE: Write enable

Content „Volatile“

• Volatile: looses content after Power-loss– Random Access Memory (RAM): access time constant

• DRAMDRAM "dynamic" (high density, low speed)

used in main memory

• SRAMSRAM "static" (low density, high speed) used in CPU register file

2D Memory Architecture

A0

Row

Dec

o der

A1

Aj-1

bit lineword line

storage (RAM) cell

Row

Add

r ess

Col

umn

Add

r ess

Aj

Aj+1

Ak-1

Read/Write Circuits

Column Decoder

2k-j

m2j

Input/Output (m bits)

selects appropriate word from memory row

Typical parallel DRAM organization

256Kb256Kb

256Kb

01

7•••

•••

512

rows

512

columns

2Mbit DRAM: 256K x 8bits = 218 x 8bits = 29 rows x 29 columns x 8 bits

AS7C4096

Internal structure of a 1x2 static RAMin1 in0

D Q

C

inselwr

in outselwr

in outselwr

in outselwr

in outselwr

1 x 2

decoder

out1 out0

WECS

OE

1

10

WE CS OE

1 1 0 latch open

0 1 0 latch closed

0 1 1 read content

sel = 1 makes output available

Bidirectional bus structure

in1 in0

D Q

C

inselwr

in outselwr

in outselwr

in outselwr

in outselwr

1 x 2

decoder

out1 out0

WECS

OE

1

10

WE CS OE

1 1 0 latch open

0 1 0 latch closed

0 1 1 read content

1 1 1 latch closed

* 0 * latch closed

sel = 1 makes output available

Static RAM (SRAM)WordLine

Bit!Bit

Read: Make word line H

sense value on bit lines

Write:

Make word line H

put values to Bit and !Bit

flip-flop stays in stable state when word line L

!Bit = NOT(Bit)

6 MOSFETS low density

higher cost/bit, but fast

Dynamic RAM (DRAM)

Bit Line

Word Line Read: - make word line H,

- sense voltage on bit line (destroys saved value, i.e. content must be written back)

Write: - make word line H- put new value on bit line- make word line L ( freeze the capacitor load )

Refresh cycles are needed for the whole memory to restore the content! (do dummy read)

Small cell high density lower speed more difficult to produce

memory access• Hardware Registers (CPU)• Random Access: access time is the same for all locations

– SRAM: Static Random Access Memory• Low density, high power, expensive, fast• Static: content will last “forever”(until no power)

– DRAM: Dynamic Random Access Memory• High density, low power, cheap, slow• Dynamic: need to be “refreshed” regularly

• “Not-so-random” Access Technology:– Access time varies from location to location and from time to time– Examples: Disk, CDROM, DRAM page-mode access

• Sequential Access Technology: access time linear in location (e.g.,Tape)

speed

size

DRAM Generation

‘84 ‘87 ‘90 ‘93 ‘96 ‘99

1 Mb 4 Mb 16 Mb 64 Mb 256 Mb 1 Gb

55 85 130 200 300 450

30 47 72 110 165 250

28.84 11.1 4.26 1.64 0.61 0.23

(from Kazuhiro Sakashita, Mitsubishi)

DRAM over time

1st Gen. Sample

Memory Size

Die Size (mm2)

Memory Area (mm2)

Memory Cell Area (µm2)

trends

Capacity Speed (latency)Logic: 2x in 3 years 2x in 3 yearsDRAM: 4x in 3 years 2x in 10 yearsDisk: 4x in 3 years 2x in 10 years

µProc60%/yr.(2X/1.5yr)

DRAM9%/yr.(2X/10 yrs)1

10

100

100019

8019

81 19

8319

8419

85 19

8619

8719

8819

8919

9019

91 19

9219

9319

9419

9519

9619

9719

98 19

9920

00

DRAM

CPU19

82

Processor-MemoryPerformance Gap:(grows 50% / year)

Perf

orm

ance

Processor-DRAM Memory Gap (speed)

Page Mode/EDO RAM

Latch

• Normal RAM drives many bits (row) out of array, selects few to output.

• Adding latch at row outputs allows us to save an entire row of the RAM

• Later accesses to the RAM can eliminate the row access time, just need column access time

• Most common in DRAM, page-mode SRAMs also exist