Digital Logic Design IDigital Logic Design IELEC2170ELEC2170--11

Dr. Roberto Muscederermusced@uwindsor.ca

© 2003-2021 Roberto Muscedere 2

Who is Roberto Who is Roberto MuscedereMuscedere??• Roberto Muscedere (Moo-shed-er-ay)

• “Sir” also works

• Education (University of Windsor)• Undergraduate (1992-1996)• Masters (1996-1999)• Ph.D. (1999-2003)

• Associate Professor since 2004

© 2003-2021 Roberto Muscedere 3

Who is Roberto Who is Roberto MuscedereMuscedere??• Expertise

• VLSI/ASIC Design• System Level Design• Full and Semi Custom Hardware Implementation• Number Systems• Embedded Systems

• Only Human• Yes, I do make mistakes!• If something doesn’t make sense, ask me

© 2003-2021 Roberto Muscedere 4

Where is Roberto Where is Roberto MuscedereMuscedere??• CE3040

• I have a window office!• I never look out of it

• Office Hours and GAs• Check the website

© 2003-2021 Roberto Muscedere 5

Course ScheduleCourse Schedule• Lectures (3.0 hours/week)

• Tuesdays and Thursdays• 10:00am to 11:20am• Online

• Attendance is not mandatory, but recommended• Lecture slides only outline topics but don’t detail

discussion

© 2003-2021 Roberto Muscedere 6

Course ScheduleCourse Schedule• Labs/Tutorials (2 hours/week)

• Wednesdays• 12:30pm to 2:20pm (Section 51)

• Fridays• 12:30pm to 2:20pm (Section 52)

• Online

© 2003-2021 Roberto Muscedere 7

Grade Distribution (Preliminary)Grade Distribution (Preliminary)

• Assignments/Laboratories: 30%

• Mid-Term Exam: 35% (3 hours)

• Final Exam: 35% (3 hours)

• Grade assessment will be based on the sum of the above

© 2003-2021 Roberto Muscedere 8

Course Content (Calendar)Course Content (Calendar)• Boolean algebra and logic gates• Simplification of Boolean functions• Arithmetic operations• Analysis and design of combinatorial logic circuits

with SSI, MSI, and LSI• Sequential logic components• Registers• Counters and memory units• Analysis and synthesis of sequential synchronous

and asynchronous networks

© 2003-2021 Roberto Muscedere 9

TextbookTextbook• Digital design: with an

introduction to the Verilog HDL

• © 2013, 5th Edition• M. Morris Mano, and

Michael D. Ciletti• ISBN13: 978-0-13-277420-8• ISBN10: 0-13-277420-8

© 2003-2021 Roberto Muscedere 10

ExaminationsExaminations• Mid-Term Exam

• Week of February 8th or 22nd• Not during class time• Students decide…• Online and time limited

• Final Exam• TBD - New system selects optimal date• Date CANNOT be changed• Online and time limited

© 2003-2021 Roberto Muscedere 11

WebsiteWebsite• Course Outline• Graduate Assistant’s Hours and Locations• Lectures

• https://courses.muscedere.com