digital electonics done
TRANSCRIPT
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Table of content
1.1 Abstract... (Page 2)1.2 Introduction..(Page 3)
1.3 Analyzing Synchronous Sequential Circuit1.1.1 Next state Table.. (Page 4)
1.1.2 Implementation table... (Page 4)
1.1.3 Excitation equations..................... (Page 4)
1.1.4 Output table & output equations. (Page 5)
1.1.5 Resultant FSM circuit.. (Page 5)1.1.6 VHDL.. (Page 6,7,8)
1.4 Introduction. (Page 9)
1.5 Designing Synchronous Sequential Circuit
2.1.1 Next state table. (Page 10)
2.1.2 Implementation Table (Page 11)
2.1.3 K-maps (Page 12, 13)
2.1.4 Circuit diagram for stepper motor controller.. (Page 14)
2.1.5 VHDL (Page 15, 16, 17, 18)
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Abstract
To analyze the synchronous sequential logic
circuits it is the process in which we are
given sequential circuit and we want to
obtain precise description of operation of the
circuit by deriving the state diagram for it.
The first question all is about the sequential
logic and it has a given steps to solve it.
Anyway final result should be a state
diagram which is either Mealy or Moore
model.
A stepper motor is a brushless DC electric
motor that can divide a full rotation into a
large number of steps. The motor's position
can be controlled precisely without any
feedback mechanism as long as the motor is
carefully sized to the application. The
second question all is about and we have to
design a synchronous sequential circuit for
that.
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Question 1
Introduction
An asynchronous circuit is a circuit which
operates by clock signal. They are not
governed by a clock circuit or global clock
signal, but instead need only wait for the
signals that indicate completion of
instructions and operations. These signals
are specified by simple data transfer
protocols. This digital logic design iscontrasted with a synchronous circuit which
operates according to clock timing signals.
To analyze those kind of designs there have
steps they are
1. Derive the excitation equations from the
next state logic circuit.
2. Derive the next-state equations by
substituting the excitation equations into the
flip-flops characteristic equations.
3. Derive the next-state table from the next-
state equations.
4. Derive the output equations from the
output logic circuit.
5. Derive the output table from the output
equations.
6. Draw the state diagram from the next-
state table and the output table.
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1) This is the Moore model FSM.2) Excitation Equations
= (A + ) (A +)
= A +
= (A + Q1) (A + Q2)
= A +
3) Next state equations= = D
= A +
= A +
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4) Next state table
5) Output EquationX =
6) Resultant FSM Circuit
Present State
Input
A
Next State
Output
X
0 0 0 0 0 0
0 0 1 1 1 0
0 1 0 0 0 1
0 1 1 1 1 1
1 0 0 0 1 1
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 1 1
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Q1_FIG1 IS
PORT
(
A : IN STD_LOGIC;
CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
X : OUT STD_LOGIC
);
END Q1_FIG1;
ARCHITECTURE bdf_type OF Q1_FIG1 IS
SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC;
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BEGIN
PROCESS(CLK,CLR)
BEGIN
IF (CLR = '0') THEN
SYNTHESIZED_WIRE_7
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Figure 2
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Question 2
Introduction
A stepper motor is a brushless DC electric
motor that can divide a full rotation into a
large number of steps. The motor's position
can be controlled precisely without any
feedback mechanism as long as the motor is
carefully sized to the application. The
second question all is about and we have to
design a synchronous sequential circuit for
that.The design of the sequential circuits is
just the reverse of analysis of sequential
circuits. The steps for the design of
sequential circuits are as follows:
Produce a state diagram from thefunctional description of the circuit.
Derive the next-state table from thestate diagram.
Convert the next-state table to theimplementation table.
Derive the excitation equations foreach flip-flop input from the
implementation table.
Derive the output table from the statediagram.
Derive the output equations from theoutput table.
Draw the FSM circuit diagram basedon the excitations and output
equations.
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1) Next State Table
C
0 0 0 0 0 0 1 0 1
0 0 0 0 1 0 1 0 1
0 0 0 1 0 0 1 0 1
0 0 0 1 1 1 0 0 1
0 0 1 0 0 1 0 1 0
0 0 1 0 1 0 1 1 0
0 0 1 1 0 0 1 0 1
0 0 1 1 1 0 1 0 1
0 1 0 0 0 0 1 1 0
0 1 0 0 1 0 1 0 1
0 1 0 1 0 0 1 0 0
0 1 0 1 1 0 0 0 1
0 1 1 0 0 0 0 1 0
0 1 1 0 1 0 1 0 0
0 1 1 1 0 0 1 0 1
0 1 1 1 1 0 1 0 1
1 0 0 0 0 1 0 0 1
1 0 0 0 1 1 0 1 0
1 0 0 1 0 0 0 0 1
1 0 0 1 1 1 0 0 0
1 0 1 0 0 1 0 0 0
1 0 1 0 1 0 0 1 0
1 0 1 1 0 0 1 0 1
1 0 1 1 1 0 1 0 1
1 1 0 0 0 0 1 0 1
1 1 0 0 1 0 1 0 1
1 1 0 1 0 0 1 0 1
1 1 0 1 1 0 1 0 1
1 1 1 0 0 0 1 0 1
1 1 1 0 1 0 1 0 1
1 1 1 1 0 0 1 0 1
1 1 1 1 1 0 1 0 1
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2) Implementation Table
C
0 0 0 0 0 0 1 0 1
0 0 0 0 1 0 1 0 1
0 0 0 1 0 0 1 0 1
0 0 0 1 1 1 0 0 1
0 0 1 0 0 1 0 1 0
0 0 1 0 1 0 1 1 0
0 0 1 1 0 0 1 0 1
0 0 1 1 1 0 1 0 1
0 1 0 0 0 0 1 1 0
0 1 0 0 1 0 1 0 1
0 1 0 1 0 0 1 0 0
0 1 0 1 1 0 0 0 1
0 1 1 0 0 0 0 1 0
0 1 1 0 1 0 1 0 0
0 1 1 1 0 0 1 0 1
0 1 1 1 1 0 1 0 1
1 0 0 0 0 1 0 0 1
1 0 0 0 1 1 0 1 0
1 0 0 1 0 0 0 0 1
1 0 0 1 1 1 0 0 0
1 0 1 0 0 1 0 0 0
1 0 1 0 1 0 0 1 0
1 0 1 1 0 0 1 0 1
1 0 1 1 1 0 1 0 1
1 1 0 0 0 0 1 0 1
1 1 0 0 1 0 1 0 1
1 1 0 1 0 0 1 0 1
1 1 0 1 1 0 1 0 1
1 1 1 0 0 0 1 0 1
1 1 1 0 1 0 1 0 1
1 1 1 1 0 0 1 0 1
1 1 1 1 1 0 1 0 1
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3) K-maps & excitation Equation
K-map for flip-flop
000 001 011 010 110 111 101 100
000 1 0 0 0 0 1
1
01 00 0 0 0 0 0 1
111 0 0 0 0 0 0
1
100 0 0 0 0 0 0 0
= + + +
K-map for flip-flop
000 001 011 010 110 111 101 100
001 0 0 1 1 1 0 0
011 1 1 1 1 1 0 0
110
11 0 1
11 0
10 11 1 1 1 1 1 0
= + + + + +
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K-map for flip-flop
000 001 011 010 110 111 101 100
000 1 1 1 0 0 0 0
010 1 0 0 0 0 1 1
110 0 0 0 0 0 0 0
10
0 0 0 0 0 0 0 0
= + + +
K-map for flip-flop
000 001 011 010 110 111 101 100
00 10 0 0
11 0
1
011
00 1 1 1 0 0
11 11 1
11 1 1 0
101 1 1 0 1 1
11
= + + + + + +
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Figure 3 the circuit diagram for stepper motor controller
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY tt2 IS
PORT
(
CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC
);
END tt2;
ARCHITECTURE bdf_type OF tt2 IS
SIGNAL SYNTHESIZED_WIRE_62 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_63 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_64 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_65 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_66 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_67 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_68 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_69 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_19 : STD_LOGIC;
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SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_21 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_22 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_23 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_24 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_25 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_26 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_27 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_28 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_37 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_38 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_39 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_40 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_41 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_42 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_54 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_55 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_56 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_57 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_58 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_59 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_60 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_61 : STD_LOGIC;
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BEGIN
Figure 4
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Figure 5
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