digital circuits and systems (ece124) tutorial, final...
TRANSCRIPT
Digital Circuits and Systems (ECE124) Tutorial, Final Review, Winter 2011
Should you have any questions on this review, please contact Arash. [[email protected]]
[Q1] For the following clocked sequential circuit with one input (X) and one output (Z):
1. Drive a state table and draw a state diagram for the circuit. 2. Redesign this circuit by replacing the Q1 flip-flop (i.e. the D flip-flop holding Q1 state) with a JK flip-
flop, and the Q2 flip-flop with a T flip-flop. Only show the excitation equations (or state equations) for J1, K1, and T2.
[Q2] For the table below describes a finite-state machine which has one input x and one output z:
1. Draw the state diagram of this machine. 2. Draw the implication chart and determine it is reducible or not? 3. Draw the merger diagram. 4. Identify the reduced set of states. 5. Make state assignments. 6. Implement circuit by D flip-flops.
Present State Next State Output (z)
x = 0 x = 1 x = 0 x = 1 A A E 1 0 B C F 0 0 C B H 0 1 D E F 0 0 E D A 0 1 F B F 1 1 G D H 0 1 H H G 1 0
[Q3] Consider the following state diagram for a circuit with one input X and one output Z. Analyze this state diagram and draw its circuit implementation using:
1. Synchronous JK flip-flop (state Q0) and T flip-flop (state Q1) and MUX-4x1 for Z 2. SR latches 3. Synchronous ROM
Digital Circuits and Systems (ECE124) Tutorial, Final Review, Winter 2011
Should you have any questions on this review, please contact Arash. [[email protected]]
[Q4] Draw a logic diagram for non-overlapped ‘101’ detector (Moore machine) with D-type flip-flops. [Q5] Given a 32x8 ROM chip with an enable input, show the block level required connections to construct a 128x8 ROM with 4 ROM chips and a decoder. How many data and address lines these ROMs have? [Q6] Implement the circuit defined by equation F(a,b,c,d) = ∑ m(0,5,6,7,11) using:
1. 4-to-1 multiplexers and logic gates. 2. 2-to-4 decoders with non-inverted outputs and logic gates. 3. Programmable Logic Array (PLA) along with inverters at the outputs.
[Q7] Use a 3-bit binary counter with active-high load (L) and Increment (I) control inputs (load has higher priority than increment) and implement a circuit (draw) to generate and repeat the following sequence at the output of the counter. Initial counter value is “000”. Check that you have implemented a self-correcting logic.
··· → 000 → 001 → 010 → 101 → 110 → 111 → 000 → ··· [Q8] Design a digital circuit that takes two 4-bit numbers A and B as input and generates output Z as follows:
• If A and B are odd numbers then Z=A-B • If A and B are even numbers then Z=B-A • If A is an even number and B is an odd number then Z=A+B • If A is an odd number and B is an even number then Z=A-B-1
Assume that you have access to as many as you need of AND, OR, INV, XOR gates and FULL-ADDER, DECODER and MULTIPLEXER of any size. [Q9] For the following programmed Programmable Array Logic (PAL) and Programmable Logic Array (PLA), find the function expressions for all outputs and draw the Karnaugh-Maps for functions "w" and "F".
[Q10] Two n-bit binary numbers x and y - stored in shift registers - are to be compared in an iterative mode. Implement the logic using NAND gates and one D-type flip-flop. The circuit output is 1 if x>y, otherwise 0 if x<=y.
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