die attach void impact study on ic package thermal behavior … · 2016-05-10 · aug 2006-sep 2009...

Dr Yang Yongbo

Infineon Technologies, Singapore

Die Attach Void Impact Study on IC Package Thermal Behavior with ANSYS Mechanical

For internal use only

Biography

Author : YANG YONGBO

Job Title : Staff Engineer

Department : IFAP OP BE DEV SIN VDS

Biography:

Graduated from Nanyang technological University (NTU) Singapore with Ph. D degree in mechanical engineering in Aug 2006;

Aug 2006-Sep 2009 Field process engineer of plasma etching in Lam Research supporting UMC, SSMC and Chartered Semiconductor;

Sep 2009-July 2013 RnD mechanical engineer in UTAC taking care thermo-mechanical simulation and mechanical test;

July 2013- Present Mechanical engineer for thermo/mechanical simulation in Infineon.

2Copyright © Infineon Technologies AG 2016. All rights reserved.


Infineon- Part of your life. Part of tomorrow

The simulation team compromises about 20 members, working on visual prototying and development services including thermal, mechanical and mold flow simulation/measurement.

In Singapore, there are 4 people.

3

Infineon Technologies, headquarter in Neubiberg near Munich, Germany, a world leader in semiconductor solutions that make life easier, safer and greener.

The key business is about microelectronics : offering semiconductors and systems for Automotive, Industrial Power Control, Power Management & Multimarket as well as Chip Card & Security

Infineon Technologies Asia Pacific Pte. Ltd (Singapore)

Copyright © Infineon Technologies AG 2016. All rights reserved.


IC package thermal concept

4

Typical thermal dissipation with die pad grounded

Typical leadframe package



Problem description

For power IC packages, the thermal dispense is critical to overall package performance.

Here the die attach is a high conductive die attach film (CDAF) which has high content of silver (Ag).

After assembly, some microvoid was found in the CDAF layer. If the void affect the chip temperature by 10%, the package will be rejected.

An IR camera is used to select package, as shown in the illustration.

Problem: the camera didn’t detect clear temperature difference (10%) at mold compound top surface.

Thermal simulation to see the reason

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CDAF void

ChipLeadframe

Experimental setup



Thermal modeling cases

Total 6 cases, with extreme conditions on void assumption, the temperature response on chip and mold cap top is studied.

6

Void assumption cases

DMOS (power)

Case Description Illustration

1 No air void

2 Center 1/4 area

3 Center 1/2 area

4 Full power area

5 Full non-power area

6 Center 1/2 area,top half DA

Chip surface powered area (DMOS)


Thermal source (DMOS)



FEM Modeling

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Package thermal model

Inside structure

Chip

Half of the package is modelled. The bottom exposed pad area is connected to cooling pad of temperature 25oC.

The void part is defined with air property

A power of w=1.0w is applied to DMOS area in all cases, and a transient study with steady convection is done.

An internal developed film coefficient applied at package surface for convection flow.



Temperature plotting

With full void beneath DMOS area, it can cause 9.0 degree difference on chip.

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Case 1Case 3

Case 4Case 5

Unit:Kelvin



Maximum temperature comparison

The maximum temp. on chip and minimum temp. on mold cap top are compared. Only case 4 (full void beneath DMOS area) shows significant temperature difference.

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Mold cap top corner

Chip top maximum temp

Junction temperature Case (mold cap) temperature


Average temperature comparison

Only case 4 shows big difference on average temperature of DMOS area.

if only focused on chip area at mold cap top, the difference is around 3.0 degree.

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Mold top chip area

DMOS top area



Heat flux of case 1: no air void

Without void, the heat flux path is directly down to chip, CDAF and leadframe.

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Time=1.0E-7s Time=1.78E-6s Time=5.6E-4s

Time=0.01s Time=0.178s Time=100s



Heat flux of case 4: full void beneath DMOS

With full void below DMOS area, the heat flux needs to by pass the void area.

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Time=1.0E-7s Time=1.78E-6s Time=5.6E-4s

Time=0.01s Time=0.178s Time=100s




Conclusion

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Only if full delam.(void) at DMOS area, the temp. difference could be possibly differentiated by 10%.

However, in reality, such case seldom happens, which explains why the IR camera cannot capture the difference.

Case Description Illustration

1 No air void

2 Center 1/4 area

3 Center 1/2 area

4 Full power area

5 Full non-power area

6 Center 1/2 area,top half DA

Monitor temp, [deg] Case1 Case2 Case3 Case4 Case5 Case6

DMOS top average temp

value 28.0 28.8 30.2 34.6 28.9 30.1

ratio 100% 102.8% 107.9% 123.7% 103.4% 107.5%

Mold top chip area average temp

value 26.3 26.7 27.5 29.3 27.4 27.5

ratio 100% 101.8% 104.8% 111.5% 104.3% 104.6%

Chip max. tempvalue 28.3 29.2 30.7 36.2 29.0 30.5

ratio 100% 102.9% 108.2% 127.8% 102.2% 107.8%

Zth-JC (deg/W) 3.3 4.2 5.7 11.2 3.9 5.5


Computation summary

Model

Transient thermal study: about 140K nodes, 130K elements

Workstation

HPZ820, HPC 6 cores of Intel [email protected], 128GB memory, no GPU

ANSYS HPC benefit:

With 6 core HPC licenses, 13minutes

With 2 core licenses, 30minutes

14Copyright © Infineon Technologies AG 2016. All rights reserved.

mailto:[email protected],128GB

die attach void impact study on ic package thermal behavior … · 2016-05-10 · aug 2006-sep 2009...

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