development of the depfet sensor with signal compression: a large format x-ray imager with...

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 59, NO. 6, DECEMBER 2012 3339

Development of the DEPFET Sensor WithSignal Compression: A Large Format

X-Ray Imager With Mega-Frame ReadoutCapability for the European XFEL

Matteo Porro, Member, IEEE, Ladislav Andricek, Member, IEEE, Stefan Aschauer, Matthias Bayer,Julian Becker, Luca Bombelli, Andrea Castoldi, Member, IEEE, Giulio De Vita, Inge Diehl, Florian Erdinger,

Stefano Facchinetti, Member, IEEE, Carlo Fiorini, Member, IEEE, Peter Fischer, Thomas Gerlach,Heinz Graafsma, Chiara Guazzoni, Member, IEEE, Karsten Hansen, Senior Member, IEEE, Pradeep Kalavakuru,Helmut Klär, Andreas Kugel, Member, IEEE, Peter Lechner, Martin Lemke, Gerhard Lutz, Massimo Manghisoni,

Davide Mezza, Member, IEEE, Dirk Müntefering, Ullrich Pietsch, Emanuele Quartieri, Michael Randall,Valerio Re, Christian Reckleben, Member, IEEE, Christian Sandow, Jan Soldat, Lothar Strüder,

Janusz Szymanski, Georg Weidenspointner, and Cornelia B. Wunderer

Abstract—We present the development of the DSSC instrument:an ultra-high speed detector system for the new European XFELin Hamburg. The DSSC will be able to record X-ray images with amaximum frame rate of 4.5 MHz. The system is based on a siliconpixel sensor with a DEPFET as a central amplifier structure andhas detection efficiency close to 100% for X-rays from 0.5 keV upto 10 keV. The sensor will have a size of approximately 210 210mm composed of 1024 1024 pixels with hexagonal shape. Twohundred fifty six mixed signal readout ASICs are bump-bondedto the detector. They are designed in 130 nm CMOS technologyand provide full parallel readout. The signals coming from thesensor are processed by an analog filter, immediately digitized by8-bit ADCs and locally stored in an SRAM, which is able to recordat least 640 frames. In order to fit the dynamic range of about

photons of 1 keV per pixel into a reasonable output signalrange, achieving at the same time single 1 keV photon resolution, a

Manuscript received June 15, 2012; revised August 11, 2012; accepted Au-gust 28, 2012. Date of publication October 11, 2012; date of current versionDecember 11, 2012. This work was supported by XFEL GmbH in the Frame-work of the DSSC project.M. Porro, G. De Vita, L. Strüder and G. Weidenspointner are with Max-

Planck Institut fuer extraterrestrische Physik, 85748 Garching, Germany andalso with MPI Halbleiterlabor, 81739 Muenchen, Germany (e-mail: [email protected]).L. Bombelli, A. Castoldi, C. Fiorini, C. Guazzoni, S. Facchinetti and D.

Mezza are with Dipartimento di Elettronica e Informazione, Politecnico diMilano, 20133 Milan, Italy and also with INFN, Sezione di Milano, Milano20090, Italy.L. Andricek is with Max-Planck-Institut fuer Physik, 80805 München, Ger-

many and also with MPI Halbleiterlabor, 81739 München, Germany.M. Bayer, J. Becker, I. Diehl, H. Graafsma, K. Hansen, P. Kalavakuru, H.

Klär, M. Lemke, D.Müntefering,M. Randall, C. Reckleben, J. Szymanski, C. B.Wunderer are with Deutsches Elektronen-Synchrotron DESY, Hamburg 22607,Germany.S. Aschauer, G. Lutz, P. Lechner, C. Sandow are with PNSensor GmbH,

München D-80803, Germany.F. Erdinger, P. Fischer, T. Gerlach, A. Kugel and J. Soldat are with Universität

Heidelberg, Heidelberg 69117, Germany.M. Manghisoni, V. Re and E. Quartieri are with Università di Bergamo,

Bergamo 24129, Italy.U. Pietsch is with Universität Siegen, Siegen D-57068, Germany.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TNS.2012.2217755

non-linear characteristic is required. The proposed DEPFET pro-vides the needed dynamic range compression at the sensor level.The most exciting and challenging property is that the single 1 keVphoton resolution and the high dynamic range are accomplishedwithin the 220 ns frame rate of the system. The key properties andthe main design concepts of the different building blocks of thesystem are discussed. Measurements with the analog front-end ofthe readout ASIC and a standard DEPFET have already shown avery lownoisewhichmakes it possible to achieve the targeted singlephoton resolution for 1 keV photons at 4.5 MHz and also for 0.5keV photons at half of the speed. In the paper the new experimentalresults obtained coupling a single pixel to an 8 8 ASIC prototypeare shown. This 8 8 ASIC comprises the complete readout chainfrom the analog front-end to the ADC and the memory. The char-acterization of a newly fabricated non-linear DEPFET is presentedfor the first time.

Index Terms—DEPFET, DSSC, silicon radiation detectors,X-ray detectors, X-ray free electron lasers.

I. INTRODUCTION

O UR consortium is developing the DSSC (DEPFETSensor with Signal Compression) [1]: a high speed focal

plane detector system for the new European XFEL (X-ray FreeElectron Laser) in Hamburg [2]. In particular the DSSC willbe optimized in order to be used for the small quantum systemexperiments [3], for the spectroscopy and coherent scatteringexperiments [4] and for the coherent diffraction imaging exper-iments on single particles, clusters and biomolecules [5]. Ourinstrument will be able to record X-ray images with a max-imum frame rate of 4.5 MHz and to achieve a high dynamicrange. This will allow one to cope with the very demandingpulse time structure of the European XFEL. The machinewill provide macro-bunches with a repetition rate of 10 Hz.Every macro-bunch is composed of X-ray pulses with atemporal distance of 220 ns (Fig. 1). Our detector will be ableto acquire images every 220 ns providing a frame rate of 4.5MHz and high dynamic range at the same time. The number

0018-9499/$31.00 © 2012 IEEE

3340 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 59, NO. 6, DECEMBER 2012

Fig. 1. X-ray bunch structure at the European XFEL. The XFEL machine gen-erates macro-bunches with a repetition rate of 10 Hz. Every macro-bunch iscomposed of a train of 2700 X-ray pulses with a temporal distance of 220 ns.TheDSSCwill be able to acquire an image every 220 ns and to store the acquireddata in the focal plane. During the 99.4 ms time gap between twomacro-bunchesthe data are sent off the focal plane.

TABLE ISUMMARY OF THE DSSC MAIN PROPERTIES. SOME OF THE PARAMETERSDEPEND ON THE ENERGY AND ON THE DIFFERENT OPERATING MODESOFFERED BY THE DSSC. THEY ARE SPECIFIED IN MORE DETAILS IN THE

TABLES OF SECTION V

of stored frames per macro-bunch will be at least 640 with thepossibility to discard bad frames thanks to an external trigger.The key properties of the system are summarized in Table I.Some of the reported parameters depend on the different op-erating conditions offered by the DSSC and are discussed inmore details in Section V.The system is based on a pixelated silicon sensor with a

DEPFET [6], [7] as a central amplifier structure. The sensorwill have the following key properties: The total size will beapproximately 21 21 cm composed of 1024 1024 pixelsof hexagonal shape. The pixel array will be subdivided in 16ladders. Every ladder comprises 2 monolithic sensors with128 256 pixels each. The ladders will be geometricallyarranged such that a central hole is left to let the unscatteredphotons go through (Fig. 2).The insensitive space in the focal plane is about 15% with

the present mechanical design. A simplified block diagram ofthe system is shown in Fig. 3.The concept of our system is based on the following three key

features:

Fig. 2. 3-D view of the focal-plane comprising 4 quadrants. Each quadrant iscomposed of 4 ladders and 8 monolithic sensors of the size of 128 256 pixelseach. A hole is left in the middle in order to let the unscattered beam go through.

Fig. 3. Simplified block diagram of our detector concept.

• the intrinsic low noise provided by the DEPFET device• the signal compression at the sensor level, provided by thenew DEPFET topology

• the full parallel readout with immediate digitization of thesignals in the focal plane

Every detector ladder is bump-bonded to mixed signalreadout ASICs. The ASICs are designed in 130nm CMOStechnology and provide full parallel readout of the DEPFETpixels. The signals coming from the detector, once processedby an analog filter, are digitized by a series of 8 bit (or 9 bit forframe rates MHz) single-slope ADCs and locally storedin a custom designed memory also integrated in the ASICs.During the 99 ms time gap of cooling phase of the accelerator,the digital data are sent off the focal plane to a DAQ electronicsthat acts as an interface to the back-end of the whole instrument.The most exciting and challenging property is the 220 ns

frame rate of the system combined with low-energy singlephoton resolution. This goes beyond all existing instrumentsand requires the development of new concepts and technolo-gies.The pixel sensor has been designed so as to combine high en-

ergy resolution at low signal charge with high dynamic range:

PORRO et al.: DEVELOPMENT OF THE DEPFET SENSOR WITH SIGNAL COMPRESSION 3341

special care has been taken in order to achieve single photon de-tection also in the low energy range down to 0.5 keV (see Sec-tion V). This has been motivated by the desire to be sensitiveto single low energy photons and at the same time to measureat other positions of the detector signals corresponding to up to

photons of 1 keV per pixel. In order to fit this dynamic rangeinto a reasonable output signal range, achieving at the same timesingle photon resolution, a strongly non-linear characteristic isrequired. The new proposed DEPFET provides the required dy-namic range compression at the sensor level.After two years of development we have experimentally

proven the non-linear DEPFET compression principle withmeasurements on first sensor device prototypes. We haverealized a first mini-matrix readout ASIC comprising all theblocks of the readout chain. This has been successfully tested.Prototypes and designs of the ladder module electronics andmechanics are also available.The above mentioned achievements are summarized in this

paper. At the end an estimation of the system properties of thesystem is presented. The estimate is based on the present statusof the development and on the first experimental results. The re-ported data are obtained with the existing prototypes and matchvery well our design goals at this phase of the development. Theestimated performance figures in terms of dynamic range andfalse detection probability satisfy the requirements of the ex-periments at the European XFEL and have been discussed andapproved within the DSSC Detector Integration Group of theEuropean XFEL [8]. Better values are anyway expected for thefinal implementation of the instrument.

II. SENSOR

The DEPFET [6], [7] is a Field Effect Transistor located onone surface of a silicon wafer. A large area diode is on the oppo-site surface of the wafer. The n-type bulk is fully depleted withthe help of a sideward located doped clear contact. Suit-able doping and choice of bias voltages create a potential max-imum right below the channel of the transistor: the internal gate.Electrons generated by radiation are collected there. They createmirror charges in the channel, thereby increasing channel con-ductivity. For fixed source and external gate voltages the tran-sistor current is increased. Applying a sufficiently strong posi-tive voltage pulse to the clear (bulk) contact removes all chargefrom the internal gate. The charge stored in the internal gate canbe measured by the current difference before and after clearingof the internal gate. The DEPFET is a natural building block fora pixel detector as it combines the properties of detector, am-plifier and storage cell in a simple structure. The high repetitionrate foreseen for XFEL requires parallel readout of all pixels.Therefore an individual readout channel is required for eachpixel and all pixels have to be powered during the X-ray macro-bunch train. A new type of DEPFET solves the challenge of pro-viding excellent charge resolution for low signals as required forsingle photon detection with very large charge handling capacityfor pixels containing the overlap of very many photons. This isaccomplished by providing a strongly non-linear current-chargecharacteristic [1], [9]. The basic concept is shown in Fig. 4.The internal gate extends into the region below the large area

source. Small signal charges accumulate below the channel

Fig. 4. DSSC DEPFET Concept. The first signal electrons are collected in thepotential well exactly below the gate due to its most positive potential. If thatarea is filled up with electrons the next disk—extending below the source and thegate—collects electrons and so forth. Only the fraction of the additional chargethat arrives below the internal gate is effective in modulating the transistor cur-rent. This leads to the non-linear amplification behavior of the DEPFET pixel.

only, being fully effective in steering the transistor current.Large signal charges spill over into the region below the sourceand correspondingly are less effective in steering the transistorcurrent. To increase this signal compression gradually with theamount of signal charges, the overflow region of the internalgate is implemented by a triple staggered concentration of thedeep n-doping. The gradient in the deep n-concentration alsogenerates an electric field facilitating a short charge collectiontime and a fast clear process.Due to the requirement of fast signal charge collection the

pixel has the shape of a regular hexagon with a side length of136 m (Fig. 5). Compared to a square pixel of similar area,the hexagon has, on average, a shorter distance from the centreto the edge, resulting in a shorter charge collection time. Inaddition the hexagonal shape minimizes the fraction of splitevents, i.e., absorption events close to the pixel border resultingin charge sharing between two or more neighboring pixels. Thehexagonal mesh results in different pixel pitches in x (204 m)and y (236 m). The central part of the pixel is filled by theDEPFET with the large area overflow region underneath thesource. The DEPFET is enclosed by two drift rings that are bi-ased increasingly negative from the inner to the outer ring anddefine a funnel-like potential distribution guiding signal elec-trons towards the central DEPFET. The hexagonal shape of thedrift rings provides then a more homogeneous drift field with re-spect to a conventional squared pixel and is more effective in fo-cusing the collected charge into the internal gate of the DEPFETlocated in the center of the cell (Fig. 5).The validity of the new detector concept has been experi-

mentally verified on a 7-cell cluster of hexagonal non-linearDEPFET prototypes [10]. They do not offer the three dose-stag-gered deep n-implantations that define radially different over-flow regions of the internal gate, thus smoothing out the non-linear gain characteristics. In this first prototype there is only


Fig. 5. Geometry and simplified layout of a DSSC pixel. The DEFFET is lo-cated in the middle of the pixel cell and it is surrounded by two drift rings.

one deep-n profile. Therefore the non-linear gain curve consistsof two linear regions with different gain values.The first 7-cell prototype has been mounted and bonded on

ceramic carriers and tested at room temperature on a single pixellevel using the standard DEPFET test setup of theMPI semicon-ductor lab, realized with discrete electronics components. TheDEPFET is configured for drain current readout using a cur-rent-to-voltage converter. The output voltage level is directlysampled by an ADC. AC signals for clear and clear gate are ap-plied via programmable SWITCHER ICs [11].In a first test, the sensor was irradiated from the back side

with the X-rays from a radioactive Fe source (5.9 keV and6.5 keV). As these energies fall into the linear gain region, thesensor works in a regular spectroscopy mode. The electronicnoise extracted from the width of the noise peak is approxi-mately 10 electrons ENC corresponding to 150 eV FWHM ofthe Mn-K line (5.9 keV) [10]. This performance is worse thanthe values quoted for spectroscopy type DEPFETs in the liter-ature. The difference is due to the long signal integration timeof several milli-seconds and the direct sampling of the signallevels without filtering. In any case the DEPFET noise contri-bution will not be the limiting factor of the DSSC system resolu-tion. The obtained spectrum has been used to calibrate a pulseddiode laser in terms of signal charges per laser pulse. Applyinga series of calibrated laser pulses the non-linear gain curve hasbeen acquired (Fig. 6). As expected the linear region extends toa large integrated energy of roughly 100 keV. For comparisonwith the final DSSC device we expect the linear region to extendup to about 10 keV. The gain of the DEPFET in the linear re-gion, defined as , is about 600 pA per signalelectron. In the compression region the is reduced by a factorof 17.5.The measurement shown here is the very first proof of prin-

ciple of a new detector concept.The production of the 128 256 full format sensor, already

implemented in the final technology, i.e., providing the desiredshape of the non-linear response, has started in June 2011. Fig. 7shows a simulation of the characteristic of the final DEPFET.

Fig. 6. Measured non-linear curve of a DSSCDEPFET prototype using a seriesof calibrated laser pulses. The symbols in the curve represent the laser pulses.

This curve will be used to estimate the expected system param-eters of the DSSC, described in Section V.Fig. 8 shows the simulation of the charge collection time for

the final DEPFET topology. In the simulation the charge is gen-erated at the edge of the pixel, i.e., at a distance of 115 m fromthe center. In this worst case and at 300 K, about 60 ns are suffi-cient to collect into the internal gate 99% of the injected charge.Even faster collection times are expected for lower temperature.In the simulation, given the amount of generated electrons, allthe charge ends in the inner region of the internal gate, locatedjust below the DEPFET conductive channel (solid blue curve).The charge is generated at a depth of 175 m and it flows to thecenter of the pixel, crossing the first and second overflow re-gions of the internal gate (dashed green and dashed and dottedred curves).In the next sections a short description of the electronics

and of the module construction needed to embed the DEPFETsensor in a working system is given. We start with the descrip-tion of one ladder module, which is the basic unit of the DSSCinstrument.

III. MODULE CONSTRUCTION AND ELECTRONICS

As shown in Fig. 2, every quadrant comprises four laddermodules with the focal-plane electronics of 512 512 pixels.Fig. 9 shows a sketch of one ladder module construction [12].Each module consists of a main board with two sensor-readoutchip layer stacks, four regulator boards and a single I/O board.At the bottom there are two DEPFET sensors. They are bumpbonded to 16 readout ASICs (8 per sensor). The sensors are alsowire bonded to the main board. In this way, all the power andsignal lines go to the ASICs through the DEPFET sensor chips.The readout ASICs are bumped by the commercially avail-

able IBM bumping process C4 providing bumps with mdiameter. The bump bonding will be done on a conventionalflip-chip bonder adapted to the special requirements due to thehighly sensitive back side of the sensors. The sensor acts as asubstrate for the flip-chip procedure and has to have solder wet-table landing pads (under bump metallization) for the bumps


Fig. 7. Simulated characteristic of the final DSSC DEPFET. The bottom pic-ture shows a zoom of the linear region, which extends up to about 10 keV. Theequivalent bin sizes, expressed in current, for 1 keV and 3 keV photons areshown. As explained in Section V, they are used to estimate the achievable dy-namic range. The specific case of 8 bits and 1 bin/ph is shown in the picture.

on the ASICs side. This under bump metallization is effectivelya third metal layer on the sensor. The additional steps have tobe integrated in the process flow of the DEPFET production;they must not degrade the properties of the sensor and shouldbe compatible with double sided processed sensor wafers witha sensitive entrance window for low energy photons.The ASICs are separated from the main board by a silicon

heat spreader.The task of the main board is the distribution of the power

and of the signals. Then it accommodates five board-to-boardconnectors for the I/O board and the four regulator boards.

Fig. 8. Simulation of the charge collection for the final DSSC DEPFET at 300K. The charge is generated at the edge of the pixel at a depth of 175 m. At theend, all the electrons are collected into the inner region of the internal gate (solidblue curve). Part of the charge transits through the first and second overflowregions of the internal gate (dashed and dashed and dotted curves). About 60 nsare sufficient to collect the whole charge. Faster collection times are expectedat lower temperature.

Fig. 9. Drawing of the ladder module. It comprises 2 sensors, 16 readoutASICs, one main board, 4 regulator boards, 1 I/O board and an interconnectionboard. The Al box surrounding the module is not shown.

One of the tasks of the regulator boards is to provide thepower supply regulation for the readout ASICs. In order to min-imize the power consumption, the DEPFET sensors and theASICs are active only during the X-ray macro-bunch train pe-riods. This means that the sensors and the ASICs are powereddown during readout, i.e., in the 99.4 ms gap of the XFEL ma-chine (see Fig. 1). The power supply is provided to the ASICsthrough a set of voltage regulators with large capacitor banks.The first prototypes of the board have proven that the regulatorsare able to provide a constant voltage output of 1.4 V at a currentrequest of 2.9 A, which is required by the readout ASICs, for thewhole 600 s duration of the macro-bunch train. In addition theregulator boards have to provide the fast clear pulses that are


needed to remove the signal charge from the internal gate of theDEPFETs after every single laser shot. For this reason a gatedriver stage is mounted on one side of the regulator board asa hybrid device. The two associated banks of capacitors are lo-cated on the top and bottom side to provide the charge needed topush up and pull down the DEPFETs clear electrodes with a rep-etition rate of 4.5 MHz during the 600 s of the macro-bunch.In order to ensure a complete removal of the charge from theinternal gate of the DEPFET within the required 60 ns (see Sec-tion V), the clear pulse voltage-swing is about 20 V. The timingand control signals for the generation of the clear pulses are pro-vided by the I/O board. The signals are transmitted to the gatedrivers of the four regulator boards through an interconnectionboard on top (see Fig. 9).Besides generating the timing signals for the regulator boards,

the I/O board accomplishes several tasks [13]. The central el-ement of this board is a Xilinx Spartan-6 FPGA device. Themain task is to collect the data coming from the 16 readoutASICs of one ladder module and to concentrate them into se-rial high-speed data streams, which are then passed to a secondlevel of the DAQ outside vacuum. The intended readout rateper ASIC is 400 Mb/s and is sufficient to read more than the640 frames that can be stored in the present implementation ofthe SRAM (see Section IV). At last the I/O board carries theswitching circuity used to power-on and power-off the sensorchips, thus realizing the power cycling for the DEPFETs.Taking into account the power cycling strategy the total mean

power consumption of the camera head inside vacuum is about400 W. This comprises the power consumption of the sensorsand of the ASICs as well as the power consumption of allthe boards. The mechanical construction of the ladder moduleis designed in order to maximize the top-bottom thermalthroughput though cooling paths via an aluminum ladder boxwhich surrounds the whole ladder module. Thermal simulationshave shown that it is possible to keep the temperature variationalong one DEPFET sensor below the desired value of 5 C.

IV. READOUT ASIC

The DSSC ASIC [14] will be a bump bondable pixel chipwith 64 64 channels suited for the low noise readout and dig-itization of the DEPFET current signals at a rate of up to 4.5MHz (allowing also slower operation). A total of 256 chips willbe used to readout the full 1Mpixel camera. As shown schemati-cally in Fig. 10, each pixel of 206 236 m contains the blocksdescribed below.• A cascode to keep the DEPFET drain at constant potential.This is needed because of the relatively low output resis-tance of the DEPFET.

• A circuit for theDEPFET bias current cancellation [15],[16], which is fixed by the DEPFET Gate-Source voltageandwhich can vary from pixel to pixel. This circuit is basedon a 5-bit DAC (with pixel-wise settings) and on an addi-tional continuous regulation which is operated in a closedloop before the arrival of the X-ray macro bunch. The sameamplifier used for the filter (see next point) is operated, inthis phase, as an error amplifier.

Fig. 10. Simplified diagram of one pixel of the DSSC pixel ASIC.

• A filter stage implementing a trapezoidal shaping withvariable gain [15], [16]. The filter integrates the drain cur-rent of the DEPFET before and after the arrival of a singleX-ray pulse and provides at the output the difference be-tween the two integrations, thus realizing a trapezoidalweighting function. Thanks to the fact that the feedbackcapacitance can be flipped, the DEPFET current integra-tion phase (baseline readout) and DEPFET current de-inte-gration phase (baseline+signal readout), needed to obtainthe trapezoidal filter, are accomplished by a single stage.The gain of the filter can be changed by selecting differentvalues of the feedback capacitor. This is required by theneed to adapt the overall gain to the photon energy, on oneside, and to the different possible frame-rates, on the otherside. In fact, with the trapezoidal filter, the gain of the stagedepends also on the time duration of the integration of theDEPFET current, i.e., on the operating speed of the circuit.In the available prototype of the ASIC four different valuesof the feedback capacitor are implemented. A wider selec-tion will be introduced in future versions of the ASIC.

• An injection circuit [17], [18] which pulses a known pro-grammable current into the input node. This is used forfunctionality check and calibration purposes. The currentcan be adjusted with a single global 8-bit DAC.

• A pair of sample and hold capacitors for double buffering• A Wilkinson type (single slope) ADC [19], [20] with8 bit resolution: the S&H capacitor is charged with aconstant current source. The ramp is started with a precisestrobe, distributed to all pixels as a differential signal oncoplanar wave guides. Once the reference potential isreached, a comparator latches 8 gray coded time stampswhich are also distributed differentially. A fast 800 MHzexternal clock is used to toggle the counter on both edges,giving a time resolution of 625 ps. The value of the currentsource discharging the S&H capacitor is programmablepixel-wise, in order to fine tune the gain of the individualpixel in small steps whose amplitude is about 5% of thenominal value. A programmable time delay on the rampsignal allows to individually adjust the ADC offset witha granularity equal to 1/10 of the bin size. This pixel bypixel adjustment capability is essential for the calibrationof the system [21]. When operating at a speed MHz,a 9th bit can be obtained by toggling a flip-flop internally.


• A temperature and supply voltage insensitive bandgapreference in order to bias the circuits.

• A large SRAM to store at least 640 words of 9-bit duringthe X-ray macro-bunch. The RAM is organized such thatindividual words can be overwritten to allow triggeredoperation of the chip (where an “abort” signal rejectsrecorded events). A compact serial readout is included.The control overhead is minimized as much as possibleto achieve high density. The RAM occupies of thepixel. In the latest layout of the ASIC, the memory canstore 640 frames. Some free area is left in order to increasethe memory size in the next ASIC prototype. Nevertheless640 frames are already enough to store all the pulses of onemacro-bunch, when the system is operated at 0.9 MHz. Inaddition, even when operating at higher frame rate, not allthe X-ray pulses will generate useful information.

• Further auxiliary blocks, like static control registers, alarge switchable decoupling capacitor, monitoring linesand a debug readout circuit.

A global logic (not shown in Fig. 10) controls the data takingsequence during the X-ray pulse train and the serial readout ofthe memory between two macro-bunches.The prototypes of all pixel circuit blocks have been de-

signed and characterized successfully. Signals from radioactivesources and laser pulses have been measured with standardDEPFETs connected to single channel prototypes. Weightingfunctions are as expected [15]. The noise figures measuredcoupling the analog front-end with standard DEPFETs withan external 14-bit ADC are very close to simulations andcalculations. In fact an Equivalent Noise Charge (ENC) of 13el. r.m.s. has been measured with an operating frequency of 1MHz, while 48 el. r.m.s. have been obtained at 5 MHz [15].The measured Differential Non Linearity of the ADC, which

is essential to discriminate single and multiple photon signals,is LSB, with a standard deviation smaller than 0.1 LSB.The time jitter of the comparator for small signal amplitudes is

ps. Even if we expect to reduce this value in future imple-mentations, -at present- the upper limit of 70 ps has been usedin order to calculate the expected performance of the system,reported in Section V.All available blocks have then been successfully merged into

a first 8 8 mini matrix pixel chip (Fig. 11) to demonstrate thateverything can be accommodated in the available pixel area of206 236 m , that routing of power, control and readout ispossible and that the interfaces between the individual blockswork as expected. This mini-matrix chip is fully functional andallows the measurement of the DEPFET signals using the ADCwith local data storage, so that a realistic XFEL type operationis demonstrated. Overall, we have implemented all the requiredfunctionalities in the available space within the available powerbudget ( mW per pixel during operation). Performance ofthe individual blocks in the first prototype versions is very closeto our requirements that should be reached with the new de-signs, which are currently under way or being tested. In partic-ular noise performance of the front-end with standard DEPFETsmatches expectations very well.The properties of the full readout chain, comprising also the

integrated 8-bit ADC, are being investigated for the first time

Fig. 11. Layout of the 8 8 mini-matrix ASIC. From the layout of one pixel(on the right) it is evident that some space is left to increase the size of thememory. At the moment 640 frames per macro-bunch can be stored.

Fig. 12. Fe spectrum measured with a standard DEPFET and the full ASICchannel readout chain, including the on-chip 8-bit ADC. The width of the noisepeak is el. r.m.s. The statistics of this spectrum are low because of the weaksource used (the above histogram refers to a measurement lasting two hours. TheDEPFET pixel used has an active area of only 75 75 m so that many splitevents degrade the spectrum).

connecting a single channel of the mini-matrix to a standardDEPFET. A preliminary noise measurement, with a Fe sourceas gain calibration, has been performed (Fig. 12). A value of

el. r.m.s. with a DEPFET current integration time of 250 nshas been obtained. This value matches very well our goals andpredictions and is almost identical to the value obtained with thefront-end alone read-out by an external ADC.The data obtained with the experimental characterization of

the prototypes of the readout ASIC have been used, togetherwith the simulations on the final non-linear DEPFET, in orderto estimate the performance figures of the DSSC system, as de-scribed in the following section.

V. ESTIMATED PERFORMANCE FIGURES

The DSSC is designed to cover a large variety of operatingconditions, thanks to a set of adjustable parameters of thereadout chain. The instrument properties can be tuned ac-cording to the specific experiments. The main available settingsare provided by the readout electronics. They are:• The analog-filter gain from the DEPFET output to the inputof the on-chip ADC. The gain depends on four selectable


Fig. 13. Timing diagram of one readout cycle of the DSSC for a frame rateof 4.5 MHz. The trapezoidal weighting function implemented by the filer isshown on top of the diagram. The shaping time is defined as the time neededto make an integration of the DEPFET drain current. A complete readout cyclecomprises two integrations, because both the baseline and the baseline+signalmust be read-out.

feedback capacitors and on the chosen shaping time of thefilter itself.

• The shaping time of the filter. We define as the shapingtime the time needed for one DEPFET signal currentintegration (see Fig. 13). This can be changed, not only toinfluence the gain of the filter, but also to adjust the noiseperformance according to the different operating speeds ofthe system. In principle slower frame rates allow longershaping times and better noise performance.

• The number of bits of the ADC. 8 bits are available for allframe rates, while 9 bits can be used for a frame rateMHz.

All these settings act in a linear way on the system properties,while the non-linear response of the instrument is given by theintrinsic DSSC-DEPFET characteristic, which cannot be tuned(after sensor production). It must be noticed that the settingsare not independent from each other. For example a change inthe analog-filter integration time is automatically reflected in amodification of the system gain or a 9-bit operation requires aframe rate MHz. The choice of one parameter can influ-ence more than one performance figure of the system. Tuninge.g. the integration time of the filter, the gain, the maximum op-erating speed and the noise properties are affected at the sametime.In order to accept input photons of different energies, pre-

serving the dynamic range, a coarse gain adjustment is needed.As already explained, this is accomplished thanks to 4 (in thepresent version of the ASIC) selectable feedback capacitorsplaced in the analog-front-end and thanks to a proper choice ofthe filter shaping time. The capacitors must be sized in order toprovide shaping times suitable to cope with the foreseen framerate of the XFEL machine. Given the area constraints and theneed to limit the complexity of the ASIC, it is not possible to

find a specific set of parameters in order to optimize the readoutchain for every arbitrary frame rate. So, even if the DSSC canoperate at any speed MHz, we have designed the systemfocusing on the following frame rates: 4.5 MHz, 2.25 MHz and0.9 MHz.Given the flexibility offered by the DSSC, the data given here

cover the most probable but not all the possible operating con-ditions of our instrument. The estimates are obtained from thepresent status of our development. In order to calculate the dif-ferent performance figures we have used the measured valuesfor the already existing blocks of the system, e.g., the measure-ments on the existing ASIC prototype stages, and the latest sim-ulations for the parts still in production like the final non-linearDEPFET. Even if the results of our calculations are already sat-isfactory, we know that the system performance can be opti-mized with some adjustments of the parameters of the ASIC. Infact, the first prototypes of the ASIC blocks were developed andrealized when the final non-linear DEPFET was still in the de-sign phase. Optimizations dictated by the simulation of the finalDEPFET topology will be implemented in the next ASIC proto-type. We expect that the presented results will be improved forthe final version of the instrument.At first we have to make some assumptions. We expect that

120 ns in total are needed in order to collect the charge intothe internal gate of the pixel and to remove it after the signalreadout (see Section II and [9]). This leaves a maximum filterintegration time of 50 ns (see Fig. 13), 161 ns and 494 ns for theframe rates of 4.5 MHz, 2.25 MHz and 0.9 MHz respectively.Given a specific frame rate the maximum possible integrationtime should be used in order to reduce the noise. Neverthelessa shorter integration time may be chosen in order to adapt thegain in combination with the available four selectable feedbackcapacitors, as shown for example by the (blue) dashed curve inFig. 14.For the noise of the DEPFET and the analog front-end we

consider the value of 48 electrons r.m.s., measured at 4.5 MHzwith a standard DEPFET characterized by a gain of 350pA/el. The noise value has been scaled according to the foreseen

pA/el. of the final DSSC-DEPFET.

A. Maximum Dynamic Range With Single-Photon Detection

In this section we present the performance figures of thesystem, under the condition that the maximum possible dy-namic range compatible with the single photon detection isselected. It is worth reminding that the achievable dynamicrange, expressed in photons, of the DSSC system depends onthe following factors:• The shape of the DEPFET non-linear characteristic• The number of bits of the ADC• The number of bins of the ADC associated to the signalproduced by the first collected photon

• The photon energy.Once the photon energy is fixed, we take the simulated DSSC-

DEPFET characteristic and we estimate the drain current signalproduced by the first photon collected into the internal gate.Then a suitable combination of gain settings (filter feedback ca-pacitance and shaping time) is chosen in order to assign one ortwo bins of the ADC to the signal produced by the first photon.


Fig. 14. Schematic representation of the association mechanism between photons and ADC bins. The first collected photon in the DEPFET generates a currentstep. This is integrated on the feedback capacitor of the filter for a definite amount of time. The ideal case is to integrate the current signal for the maximum timeavailable for the selected readout speed (about 60 ns at 4.5 MHz, 160 ns for 2.25 MHz and 495 ns for 0.9 MHz). Once the current integration is completed theoutput of the filter, i.e., the input of the ADC, must have an amplitude exactly equal to a multiple number of ADC bins. In order to have single photon detectioncapability it is necessary to attribute at least one ADC bin to the first collected photon. For every operating speed and photon energy a suitable feedback capacitorwould be needed. This is of course unrealistic and it is not always possible to have the optimum gain setting. The (red) solid lines on the graph at the right of thepicture represent three ideal gain settings for the same photon energy: 1 bin associated to the first photon at 4.5 MHz, two bins associated to the first photon at 4.5MHz and 1 bin associated to the first photon at 2.25 MHz. In all these cases the whole available time is used to integrate the signal current. The (blue) dashed linerepresents the non-ideal case in which the gain is too high in order to associate one bin to the first collected photon exploiting the whole available readout time.A signal current integration time shorter than the available one must be used, thus increasing the readout noise of the system. The (green) dotted and dashed linerepresents the non-ideal case in which the gain setting is too low in order to achieve in the available time an amplitude equal to the first bin of the ADC. This meansthat it is not possible to have single photon detection capability with this speed setting, but it is necessary to use a lower frame rate.

This means that the current signal produced by the DEPFETmust be transformed by the filter stage into a voltage signal atthe input of the ADC. This voltage signal must have an ampli-tude that is equal to a specific number of bins (e.g., 1 or 2) ofthe input dynamic range of the ADC. This is schematically de-picted in Fig. 14.The achievable dynamic range is independent of the frame

rate. Nevertheless, in order to operate at all the speeds, weneed—for every energy of interest—a suitable gain setting inorder to establish the correct correspondence between DEPFETsignal current and ADC input. This will be achieved in the finalversion of the DSSC, but at the moment not all the requiredgain settings are available. For example, even with the min-imum available feedback capacitor (which provides maximumamplification) an integration time longer than 50 ns would berequired in order to have a gain high enough to assign the signalproduced by the first collected 0.5 keV photon to the first bin ofthe ADC (see the green dotted and dashed curve of Fig. 14). Forthis reason, with photons of 0.5 keV, the 4.5 MHz operation isnot available if single photon resolution is required. This is nota principle limitation and can be overcome by implementing ahigher gain in the filter stage. In this work we will report onlythe data regarding the already available operating parameters.

TABLE IIMAXIMUM ACHIEVABLE INPUT DYNAMIC RANGE IN CASE OF SINGLE PHOTONDETECTION CAPABILITY. THE DYNAMIC RANGE IS EXPRESSED IN NUMBER OFPHOTONS. (*) FOR THESE ENTRIES THE DYNAMIC RANGE IS LIMITED BY THE

CHARGE HANDLING CAPACITY OF THE DEPFET

While assigning one bin to the first photon (i.e., one bin foreach photon falling into the linear region of the DEPFET re-sponse) is mandatory in order to achieve single photon detec-tion, assigning two bins to the first photon is beneficial in orderto decrease the quantization noise even if this reduces the avail-able dynamic range. Our criterion is to choose the number ofbins to assign to the photons in the linear region in order tokeep the quantization noise always smaller than one half of thePoisson noise of the photon generation process. From our calcu-lations we concluded that for photons of 12 keV it is necessary


TABLE IIITOTAL NOISE EXPRESSED IN ELECTRONS R.M.S. IN CASE OF MAXIMUM DYNAMIC RANGE WITH SINGLE PHOTON DETECTION CAPABILITY. THIS NOISE

INCLUDES THE DEPFET, THE ANALOG FRONT-END AND THE ADC JITTER NOISE. THE ASSOCIATED DYNAMIC RANGE IS SHOWN IN TABLE II

to assign 2 bins to the first collected photon for both the 8 and the9 bit operation. All the other considered energies require onlyone bin per photon. A detailed study of the quantization noisefor the DSSC case can be found in [1].As an example, let us assume that we attribute one bin to the

signal produced by the first photon. In order to calculate theachievable dynamic range we have to take the amplitude of thecurrent signal generated by the this first photon collected intothe internal gate of the DEPFET. This value, which representsthe equivalent ADC bin size expressed in current, must bemulti-plied by the number of bins of the ADC, e.g., in case ofan 8-bit ADC. In this waywe get the DEPFET current swing thatcan be covered by the ADC. Looking at the non-linear DEPFETcharacteristic we can determine how many deposited electronscorrespond to this current swing. From the number of electrons,the number of the acceptable incoming photons can be derived.For example the first 1 keV photon (278 el. deposited) will gen-erate a signal current of about nA (seeFig. 7). With 8 bits the acceptable current swing is about 37 A,while in the 9 bit case it is about 74 A. The dynamic range inelectrons would be at 8-bit and at 9 bits.These values approximately correspond to 2370 and 12080 pho-tons respectively.The gain of the system is set in order to attribute a defined

number of bins (e.g., 1) to the first collected photon. The equiv-alent ADC bin size expressed in current is a function of thephoton energy; the higher that energy, the more charge is de-posited by the first collected photon, and the larger the resultingcurrent step. So, given the same number of bits, the currentswing covered by the ADC increases with the photon energy.Because of the non-linearity of the DEPFET characteristic, thedeposited charge increases more than linearly, since the numberof electrons falling into the low-gain region of the non-linear re-sponse increases (see Fig. 7(a)). Making the conversion of theinput dynamic range from electrons to photons of a defined en-ergy, it is evident that the input dynamic range expressed in pho-tons increases with the energy.For a 3 keV photon (833 electrons deposited) the equivalent

bin size in current is about 433 nA (see Fig. 7) and the covereddynamic range in current is 110 A in case of 8 bits. This turnsout into an input dynamic range of 8318 photons, to be com-pared with the 2370 photons given for the 1 keV energy.The above arguments are valid if the dynamic range of the

system is limited by the number of bits of the ADC and not bythe charge handling capacity of the DEPFET pixels. Neverthe-less, in our system, the limits given by the DEPFET are visibleonly in the case of photons of energies keV using the ADCin the 9-bit mode.

The dynamic ranges calculated for different energies in the 8and 9 bit cases are reported in Table II. As mentioned before, thevalues in the table are obtained assigning one ADC bin to thesignal produced by the first incoming photons of all the energies,except for the case of 12 keV. For this energy two bins have beenassigned to the first photon.Once the speed, the photon energy and the number of bits are

chosen, the system noise (Table III) is calculated.In the DSSC system the noise is signal dependent [1].

Table III refers to the noise of the linear region of the DEPFETresponse, i.e., the noise affecting the signals generated by thefirst few photons collected into the pixel. This noise, assumedto be Gaussian, determines the single photon detection capa-bility of our instrument [1]. The ENC values of Table III aremainly given by three components: the white thermal noise ofthe DEPFET, the white thermal noise of the filter stage and thenoise due to the time jitter of the voltage-to-time conversion ofthe ADC.The DEPFET and the filter noise contributions decrease as

the shaping time gets longer. The ideal case would be to inte-grate the current signal coming from the pixel for the maximumtime available for the selected frame rate. This is at the momentnot achievable because the filter stage does not have enoughgain settings. In addition, unlike the white thermal noise of theDEPFET and of the filter, the noise produced by the ADC jitterdoes not scale with the readout speed. Therefore, when the jitternoise becomes dominant, it is not beneficial anymore to increasethe shaping time of the filter and different frame rates are char-acterized by the same noise figures. The value of the jitter noisehas been extracted by measurements on the first prototype of theADC and corresponds to approximately V r.m.s. atthe input of the ADC (the output of the filter). Improved valuesare expected in the future implementations, but in the currentversion the ADC jitter noise is the dominant part of the ENCfor almost all the operating modes. This fact is also the maincause of the increase of the ENC with increasing photon energy.The increase of the energy, in fact, corresponds to a reduction ofthe filter gain, which transfers the ADC jitter noise to the inputof the system. The reduction of the gain is necessary to main-tain the correspondence between the signal generated by the firstcollected photon and the first ADC bin. The 6 keV and 12 keVcases have the same ENC. This is consistent with the fact that,for these two energies, the same gain setting is used: for 12 keVtwo ADC bins are associated with the first incoming photon.The ADC jitter noise is not completely dominant only for

some frame rates in case of 0.5 keV and 1 keV photon ener-gies with 8 bit resolution (see Table IV). Under this conditionthe total noise scales with the frame rate. An ENC reduction,


TABLE IVFILTER SETTINGS AND NOISE COMPONENTS FOR 0.5 KEV AND 1 KEV AT DIFFERENT FRAME RATES IN THE 8-BIT MODE

TABLE VPROBABILITY TO ERRONEOUSLY DETECT ONE PHOTON WHEN NO SIGNAL HAS BEEN COLLECTED. THE PROBABILITIES ARE CALCULATED USING

THE NOISE VALUES OF TABLE III

TABLE VIDYNAMIC RANGE FOR THREE DIFFERENT GAINS OF THE SYSTEM. WITH THESEGAINS 0.5, 1 OR 2 BINS ARE ATTRIBUTED TO THE FIRST INCOMING PHOTON. IF0.5 BINS/PH. ARE SELECTED, THE SYSTEM CANNOT DETECT SINGLE PHOTONS

ANYMORE

for example, can be appreciated for the 1 keV case with 8 bitsmoving from 4.5 MHz to 2.2 MHz. A further decrease of thenoise is not achievable going further down to 0.9 MHz. In factfor MHz the ADC jitter noise starts to become the majorcomponent of the ENC. In addition, the 2.2 MHz and 0.9 MHzmodes use the same shaping time because of the limited numberof gain settings of the filter. Therefore, in the 0.9 MHz case, it isnot possible to exploit the whole time available for the readout(a similar situation is depicted for the 4.5 MHz case by the bluedashed curve in Fig. 14).In order to have an estimate of the single photon detection ca-

pability, we have calculated -from the known noise figures- theprobability of erroneously detecting one photon whenno signal has been collected. The results are reported in Table V.Using 8 bits, the probability to have a false detection with 1 keVphotons is about operating at the maximum framerate of 4.5 MHz. This probability decreases to re-ducing the operating speed to 0.9 MHz. Despite the fact that theabsolute value of the noise increases with the energy, the signalto noise ratio slightly decreases and therefore also getssmaller as the photon energy gets higher.

B. Improved Single Photon Resolution With Limited DynamicRange

An increase of the gain of the system reduces the availabledynamic range but reduces at the same time the probability. We have taken into account the energies 0.5, 1 and 3 keV.

The gains have been chosen in such a way to attribute 2 bins tothe first collected photon. The dynamic range and the

TABLE VIIPROBABILITY OF FALSE DETECTION. THIS IS EXPRESSED AS IN

CASE OF 1 BIN/PH. AND 2 BINS/PH. FOR THE CASE OF 0.5 BINS/PH. THEIS REPORTED. ASSOCIATING 2 BINS TO THE FIRST PHOTON A

CAN BE OBTAINED WITH A DYNAMIC RANGE OFABOUT 450 PHOTONS

for the specific case of 8 bits at 0.9 MHz frame rate are reportedin Tables VI and VII. For comparison, in the tables, also thealready shown case of 1 bin per photon is reported. It can benoticed, for example, that for 1 keV photons a

can be achieved with a dynamic range about 450photons per pixel. Looking at the 3 keV case it is clear that

gets very small and the dynamic range is already on theorder of a few thousands photons. For higher energiesbecomes completely negligible and the dynamic range is furtherincreased.

C. Increased Dynamic Range With No Single Photon Detection

For the sake of completeness, in Table VI the expected dy-namic range of the DSSC, in case we give up the single photondetection, is presented. We show the estimated dynamic rangeobtained reducing the gain of the analog front-end so that theamplitude of the signal produced by the first 2 collected pho-tons is equal to the size of one bin of the ADC. In other wordswe attribute 0.5 bins to the first photon. In this way it is intrinsi-cally not possible to distinguish one photon from zero photons.Nevertheless this operating mode can be used in experimentswhere a very high dynamic range is more important than singlephoton detection. In this operating mode is not de-fined. Therefore we express the probability of false detection as

, i.e., as the probability to detect 2 or more photonseven if no charge has been collected. The values areshown in Table VII. In this table the values for the other cases(1 bin/ph. and 2 bins/ph.) represent the .


Fig. 15. T4 virus diffraction image simulation. (a) Depicts the simulated input distribution of incident photons per pixel, randomly drawn from a diffraction imagemeasured at LCLS [22], [23]. (b) Shows the reconstructed photon image, after application of a first version of the DSSC response simulation. In the reconstruction,some pixels have a non-zero output, even if no photon is present in the incoming distribution. The probability of false detection, extracted from this image, is

, as expected from Table V. The reconstructed image and the incident photon distribution agree within the Poisson uncertainty of the inputsignal. (c) shows a comparison of incident photon distribution (black data points) and reconstructed image (red histogram) for all pixels in column 191, i.e., downthe center of (a) and (b). A more detailed comparison for the bottom part of bright diffraction pattern in column 191 is given in (d): the black data points depict theincident photon distribution and its Poisson error, the red histogram depicts the reconstructed image.

It must be mentioned that the DSSC will be able to switchfrom one gain setting to another one “on-the-fly”, during an ex-periment. In this way it will be possible to acquire a set of im-ages with high dynamic range and soon after to acquire anotherset of images with reduced dynamic range but improved singlephoton resolution.

D. System Simulation

The values reported in the previous paragraphs have beenused as input parameters for the DSSC system simulation soft-ware package [21]. This is based on the CERN libraries Geant4[24] and ROOT [25] and simulates the whole signal chain fromincident photon distribution to digital output. The object ori-ented source code of this system simulation package is writtenin . The package features all salient sensor physics andsignal processing electronics required for DSSC system simu-lation.In order to demonstrate the expected capabilities of the DSSC

detector, we simulated the measurement of a T4 virus diffrac-tion image [22] measured at the Linac Coherent Light Source

(LCLS) [23] with a pnCCD detector of the CAMP chamber [26].For the simulation, the measured T4 virus diffraction image wasused as a two-dimensional parent distribution from which theinput distribution of incident photons was randomly drawn (seeFig. 15). A photon energy of 1 keV was assumed. Sensor andelectronics noise components were set as expected for 4.5 MHzoperation with an 8 bit ADC assigning one bin to the first in-coming photon (see Table III). The simulation takes into ac-count the interaction and the energy deposition into the sensorof the incident photons, the charge sharing among neighboringpixels, the non-linear response of the DEPFET and the model ofthe readout electronics, including the calibration features. Thedetails of this simulation are given in [21]. Here we simplyshow the comparison between the assumed incoming photondistribution and the simulated reconstructed image coming fromthe DSSC model. It can be stated that the absolute magnitudeof the difference between the two images is smaller than thePoisson uncertainty of the incident photon signal (Fig. 15(d)).From the reconstructed image we can see that some pixels havea non-zero output, even if no photon is present in the incoming


distribution. The probability of false detection, extracted fromthis image, is . As expected this matches verywell the value in Table V.The simulation of a photon distribution from diffraction on a

T4 virus illustrates the salient characteristics of the DSSC de-tector: simultaneous single photon counting and large dynamicrange.

VI. CONCLUSION

We are developing a Pixel Detector system for the Euro-pean XFEL based on innovative non-linear DEPFET devicesthat constitute the first element of the front-end electronics. Inour fully parallel readout scheme, the signals coming from thepixels are filtered, digitized and stored in the focal plane. TheDEPFET signal compression principle has been experimentallyverified for the first time on a non-linear DEPFET prototype. An8 8 readout ASIC comprising the whole pixel readout chainhas been produced and tested. The noise measured coupling theASIC with a standard DEPFET is about 15 el. r.m.s. with anintegration time of 250 ns. This value is fully compatible withthe expected and desired performance of the DSSC. Estimatesbased on the first experimental results show that it will be pos-sible to achieve simultaneously single photon detection and highdynamic range even at low energies.

ACKNOWLEDGMENT

The authors would like to acknowledge the excellent tech-nical work of K. Hermenau, G. Liemann, B. Schweinfest,Alexander Venzmer, Eric Wüstenhagen and Alexander Titze.The authors are also grateful to Monica Turcato, MarkusKuster, Andreas Schwarz and the members of the DSSC De-tector Integration Group of the European XFEL for preciousdiscussions.

REFERENCES

[1] M. Porro et al., “Expected performance of the DEPFET sensor withsignal compression: A large format X-ray imager with mega-framereadout capability for the European XFEL,” Nucl. Instr. Meth. A, vol.624, no. 2, pp. 509–519, 2010.

[2] [Online]. Available: http://www.xfel.eu/[3] M.Meyer, “Conceptual design report: Scientific instrument SQS,” Apr.

2011, doi:10.3204/XFEL.EU/TR-2011-003.[4] [Online]. Available: http://www.xfel.eu/research/instruments/scs/[5] A. Mancuso, “Conceptual design report: Scientific instrument SPB,”

Jan. 2012, doi:10.3204/XFEL.EU/TR-2011-007.[6] J. Kemmer and G. Lutz, “New semiconductor concept,” Nucl. Instr.

Meth. A, vol. 253, pp. 365–377, 1987.

[7] M. Porro et al., “Spectroscopic performance of DePMOS detector/am-plifier devicewith respect to different filtering techniques and operatingconditions,” IEEE Trans. Nucl. Sci., vol. 53, no. 1, pp. 401–408, Feb.2006.

[8] Private communications with Dr. Markus Kuster, the leading scientistsand the Detector Integration Group of the European XFEL.

[9] G. Lutz, P. Lechner, M. Porro, L. Strüder, and G. D. Vita, “DEPFETsensor with intrinsic signal compression developed for use at the XFELfree electron laser radiation source,” Nucl. Instr. Meth. A, vol. 624, no.2, pp. 528–532, 2010.

[10] P. Lechner et al., “DEPFET active pixel sensor with non-linear ampli-fication,” in Proc. Nucl. Sci. Symp. Med. Imag. Conf. (NSS/MIC), 2011IEEE, Oct. 2011, pp. 563–568.

[11] R. Kohrs et al., “Development of a prototype module for a DEPFETpixel vertex detector for a linear collider,” IEEE Trans. Nucl. Sci., vol.52, no. 4, pp. 1171–1175, Aug. 2005.

[12] K. Hansen, H. Klar, and D. Muntefering, “Camera head of the DSSCX-ray imager,” in Proc. Nucl. Sci. Symp. Med. Imag. Conf. (NSS/MIC),2011 IEEE, Oct. 2011, pp. 1713–1717.

[13] T. Gerlach et al., “The DAQ readout chain of the DSSC detector at theEuropean XFEL,” in Proc. Nucl. Sci. Symp. Med. Imag. Conf. (NSS/MIC), 2011 IEEE, Oct. 2011, pp. 156–162.

[14] P. Fischer et al., “Pixel readout ASIC with per pixel digitization anddigital storage for the DSSC detector at XFEL,” in Proc. Nucl. Sci.Symp. Med. Imag. Conf. (NSS/MIC), 2010 IEEE, 30, 2010–Nov.62010, pp. 336–341.

[15] S. Facchinetti, L. Bombelli, C. Fiorini, M. Porro, G. De Vita, and F.Erdinger, “Characterization of the flip capacitor filter for the XFEL-DSSC project,” IEEE Trans. Nucl. Sci., vol. 58, no. 4, pp. 2032–2038,Aug. 2011.

[16] S. Facchinetti et al., “Fast, low-noise, low-power electronics for theanalog readout of non-linear DEPFET pixels,” inProc. Nucl. Sci. Symp.Med. Imag. Conf. (NSS/MIC), 2010 IEEE, Oct. 2011, pp. 1846–1851.

[17] M. Manghisoni, E. Quartieri, L. Ratti, and G. Traversi, “High accuracyinjection circuit for pixel-level calibration of readout electronics,” inProc. Nucl. Sci. Symp. Med. Imag. Conf. (NSS/MIC), 2010 IEEE, 30,2010–Nov. 6 2010, pp. 1312–1318.

[18] E. Quartieri and M. Manghisoni, “Performance of a high accuracy in-jection circuit for in-pixel calibration of a large sensor matrix,” in Proc.Nucl. Sci. Symp. Med. Imag. Conf. (NSS/MIC), 2011 IEEE, Oct. 2011,pp. 677–681.

[19] C. Reckleben, K. Hansen, P. Kalavakuru, and I. Diehl, “8 bit 5 MS/sper-pixel ADC in an 8-by-8 matrix,” in Proc. IEEE Nucl. Sci. Symp.Med. Imag. Conf. (NSS/MIC), Oct. 2011, pp. 668–672.

[20] K. Hansen, C. Reckleben, I. Diehl,M. Bach, and P. Kalavakuru, “Pixel-level 8-bit 5-MS/s Wilkinson-type digitizer for the DSSC X-ray im-ager: Concept study,”Nucl. Instr. Meth. A, vol. 629, no. 1, pp. 269–276,2011.

[21] G. Weidenspointner et al., “Strategy for calibrating the non-lineargain of the DSSC detector for the European XFEL,” in Proc. Nucl.Sci. Symp. Med. Imag. Conf. (NSS/MIC), 2011IEEE, Oct. 2011, pp.468–473.

[22] S. Kassemeyer et al., “Femtosecond free-electron laser x-ray diffrac-tion data sets for algorithm development,” Opt. Exp. vol. 20, no. 4,pp. 4149–4158, Feb. 2012 [Online]. Available: http://www.opticsex-press.org/abstract.cfm?URI=oe-20-4-4149

[23] [Online]. Available: http://lcls.slac.stanford.edu/[24] S. Agostinelli et al., “Geant4 a simulation toolkit,” Nucl. Instr. Meth.

A, vol. 506, no. 3, pp. 250–303, 2003.[25] R. Brun and F. Rademakers, “Root: An object oriented data analysis

framework,” Nucl. Instr. Meth. A, vol. 389, no. 1–2, pp. 81–86, 1997.[26] L. Strüder et al., “Large-format, high-speed, X-ray pnCCDs combined

with electron and ion imaging spectrometers in amultipurpose chamberfor experiments at 4th generation light sources,” Nucl. Instr. Meth. A,vol. 614, no. 3, pp. 483–496, 2010.

development of the depfet sensor with signal compression: a large format x-ray imager with...

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