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Institutionen för systemteknikDepartment of Electrical Engineering

Examensarbete

Designing a Low Power Regulator for Smart Dust

Examensarbete utfört i ämnet Elektroniksystemvid Tekniska högskolan vid Linköpings universitet

av

Mohamed Lababidi

LiTH-ISY-EX--12/4643--SE

Linköping 2011

Department of Electrical Engineering Linköpings tekniska högskolaLinköpings universitet Linköpings universitetSE-581 83 Linköping, Sweden 581 83 Linköping

Designing a Low Power Regulator for Smart Dust

Examensarbete utfört i ämnet Elektroniksystemvid Tekniska högskolan i Linköping

av

Mohamed Lababidi

LiTH-ISY-EX--12/4643--SE

Handledare: Joakim Alvbrantisy, Linköpings universitet

Examinator: Dr. J Jacob Wiknerisy, Linköpings universitet

Linköping, 19 September, 2011

Avdelning, InstitutionDivision, Department

Division of Electronics SystemsDepartment of Electrical EngineeringLinköpings universitetSE-581 83 Linköping, Sweden

DatumDate

2011-09-19

SpråkLanguage

Svenska/Swedish Engelska/English

RapporttypReport category

Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk versionhttp://www.es.isy.liu.se/

http://www.ep.liu.se

ISBN—

ISRNLiTH-ISY-EX--12/4643--SE

Serietitel och serienummerTitle of series, numbering

ISSN—

TitelTitle

Designa en Låg Effekt Regulator för Smart DustDesigning a Low Power Regulator for Smart Dust

FörfattareAuthor

Mohamed Lababidi

SammanfattningAbstract

The revolutionary progress that happened recently in the micro-electro mechan-ical systems (MEMS) field and the complementary metal-oxide-semiconductor(CMOS) integrated circuits has made it possible to produce low-cost, low-powerand small size processing circuits. Utilizing wireless communication theory allowsthose circuits to send their data over a network. This wireless sensor network isknown as "Smart Dust".

Each wireless sensor node in the network is indicated as "mote". It consistsof several components: sensors, micro-processors, radio transceivers and a powermanagement unit. The power management unit can be divided into several partsincluding battery, power control and regulator. The purpose of the regulator is tosupply a constant reliable voltage to the other parts in the mote as most of thedevices have voltage limits that need to be considered to guarantee producing arobust long-life mote.

In this thesis designing a low-power regulator is investigated. The goal of thethesis is to design a regulator that can handle the high-voltage acquired froman energy harvest unit using only 65-nm core transistors. This allows an easierproduction process that results in a low-cost fully-integrated chip. The regulatorarchitecture to be used is a simple linear regulator.

The report highlights the theoretical background, the challenges of the analogdesign and presents the results of the simulation that were ran using cadence designsystem software on schematic level.

NyckelordKeywords communication, electronics, smartdust, regulator, low power, 65-nm

AbstractThe revolutionary progress that happened recently in the micro-electro mechan-ical systems (MEMS) field and the complementary metal-oxide-semiconductor(CMOS) integrated circuits has made it possible to produce low-cost, low-powerand small size processing circuits. Utilizing wireless communication theory allowsthose circuits to send their data over a network. This wireless sensor network isknown as "Smart Dust".

Each wireless sensor node in the network is indicated as "mote". It consistsof several components: sensors, micro-processors, radio transceivers and a powermanagement unit. The power management unit can be divided into several partsincluding battery, power control and regulator. The purpose of the regulator is tosupply a constant reliable voltage to the other parts in the mote as most of thedevices have voltage limits that need to be considered to guarantee producing arobust long-life mote.

In this thesis designing a low-power regulator is investigated. The goal of thethesis is to design a regulator that can handle the high-voltage acquired froman energy harvest unit using only 65-nm core transistors. This allows an easierproduction process that results in a low-cost fully-integrated chip. The regulatorarchitecture to be used is a simple linear regulator.

The report highlights the theoretical background, the challenges of the analogdesign and presents the results of the simulation that were ran using cadence designsystem software on schematic level.

v

Acknowledgments

I would like to thank God that I was fortunate enough to have the opportunityto study this master program at Linköping University. A lot of people in differentparts of the world are not able to do that because of their bad circumstances. SoI am, as always, very grateful.Then I would like to thank My parents: My father who did everything he could, onboth economical and motivational sides, to make me study this master programand finish my thesis work, and my mother who kept pushing me forward, evenduring the hardest times, towards reaching my goals and dreams.A big thanks to My examiner Dr.Jacob Wikner, who also suggested me this chal-lenging topic, for his unconditional support and incredible patience during thisthesis work. I could not ask for any better mentoring. I have certainly learned alot during this thesis work and I am very thankful to you Jacob for all the supportyou have provided.My supervisor Joakim Alvbrant who answered all my questions regarding the ana-log design, thanks a lot Joakim.Many thanks to PhD student Ekhiotz Vergara who helped me a lot to improvemy thesis report. Also Markus Keller who gave me a great feedback through hisopposition, Blerina Hasa and Hani Kamal who put an effort to help me fixing themistakes in the report.My siblings, friends and lab mates who are all part of my success in one way oranother.

I thank you all and wish you the best in the bright future ahead of you. I willdo my best to support or help you whenever I am needed.

Finally, I hope that this report will add some knowledge to the readers andwill help students who are doing their thesis in the analog design to complete theirwork or report in a good way.

vii

Contents

1 Introduction 51.1 Smart Dust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1.1 What is Smart Dust? . . . . . . . . . . . . . . . . . . . . . 51.1.2 A Brief History . . . . . . . . . . . . . . . . . . . . . . . . . 51.1.3 Smart Dust at Linköping University (LiU) . . . . . . . . . . 6

1.2 Thesis Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.3 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Introduction to Regulators 132.1 What is a Regulator? . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2 Regulator Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.1 Switching Regulators . . . . . . . . . . . . . . . . . . . . . . 142.2.2 Linear Regulators . . . . . . . . . . . . . . . . . . . . . . . 16

2.3 Selecting the Architecture . . . . . . . . . . . . . . . . . . . . . . . 19

3 Theory Background for Analog Design 213.1 Modeling the Short Channel MOSFET . . . . . . . . . . . . . . . . 213.2 Core Transistors and I/O Transistors . . . . . . . . . . . . . . . . . 223.3 Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.3.1 Two-Stage Operational Amplifier . . . . . . . . . . . . . . . 273.3.2 Cascode Operational Amplifier . . . . . . . . . . . . . . . . 273.3.3 Folded-Cascode Operational Amplifier . . . . . . . . . . . . 273.3.4 Current-Mirror Operational Amplifier . . . . . . . . . . . . 303.3.5 Operational Transconductance Amplifier (OTA) . . . . . . 313.3.6 Selecting a suitable Operational Amplifier . . . . . . . . . . 33

3.4 Current Mirrors Techniques . . . . . . . . . . . . . . . . . . . . . . 343.4.1 Basic Current Mirrors . . . . . . . . . . . . . . . . . . . . . 343.4.2 Cascode Current Mirrors . . . . . . . . . . . . . . . . . . . 343.4.3 Wide-Swing Current Mirrors . . . . . . . . . . . . . . . . . 37

4 Designing the Regulator 414.1 The Resistors Ladder and the Transmission Gates . . . . . . . . . 434.2 Designing the OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.2.1 Cascading the OTA . . . . . . . . . . . . . . . . . . . . . . 47

ix

x Contents

4.3 The Pass Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . 504.3.1 Biasing the Cascoding Transistors . . . . . . . . . . . . . . 51

4.4 The OTA Test-Bench . . . . . . . . . . . . . . . . . . . . . . . . . 524.5 The Regulator Test-Bench . . . . . . . . . . . . . . . . . . . . . . . 52

5 Simulation Results 555.1 Voltage Drop Simulations . . . . . . . . . . . . . . . . . . . . . . . 555.2 DC Load Simulations . . . . . . . . . . . . . . . . . . . . . . . . . 575.3 AC Load Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . 605.4 Transient Response Simulations . . . . . . . . . . . . . . . . . . . . 645.5 Temperature Changes Simulations . . . . . . . . . . . . . . . . . . 675.6 Ctrl-bit Settings Simulations . . . . . . . . . . . . . . . . . . . . . 70

5.6.1 0.5 V Output . . . . . . . . . . . . . . . . . . . . . . . . . . 705.6.2 0.6 V Output . . . . . . . . . . . . . . . . . . . . . . . . . . 725.6.3 0.7 V Output . . . . . . . . . . . . . . . . . . . . . . . . . . 735.6.4 0.8 V Output . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.7 Sleep Mode Simulations . . . . . . . . . . . . . . . . . . . . . . . . 765.8 Power Down Simulations . . . . . . . . . . . . . . . . . . . . . . . . 785.9 Corner Analyze Simulations . . . . . . . . . . . . . . . . . . . . . . 79

6 Conclusion 85

7 Future Work 87

Bibliography 89

A Permission of using the photo of the Mica mote 91

List of Figures1.1 The Mica mote combines sensing, power, computation, and com-

munication into one package using off-the-shelf components. . . . . 71.2 Outline of smart dust model. . . . . . . . . . . . . . . . . . . . . . 8

2.1 Single-ended PWM DC-DC converters. . . . . . . . . . . . . . . . . 152.2 Basic circuits of linear voltage regulators (a) Series voltage regulator

(b) Shunt voltage regulator. . . . . . . . . . . . . . . . . . . . . . . 172.3 The selected voltage regulator architecture for the smart dust mote. 19

3.1 A two-stage operational amplifier circuit. . . . . . . . . . . . . . . 283.2 A cascode (telescopic) operational amplifier circuit. . . . . . . . . . 293.3 A folded-cascode operational amplifier circuit. . . . . . . . . . . . . 303.4 A current-mirror operational amplifier circuit. . . . . . . . . . . . . 313.5 A simple current-mirror operational transconductance amplifier cir-

cuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.6 A cascode current-mirror operational transconductance amplifier

circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.7 (a) A simple current-mirror. (b) A small-signal model of the current-

mirror circuit shown in (a). . . . . . . . . . . . . . . . . . . . . . . 353.8 A cascode current-mirror circuit. . . . . . . . . . . . . . . . . . . . 363.9 A wide-swing current-mirror circuit. . . . . . . . . . . . . . . . . . 38

4.1 The voltage regulator circuit. . . . . . . . . . . . . . . . . . . . . . 424.2 (a) The resistor ladder for several output values. (b) The transmis-

sion gate placing in the regulator circuit. . . . . . . . . . . . . . . . 444.3 The transmission gate circuit. . . . . . . . . . . . . . . . . . . . . . 454.4 A simple current-mirror PMOS-input circuit. . . . . . . . . . . . . 464.5 A circuit to increase the input level. . . . . . . . . . . . . . . . . . 474.6 The cascoded bias current circuit of the OTA. . . . . . . . . . . . . 494.7 The final circuit of the cascoded OTA. . . . . . . . . . . . . . . . . 504.8 The test bench circuit of the OTA. . . . . . . . . . . . . . . . . . . 524.9 The test bench circuit of the regulator. . . . . . . . . . . . . . . . . 53

5.1 The voltage drops on all the transistors of the OTA when the max-imum current is pulled by the load. . . . . . . . . . . . . . . . . . . 56

5.2 The voltage drops on all the transistors of the OTA when there isno current pulled by the load. . . . . . . . . . . . . . . . . . . . . . 56

5.3 The output error for all unregulated voltage values and maximumDC load current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.4 The output error variation against DC load current for 1.8 to 2.1 Vunregulated voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 58



2 Contents

5.7 The output error variation against DC load current for 3 to 3.3 Vunregulated voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 59


5.9 The AC current load on the regulator output. . . . . . . . . . . . . 615.10 The output error for all unregulated voltage values and AC current

load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615.11 The output voltage for 1.8 V unregulated voltage and AC current




load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635.15 The vpwl signal used to cause load transient. . . . . . . . . . . . . 645.16 The output voltage load transient response for 1.9 V, load changes

from half-load to full-load. . . . . . . . . . . . . . . . . . . . . . . . 655.17 The output voltage load transient response for 3.3 V, load changes

from half-load to full-load. . . . . . . . . . . . . . . . . . . . . . . . 655.18 The output voltage load transient response for 1.9 V, load changes

from half-load to no-load. . . . . . . . . . . . . . . . . . . . . . . . 665.19 The output voltage load transient response for 3.3 V, load changes

from half-load to no-load. . . . . . . . . . . . . . . . . . . . . . . . 665.20 The output error for temperatures between -20-70 C and input volt-

ages between 1.8-3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . 685.21 The output error for temperatures between -20-70 C and DC-load

between 0-50 uA ,1.8 V input voltage. . . . . . . . . . . . . . . . . 695.22 The output error for temperatures between -20-70 C and DC-load

between 0-50 uA, 2.7 V input voltage. . . . . . . . . . . . . . . . . 695.23 The output error for temperatures between -20-70 C and DC-load

between 0-50 uA, 3.6 V input voltage. . . . . . . . . . . . . . . . . 705.24 The output error for input voltages between 1.8-3.6 V and full DC

load, 0.5 V regulated voltage. . . . . . . . . . . . . . . . . . . . . . 715.25 The output error for input voltages between 1.8-3 V and DC-load

between 0-50 uA, 0.5 V regulated voltage. . . . . . . . . . . . . . . 715.26 The output error for input voltages between 1.8-3.6 V and full DC-

load, 0.6 V regulated voltage. . . . . . . . . . . . . . . . . . . . . . 725.27 The output error for input voltages between 1.8-3.2 V and DC-load


load, 0.7 V regulated voltage. . . . . . . . . . . . . . . . . . . . . . 735.29 The output error for input voltages between 1.8-3.3 V and DC-load


load, 0.8 V regulated voltage. . . . . . . . . . . . . . . . . . . . . . 74

Contents 3

5.31 The output error for input voltages between 1.8-2.1 V and DC-loadbetween 0-50 uA, 0.8 V regulated voltage. . . . . . . . . . . . . . . 75

5.32 The output error for input voltages between 2.1-3.4 V and DC-loadbetween 0-50 uA, 0.8 V regulated voltage. . . . . . . . . . . . . . . 75

5.33 The current consumption for the regulator when Ctrl equals VDD. 775.34 The current consumption for the regulator in sleep mode. . . . . . 775.35 The output voltage versus time during periodic VDD change every

10µs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.36 The output voltage versus time during VDD change with period of

200µs and a pulse width of 1µs. . . . . . . . . . . . . . . . . . . . . 795.37 The output error for full DC load in corner analyze typical case. . 805.38 The output error for full DC load in corner analyze fast-fast-fast case. 805.39 The output error for full DC load in corner analyze slow-slow-slow

case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815.40 The output error for full DC load in corner analyze fast-slow-typical

case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815.41 The output error for full DC load in corner analyze slow-fast-typical

case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815.42 The output error for full DC load in corner analyze fast-slow-slow

case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825.43 The output error for full DC load in corner analyze slow-fast-slow

case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825.44 The output error for full DC load in corner analyze fast-slow-fast

case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825.45 The output error for full DC load in corner analyze slow-fast-fast

case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

List of Tables1.1 Requirement specifications of the regulator. . . . . . . . . . . . . . 11

2.1 Comparison between switching and linear regulators features andthe requirements and preferences for the smart dust project. . . . . 20

3.1 The tolerable voltages regarding the affecting lifetime mechanismsfor a typical 65-nm CMOS technology. . . . . . . . . . . . . . . . . 25

5.1 The DC-load range where the regulator supplies a regulated outputfor different input voltages. . . . . . . . . . . . . . . . . . . . . . . 60

5.2 A summary of the transient response simulation results. . . . . . . 675.3 The maximum input voltage versus the output voltage for which

the regulator is still able to provide a good output regulated voltage. 765.4 The corner cases and the respective input voltage range for which

the regulator is still able to provide a good output regulated voltage. 83

4 Contents

6.1 The simulation type and the respective input voltage range forwhich the regulator is still able to provide a good output regulatedvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Chapter 1

Introduction

The revolutionary improvements in the Micro Electro Mechanical Systems (MEMS)field, which have recently evolved following Moore’s Law, have pushed the indus-try towards producing microsensors that consume less power and cost less [1].Furthermore Moore’s law has continued to correctly estimate the improvements inthe complementary metal-oxide-semiconductor (CMOS) integrated circuits, lead-ing to the possibility of producing 'tiny' low-cost processing circuits.Combining the former two technologies with the wireless communication theoryallows for producing a low-cost, low-power and a small size chip that can sense,compute and send data over a network. This wireless sensor network is usuallyreferred to as Smart Dust [2].

1.1 Smart Dust1.1.1 What is Smart Dust?The Smart Dust term is used to refer to a broad range of tiny hardware thatforms a wireless sensors network. Those wireless sensor nodes, also called motes,are spread around a large area and can communicate with each other in an ad-hocnetwork.Each dust mote is made up mainly from one or more sensors, a data processingunit, a transceiver for communicating with other motes in the network, and apower supply [2].

1.1.2 A Brief HistoryIn 1992 the idea of Smart Dust was visualized as a future technology by Kris Pisterduring a workshop at RAND Corporation. Two years later, he found out that itcould be implemented sooner than he had thought. Therefore, he continued hisresearch and started publishing papers to present that technology [3].

The idea was to create tiny wireless sensors that are distributed randomly overa big area to make a network that acts as one intelligent system.

5

6 Introduction

Those sensor nodes have got the ability to sense sound, light, temperature, mois-ture, vibrations or chemicals, and then send the information to a distanced mainunit.

A typical application for the Smart Dust is in the military, where the motescould be spread in the desert sands and be used to detect the sound of a passingtank or the metal of the weapons of passing soldiers. Once the sensors detect asignal they send an alarm and they can be even used to track the enemy’s move-ments.With such possible applications, Smart Dust attracted the US Defense AdvancedResearch Projects Agency (DARPA) to support Pister’s research. DARPA’s sup-port has helped Pister to implement the first Smart Dust hardware in 1998.

The third-generation hardware, known as the Rene mote, was developed in2001 by the Pister’s lab. The mote had the size of a matchbox and the battery setwas a few times bigger. But the battery voltage affected the mote’s performancein a direct way. Overall, the Rene motes did not function with high credibility.Meanwhile, there were efforts to move further on the software side. At Berekley,a software engineer named David Culler was working on building a bare-bonesoperating system flexible for implementation in many different electronics.Jason Hill, a smart dust software consultant, combined the two projects togetherby editing the circuit design of the mote and embedding the operating system,named TinyOS. Hill’s efforts’ outcome was called the Mica mote.The operating system (OS) preserved power by controlling the hardware to executeonly vital operations. Thanks to those improvements the Mica mote needed just acouple of AA batteries to function, which made the whole device’s size equivalentto the new pagers size [2]. Figure 1.1 shows the Mica mote.

Mica was selected by the defense agency for the Network Embedded SystemsTechnology (NEST) project, making the mote an interest for a lot of labs, andwith corporation between Berkeley and Crossbow Technology the motes have beencommercialized within affordable prices.The success that Mica showed in the first few months of NEST encouraged Hilland Pister to bring this new technology to the market, as a result "Dust, Inc" wasestablished by Hill and Pister in 2002.

Being financially supported helped developing a smaller mote. The mote wasnamed Spec, and it was the first mote to implement radio frequency communica-tion with adopted circuits running on TinyOS. The size of the mote was roughlyequal to the size of a piece of glitter.Spec being much smaller than Mica indicates that Smart Dust has the potential toreach the size of the real dust, however this is related to the evolution of batterytechnology [3].

1.1.3 Smart Dust at Linköping University (LiU)As mentioned at the beginning of chapter 1, the revolutionary progress in CMOSand MEMS manufacturing joined by the motivation to produce costless long-life units are pushing the evolution of system on chip (SoC) solutions towards

1.1 Smart Dust 7

Figure 1.1. The Mica mote combines sensing, power, computation, and communicationinto one package using off-the-shelf components [2].

producing motes within cubic centimeter scale and fewer off-chip components.Here, at the division of Electronics systems, Department of Electrical Engineeringat Linköping University, a recent Smart Dust research has been launched underthe supervision of Dr. Jacob Wikner and the contribution of researchers, Phdstudents and Master Students.

The aim of the project is mainly to achieve an extreme low power consumptionand to digitize the components in order to achieve a better performance. Theproject gives the chance for the master students to work in an industrial fashion,where each student is responsible for building a particular block while workingalong with other students and researchers to complete the whole project.The outline of the mote is illustrated in Figure 1.2. Different blocks shown in thefigure can be briefly presented as the following: The sensor can vary depending onthe application that the mote is intended to be used for, it can be a microphone,thermometer, smoke sensor, etc. For some applications, there could be more thanone sensor. The transceiver is used for communication with the other motes in thenetwork. The energy harvest, energy storage, supply regulator and control unitblocks shown in figure 1.2 represent the mote’s power supply system. The energyharvest block can acquire energy from the surrounding environment. The energystorage block is usually a battery that is responsible for maintaining the energy.The regulator block is responsible for supplying suitable voltages required for dif-ferent blocks in the mote. The control block is responsible for administrating theavailable power in an efficient way. The micro processor unit’s main responsibility

8 Introduction

Figure 1.2. Outline of smart dust model.

is to manage the data between the transceiver and the sensors.

Producing motes with long lifetimes is demanded for most applications of thesmart dust. Even though harvesting energy from the surrounding environmentincreases the mote’s life time, since energy is not limited, a battery unit might stillbe needed for maintaining the harvested energy. Batteries can usually live in therange of one to ten years, which indicates that the power dissipation of a mote,sized within an inch range, must be in the order of tens to hundreds of microwattson average per day, according to typical batteries’ capacity.

1.2 Thesis ScopeThe demand for higher level of integration, low cost and high speed are draggingCMOS technology towards the dimension of 65nm and less. In order to guaranteea good performance of these 65nm devices, the supply voltage should be less than1 V. However, the drawback of such a low supply voltage is that it increases thepower consumption of many analog devices [4].In CMOS circuits the power dissipation is proportional to the minimum featuresize. Therefore using only core transistors in the regulator circuit while supplyinghigh voltages will result in an extreme low power consumption. However, applyinghigh voltages on core transistors posses a big challenge since it shortens the devices’

1.3 Thesis Outline 9

lifetime.The scope of this thesis is investigating a method to apply voltages higher thanthe nominal supply voltage of 65-nm devices while keeping the lifetime unaffected.In particular, this thesis studies the feasibility of designing a regulator with 65-nmcore transistors that has an input voltage much higher than the nominal supplyof core transistors.

1.3 Thesis OutlineIn this thesis a regulator is designed, which supplies a regulated voltage to thedigital and analog parts of the mote. The regulator is required to consume lowpower. Moreover, it is requested to be built using 65-nm core transistors only.

The report, which covers work that has been done in this thesis, is divided intothe following chapters:

• Chapter 1 introduces the reader to the smart dust project and the work thatneeded to be done in this thesis.

• Chapter 2 includes a brief introduction of some regulator types, such as linearregulators and switched regulators. The advantages and disadvantages ofthose regulator types are shown. The chapter ends with a discussion aboutchoosing a suitable architecture for the project.

• Chapter 3 presents some theoretical background about analog design andthe challenges for analog designers in low voltage devices.

• Chapter 4 explains the regulator design of this project and the problems thathave been faced to meet the requirements in the design.

• Chapter 5 shows the simulation results that have been executed on a schematiclevel of the designed regulator circuit.

• Chapter 6 concludes the work that has been done during this thesis, basedon the achieved results.

• Chapter 7 presents some of the future work to be done towards the produc-tion of the mote’s chip.

1.3.1 SpecificationsThe requirement specifications for the regulator design are shown in table 1.1.The input voltage represents the unregulated supply voltage. Achieving a 5µAcurrent consumption is targeted for active mode, while the current consumptionshould reach a minimum value during sleep mode. The regulated output voltagecan be tuned to one of the voltage levels shown in the table. The load current 1is assumed to be a Direct Current (DC) current for the analog parts in the motewhile load current 2 is assumed for the digital parts in the mote. The currentconsumed by the digital parts is pulse Alternative Current (AC) current. The

10 Introduction

response time of the regulator to changes in the load should not exceed 10µs. Theoperating temperature is ranging between -20 and 70 C. The area and the biascurrents are decided at later stages in the design. However, minimal values aretargeted. Finally, the technology used is STM 65-nm core devices. The usageof core devices in combination with the requirements for the input voltage rangeposes the greatest challenge for the design.

1.3 Thesis Outline 11

Item Unit Min Type Max

Input Voltage V 1.8 2.7 3.6

Current Consumption Amp 0µ 5 µ

Output Voltage level 1 V 0.85 0.9 0.95





Load Current 1 Amp 0µ 50µ

Load Current 2 Amp 0µ 100µ

Transient Response Sec 10µ

SleepMode Yes

Temp C -20 70

Process nm 65

Area mm TBD

Bias Currents Amp TBD

Table 1.1. Requirement specifications of the regulator.

Chapter 2

Introduction to Regulators

As we are heading towards nano meter scales in size and GHz frequency rangesin operating frequencies used, the problems of obtaining reliable power sourcesare becoming more significant. Supplying a clean power in the integrated cir-cuits became more challenging with the frequency increment and the rise of usingmixed-signal systems. Inefficient management of power leads to poor chip perfor-mance, larger area utilization and causes the design to function improperly. Forthis reason, managing the power consumption is vital since it has an importanteffect on the Integrated Circuit’ (IC) performance.

Most of the computing systems contain voltage regulators which are necessaryto hand over the power from the source to several integrated circuits. They canhandle either constant or time-varing voltage levels. The regulator is responsiblefor supplying a constant proper voltage level to the electronic components whichenables them to function properly. In addition, the regulator should be able tocontrol power fluctuations and protect loads connected to the supply from damage[5].

2.1 What is a Regulator?Generally, a voltage regulator is a circuit that provides a constant voltage supplyfor the electrical or the electronic devices that are connected to it. The regula-tor circuit is used in order to protect those devices from damage due to voltagechanges, since most of the devices have voltage limits. It is one of the main powersupply blocks for every electronic or electrical device. Furthermore, regulators canbe used to supply voltages to the connected devices that are within the operatingranges of those devices.

Usually electronic devices work in low voltages, and providing a voltage higherthan the maximum acceptable voltage causes a damage in the device. On theother hand, providing a very low voltage can cause the device to disfunction orwork inappropriately. Therefore we need to guarantee an acceptable voltage sup-

13

14 Introduction to Regulators

ply range for the device, and the purpose of the regulators is to supply a voltagewithin that range. In most of the cases, the regulators down-convert the voltagefrom a higher voltage to a lower one [6].

Since the regulator is designed to keep the output voltage constant in spite ofchanges in the input voltage or the load current, the regulator’s performance isoften specified with the following parameters [7]:

Dynamic load response time is the time slot needed for the regulator to setthe output voltage withing the acceptable range when there is a step changein the load current [8].

Line regulation is indicating how much the output voltage changes when theinput voltage changes, in percentage [8].

LineReg =Vo,(hi,in) − Vo,(lo,in)

Vo,(nom,in)· 100(%) (2.1)

Load regulation is indicating, in percentage, how much the output voltage changeswhen the load current changes from the no load current to full load currentcondition [8].

LoadReg =Vo(no−load) − Vo(full−load)

Vo(full−load)· 100(%) (2.2)

Overall efficiency is the percentage of the output power to the input powerratio, and it helps specifying the heat produced in the regulator [8].

effic. = PoutPin

· 100(%) (2.3)

2.2 Regulator TypesThere are plenty of voltage regulators types, but the most common ones for im-plementing on-chip are linear and switching regulators. Each of those types hasits advantages and disadvantages depending on the design of the IC [5].

Linear and switching regulators are also divided into different categories. Themain two categories of linear regulators are shunt regulators and series regulators,while the main switching regulator types are Pulse-Width Modulated (PWM),resonant regulators and switched-capacitor regulators.

2.2.1 Switching RegulatorsAlso known as DC-DC converters, the switching-mode regulators employ tran-sistors as switches. The voltage drop across the transistors and the conductedcurrent are inversely proportional which enables this regulators type to offer lowconduction losses and a high efficieny. However the conduction losses increase by

2.2 Regulator Types 15

increasing the switching frequency which leads to less efficiency.The pulse-width modulated regulators are very popular between the switching reg-ulators. Figure 2.1 shows some of the common topologies of single-ended PWMswitching regulators.

Figure 2.1. Single-ended PWM DC-DC converters.

The switching regulators function with a method that can be explained in asimplified way. As mentioned before, the power transistors of the PWM switchingregulators are working as switches, i.e. saturation and cutoff regions. The volt-ampere product in the power transistors is low during these states (low voltageand high current in saturation mode and high voltage no current in cutoff mode).The volt-ampere product in the power transistors represents the loss in the powerdevice (the regulator).The highly efficient functioning of the switching regulators is obtained by cuttingthe DC input voltage into pulses. The magnitude of the input voltage decides theamplitude of the pulse while the regulator controller part is controlling the dutycycle of the pulse.By transforming the input voltage to an AC rectangular waveform, several oper-ations can be performed to get the desired output voltage. Stepping the inputvoltage up or down is done by changing the amplitude of the pulse using a trans-former, also by adding secondaries to the transformer several output voltages canbe obtained. Eventually, the DC output voltages are derived by filtering the ACwaveforms.Similar to the linear regulator controller, the switching regulator controller is re-


sponsible for keeping a regulated output voltage. This means that the functionalblocks, voltage reference and error amplifier are staged in the same way of thelinear regulators. However, in the switching regulators a voltage-to-pulsewidthconverter stage is following the error amplifier, whereas in the linear regulatorsthe output voltage of the error amplifier (the error voltage) is driving the powertransistors. The main functional types of switching regulators are the forward-mode converter and the boost-mode converter, each has its advantages dependingon the applications to be used [8].

Advantages and Disadvantages

The switching regulators contain a low loss inductor which provides more efficientpower conversion, it also provides the regulator with the ability to transmit theenergy from the input to the output and finally it filters the output from switchingsignals.In addition, the switching regulators has the ability to create several output volt-ages from one input voltage and to step up the voltage. The duty cycle of theswitch decides the amount of charge transmitted to the load. However, as typi-cal switching regulators work in low switching frequency ranges and contain filtercomponents like inductors or capacitors, they are usually implemented off-chip.Hence problems like slow responses to the variations in the load current transientsand parasitic components in the circuitry between the regulator and the load areintroduced. Nevertheless, recently the focus was to implement on-chip switch-ing regulators which provides faster response to voltage transitions but demandssmaller size filter components and higher operating frequencies which affect thepower conversion efficiency [5].

2.2.2 Linear RegulatorsLinear regulators can be specified as shunt or series regulators, depending on wherethe control element (usually a transistor) is situated in the circuit [7]. Figure 2.2shows two basic circuits of series linear regulator and shunt linear regulator.

The general principle of the linear regulators is based on comparing a feedbacksignal with a reference voltage and amplifying the error signal. The output ofthe error voltage amplifier is controlling the current flow of the power transistorthat controls the load. Linear regulators usually have got a higher input voltagemagnitude than the output and a low output impedance [9].

Usually, the shunt regulators contain a small resistor that is placed in seriesbetween the load and the input voltage. The resistor value should be low enoughto always allow enough current to the load. The control element is set in parallelwith the load and maintains a constant voltage over the load [7].

The control element is mainly a transistor which maintains a constant outputvoltage by changing its current when the input voltage or the load current changes.The shunt transistor works like a variable resistor. Decreasing the output voltagecauses the amplifier output voltage to decrease, which results in less conduction

2.2 Regulator Types 17

Figure 2.2. Basic circuits of linear voltage regulators (a) Series voltage regulator (b)Shunt voltage regulator.


by the transistor, thus, increasing the resistance. As a consequence, more currentwill be directed to the load, resulting the load current and the output voltage toincrease.For a constant input voltage the input current remains constant when there is achange in the load current. This means that the transistor current changes, caus-ing the voltage drop on the shunt transistor to change in order to keep the outputvoltage fixed.

Shunt regulators are immune to short-circuits, however they are less efficientthan series regulators because of the losses in the series resistor and the shunttransistor. They have better line transient response than the series regulators butinput overvoltage can damage the shunt voltage regulator [10].

In series regulators, the transistor is set in series with the load and the inputvoltage. A constant voltage over the load is maintained by controlling the currentthrough the transistor. This is done by employing a feedback to compare the out-put voltage to a reference voltage using an amplifier which drives the transistor’scurrent [7].

The voltage drop on the pass transistor varies in a similar way as the inputvoltage does. Therefore the pass transistor is considered to act like a variable resis-tor. This variable resistor together with the load resistor form a voltage divider. Areduction in the input voltage causes a decrement in the variable resistance whichin turn causes an increment in the output voltage, and vice versa.The amplifier should work in the linear region in order to control the circuit cor-rectly, if the input voltage value gets very low the amplifier will be in saturationand the series regulator will not operate correctly. The deviation between thelowest input voltage value, for which the regulator stops to work for lower val-ues Vi,min, and the regulated output voltage Vo is called the drop-out voltageVdo = Vi,min − Vo. The drop-out voltage value can be very low, in that case theregulator is called low drop-out (LDO) voltage regulator, generally the utilizedpass transistor is NMOS or pnp bipolar transistor for LDO regulators [10].

Advantages and Disadvantages

The linear regulators are easier to implement on-chip, have smaller size and costless than switching regulators. In addition, they provide a good response to thechanges in load current and offer a low noise clean output. Hence, they are moreappropriate for designs that demand fast input-output reaction and output withlow noise.

One of the disadvantages of using linear regulators is the low efficient powerconversion which decreases, in a linear proportional way, with the ratio Vout

Vin. In

addition, the linear regulators cannot create several output voltages and cannotup-convert the voltage [5].

2.3 Selecting the Architecture 19

2.3 Selecting the ArchitectureSelecting the architecture is usually based on the specifications and the require-ments needed. Comparing the advantages and the disadvantages of differenttopologies helps choosing a suitable architecture.Regarding this project, table 2.1 shows the features of switching and linear regula-tors in comparism with the requirements or preferences for the smart dust project.Considering the main challenge in this thesis, which is how to deal with high volt-ages using 65-nm core transistors, makes circuits of simpler architecture highlydesirable.

A look back on the table shows that linear regulators are more suitable forthis project. To avoid shunt regulators faults mentioned in 2.2.2 the series voltageregulator shown in figure 2.3 is used.

Figure 2.3. The selected voltage regulator architecture for the smart dust mote.


Linear Regulators Switching Regula-tors

The Requirementsand preferences forthis project

smaller size and cost,easier to implementon-chip

usually need some off-chip components andmore complicated ar-chitecture

the regulator is goingto be implemented in amote which makes thefully on-chip implementa-tion preferable

fast transient response slower transient re-sponse

fast transient response ispreferred

cannot step up the in-put voltage

able to step up voltages stepping up voltages is notneeded

low efficiency more efficient powerconversion

since the energy willbe harvested from thesurrounding environmentpower loss is not themain concern rather thansupplying a regulateddesired voltage level

low-noise output contains filter compo-nents which producenoise

low-noise output supply ispreferred since there aredigital and analog compo-nents

cannot create severaloutput voltages

several output voltagescan be created fromone input voltage

several output voltages atthe same time are not re-quired. However, the out-put voltage level is pro-grammable and can bechanged

Table 2.1. Comparison between switching and linear regulators features and the re-quirements and preferences for the smart dust project.

Chapter 3

Theory Background forAnalog Design

During this chapter, major aspects of the analog design in general, and the regu-lator in particular, are discussed. The short channel Metal Oxide SemiconductorField Effect Transistor (MOSFET) model, the difference between I/O and coretransistors and the main lifetime affecting mechanisms are explained. Furthermoreseveral operational amplifiers are discussed towards choosing the most suitable am-plifier architecture for the regulator. Finally, useful current mirror topologies andother operating condition issues are shown.

3.1 Modeling the Short Channel MOSFETRecently, the new CMOS transistors process has a minimum length much smallerthan 1µm, more specifically, in the nano-meter range. The square-law current-voltage relation which was based on the gradual channel approximation can nothold for short channel devices, since it can not be assumed anymore that theelectric field under the gate oxide is one dimensional. Also, the potential of thecarriers that are moving between the channel and the drain could reach saturation,causing an effect called carrier velocity saturation νsat, where the velocity of thecarriers refrain from incrementing with the increment of the applied electric field.The electron mobility µn is the electron drift velocity divided by the applied electricfield [11]

µn = ν

E(3.1)

The current-voltage relation becomes in the saturation region of short channeldevices as the following:

ID = W · νsat · C ′ox(VGS − VTHN − VDS,sat) (3.2)Taking into consideration that, for high electric fields, the mobility can be writtenas: µn = νsat

E and V (L) = VDS,sat when the MOSFET is in the saturation region.

21

22 Theory Background for Analog Design

It is also worth mentioning that VDS,sat for long-channel transistors can befound using the equation VDS,sat = VGS−VTHN while this equation does not holdfor short channel MOSFET transistors. VDS,sat for short channel devices is thedrain-source voltage drop VDS when the transistor is in the saturation region andVGS − VTHN is denoted as the gate overdrive voltage Vovn.

Vovn = VGS − VTHN 6= VDS,sat (3.3)

From equation 3.2 it can be seen that the drain current is linearly proportional tothe gate-source voltage VGS for short channel transistors working in the saturationregion. While for long-channel MOSFET transistors it is known that the draincurrent is proportional to the square of VGS .Equation 3.4 shows the drain current of long-channel transistors operating in thesaturation region:

ID,sat = K · Pn2 · W

L· (VGS − VTHN )2 (3.4)

Finally, another usable expression for the short channel MOSFET transistors isthe drive current per width Ion or Idrive which is defined as:

Ion = Idrive = νsat · C ′ox(VGS − VTHN − VDS,sat) . . . µA/µm (3.5)

Even though the drive current for short channel devices can be approximated usingthe previous equations, it is usually measured [11].

3.2 Core Transistors and I/O TransistorsThe evolution of CMOS technology yields smaller transistors that are faster andmore economical in terms of area and power consumption. However, since transis-tors have scaled down to nanometer dimensions, decreasing the power supply hasbecome essential in order to keep a reliable performance and a longer life time.

With the consideration of lower cost and higher speed, a highly integrated sys-tem on chip is desired for most of the portable devices. Using 65-nm and 45-nmcore transistors allows for more functions to be implemented in the unit area. Thenominal power supply for 65-nm transistors is 1.2 V and it is reduced further for45-nm transistors.For digital circuits, the lower power supply voltage reduces the power consumptionaccording to the following formula:P ∼ afCV 2

DD ; a: activity factor, C: total node capacitance, f : operating fre-quency.For some analog circuits higher power supply reduces the power consumption [4].

In the smart dust project, the 65-nm core transistors are used to build theregulator, for which the unregulated power supply can range between 1.8 to 3.6 V.This posses a challenge on how to deal with voltage drops higher than the nominalsupply voltage of the 65-nm transistors without affecting the lifetime [4].Several solutions exist to overcome this issue:

3.2 Core Transistors and I/O Transistors 23

- One possible solution is to produce transistors that can tolerate high voltagesthrough technological solutions such as multiple gate oxides. The main draw-back of this solution is the cost, since more processing steps and masks arerequired.

- Another solution is to use extended-drain transistors which does not requireextra processing steps but affects the performance-per-area.

- Finally, solutions to use only core transistors can be achieved through advancedcircuit solutions, which limit the voltage drops on each transistor to tolerablevalues that guarantee adequate lifetime [12].

For MOS transistors, the lifetime is related to the strength of the electric fieldin the device. Transistors that have minimum length can work for at least thenominal lifetime when the nominal supply voltage is applied [12].

Restraining the electric field on transistors with low voltage tolerance is vitalfor the lifetime when they are used in circuits with high voltages. This is usuallydone by sacrificing more area. The most vital electric fields that affects the lifetimeof the transistors are the vertical, the lateral and the electric fields across junctions.The representing mechanisms of those electric fields which affect the life-time arerespectively: oxide breakdown, hot-carrier degradation and junction breakdown[12].

Oxide Breakdown: When applying an exaggerated electric field over theoxide, a decay of oxide happens as a consequence of the currents that flow acrossthe oxide. When the capacity of charges exceeds a limit in a specific area of theoxide it will be destroyed, meaning that an oxide breakdown has happened.When the gate oxide is broken, the gate current will increase and the device be-comes uncontrollable by the gate voltage. The oxide breakdown is also called TimeDependent Dielectric Breakdown (TDDB) [4].The lifetime of the transistor is greatly affected by the oxide current that is gener-ated by the electric field applied over the oxide. It has been shown that by limitingthe electric field over the oxide to 5.5 MV/cm an adequate oxide lifetime couldbe achieved. This value usually means that the oxide voltage tolerated can be upto 20% higher than the nominal supply voltage of the process. The source-gatevoltage Vsg is equal to the oxide voltage at the source.Similarly, the drain-gate voltage Vdg equals the oxide voltage at the drain side ofthe transistor. When the transistor is ON, the oxide voltage in the area betweenthe drain and the source is between Vdg and Vsg. When the transistor is OFF abulk-gate voltage is applied and partly divided across the gate oxide and a de-pletion layer in the silicon, a big part of the voltage is applied over the depletionlayer [12].

Hot-Carrier Degradation: The second lifetime affecting mechanism is thehot-carrier degradation or hot carrier injection (HCI). It occurs when the transis-tor is in the saturation region and the drain-source voltage is big, which will givea high energy to the carriers moving from source to drain and cause them to turn


hot near the drain zone.The transistor performance is affected from the hot carriers that cause slow degra-dation in the gate oxide. The slow degredation happens when the hot carriersget into the gate oxide zone near the drain during their collision with the siliconlattice. The HCI results in a small variation in the threshold voltage of the tran-sistor [4].The magnitude of the hot-carrier degradation effect primarily depends on thetransistor’s length and the biasing conditions. [12].

• The lifetime is exponentially related to the drain-source voltage Tlife ∝exp(A/Vds). For deep submicron processes A = 80-120 V, Vds should beaccording to the worst case settings.

• The length does not affect the lifetime strongly, the relation can be approx-imated by: Tlife ∝ LB ; B = 1-5.

• The lifetime has got a more complicated relation with the gate-source volt-age. When the gate-source voltage is low, the transistor is turned off leadingto a zero drain-source current which in consequence means no hot carriers.Furthermore when the gate-source voltage is very high and the drain-sourcevoltage is constant there will be no hot carriers since the transistor is op-erating in the linear region. However, the hot-carrier degradation becomesmaximum for the region where the drain current is large and the transistoris well in the saturation region, resulting in a minimum lifetime.

Junction Breakdown: The junction breakdown happens when applying volt-ages that are at least several times larger than the nominal supply voltage for thenew CMOS processes. For this reason there is no need to care much about it forcircuits that work at voltages that are 2.5 times higher than the nominal supplyvoltage.Nonetheless, the junction weakly collapses when applying reverse voltages thatare higher than the nominal supply voltage. Incrementing the reverse bias voltagelevel causes the reverse diode current (the leakage current) to increase.

Another mechanism that affects the lifetime is PMOS Negative Bias ThresholdInstability (NBTI). NBTI is a serious issue for thin oxide PMOS. When the neg-ative gate-source voltage pressures the PMOS, the threshold voltage is increasedcausing a decrement in the drain current and a decreased transconductance. Theeffect of NBTI becomes worse for shorter channel lengths and higher temperatures.

Achieving a longer life time demands reducing the effect of NBTI. This isdone by keeping the transistor in the dynamic condition, where biasing the gateis varied between high and low cases, compared to the NBTI effect in the staticcondition [12].

Table 3.1 shows a comparison between 65-nm thin oxide (core) transistors and0.25µm thick oxide (IO) transistors regarding the different reliable voltages thatassure a sufficient lifetime.

3.2 Core Transistors and I/O Transistors 25

IO NMOS 3.8 V

Oxide Breakdown PMOS 4.1 Vor

TDDBCore NMOS 1.7 V

PMOS 1.7 V

IO NMOS 3.0 V

Hot-carrier degradation PMOS 3.3 VorHCI

Core NMOS 1.4 V

PMOS 1.4 V

IO PMOS 4.0 VNBTI

Core PMOS 1.4 V

Table 3.1. The tolerable voltages regarding the affecting lifetime mechanisms for atypical 65-nm CMOS technology [4].


The maximum supply voltage tolerated for 65-nm core transistors is 1.4 V inorder to assure the desired lifetime, as shown in table 3.1. The voltage is limitedby the PMOS NBTI and MOS HCI [4].

3.3 Operational AmplifierA lot of analog and mixed-signal circuits contain an operational amplifier (opamp). Operational amplifiers have got various applications. Ranging from simpleto more complex designs, op amps are used for different purposes such as filtering,generating DC bias or amplifying signals.While CMOS technologies are scaled down and the demand for less power con-sumption is increased, the design of the op amp presents a big challenge for analogand mixed-signals designers [13].

Generally in the regulator, the driver stage (usually an op amp) is the mostvital part of the regulator. It is very critical for the regulator design to build ahigh performing amplifier so the desired load and line regulations are met. Inaddition, high performance for various temperatures is achieved by designing agood amplifier. Each of the amplifier specifications play a role in the performanceof the regulator, such as the DC gain, the bandwidth, the phase margin, etc.

It is usually desired for amplifiers to have a significant DC gain, a sufficientbandwidth in order to attain a good transient response and a good phase margin(typically larger than 45 degrees) to obtain stability for the closed loop circuit.

General Considerations: The operational amplifier in general is a differ-ential amplifier with a high-gain. It is relative how high the amount of gain canbe, but it should be a sufficient value for a specific application. The op ampsare mainly used with a feedback system and the open-loop gain is decided by thedesired accuracy of the closed-loop circuit [13].Previously, op amps were designed more standardly to fulfill a lot of applicationrequirements, e.g. building op amps with a very high voltage gain and a highinput impedance to achieve a close to "ideal" op amp.However, this was possible by sacrificing other performance features such as speedand power consumption. On the contrary nowadays, designing the op amp is doneby taking into account the trade-offs between the parameters and the need foroptimization in order to achieve a sufficient performance. Therefore, it is very im-portant to decide the sufficient value for each parameter and to choose the suitabletopology according to the requirements of the application [13].

Since the design of the op amp contains a lot of transistors and a big numberof parameters that affect the performance. It is usually difficult to know whereto start from and how to select the values for the design parameters. Actually inpractice, the method of designing an amplifier mainly relies on the requirementsof the circuit, i.e. the method to design a high-gain op amp could be very dif-

3.3 Operational Amplifier 27

ferent from the method to design a low-noise op amp. Thus, the most importantparameters for the performance will decide the design procedure [13]. Several opamp topologies will be briefly explained in the following sections.

3.3.1 Two-Stage Operational AmplifierThe two-stage op amp is a very popular topology that has been widely used forbipolar and CMOS op amps [14]. It is usually used to obtain a high-gain and awide output swing. The high gain is provided by the first stage of the amplifierand the large output swings by the second stage [13]. However, the two-stage opamp is, by some means, more appropriate for resistive loads [14].

Typically, the first stage has a differential-input and single-ended output. Thisstage could be any topology of amplifier, while the second stage is usually acommon-source gain stage that grants the largest output swings. The common-source stage is connected to an active load.The first stage could also be fully differential if a two-stage fully differential am-plifier is desired. Furthermore the first stage could be differential while convertingthe differential output stage to a single-ended output in the second stage. Figure3.1 shows a two-stage op amp.

3.3.2 Cascode Operational AmplifierThe differential cascode amplifier can be used to acquire higher gain. Figure 3.2shows an example of a differential cascode op amp topology. This circuit is alsocalled "telescopic" cascode op amp.The circuit gain could be estimated to be in the class of gmN ·

[(gmN · r2

ON

)‖(gmP · r2

OP

)].

However, the main disadvantages of using the telescopic op amp is the limited out-put swing and the complexity when connecting the output to the input to build abuffer. To overcome those issues the folded-cascode op amp could be used [13].

3.3.3 Folded-Cascode Operational AmplifierThe main concept of the folded-cascode op amp is to cascode the differential inputtransistors using a different type of transistors than the input pair transistors. i.e.using PMOS transistors to cascode NMOS differential input transistors and viceversa. The compromise of using different type transistors gives an ability to theoutput signal to reach the same level of the input signal at the same bias voltagelevels.

Since the cascode methodology is used, a high output impedance is achieved.Consequently a good amount of gain is achieved because the product of the inputtransconductance and the output impedance decides the gain. The gain could bein the range of 700 to 3000. Figure 3.3 shows an example of a folded-cascode opamp circuit.


Figure 3.1. A two-stage operational amplifier circuit [14].


Figure 3.2. A cascode (telescopic) operational amplifier circuit [13].


Figure 3.3. A folded-cascode operational amplifier circuit [14].

3.3.4 Current-Mirror Operational Amplifier

The current-mirror op amp is also a very common topology that is widely usedfor on chip applications which do not have resistive loads. A decent gain could beachieved by designing current mirrors that have high output impedance.

Figure 3.4 shows a current-mirror op amp circuit where K is the rate betweenthe output current and the input mirrored current. Using higher mirror rateincreases the op amp transconductance which causes the unity gain frequency toincrease.The load capacitance plays a main role in limiting the unity gain frequency insteadof the high frequency poles. Increasing K to very high values makes it necessaryto increase the load capacitance in order to keep the circuit stable. Also, insome cases, a higher mirror rate causes the bandwidth to drop to smaller valuesdepending on the dominant poles. Since high speed is important, K should besmall if the load capacitance is small and the second pole is dominant.

The current-mirror op amp performance, regarding slew rate and bandwidth,is much better comparing to the folded-cascode op amp. This makes it moredesirable.


Figure 3.4. A current-mirror operational amplifier circuit [14].

3.3.5 Operational Transconductance Amplifier (OTA)

An amplifier is called operational transconductance amplifier (OTA) when all theinternal nodes (all the nodes in the circuit excluding the input and output nodes)of the amplifier have low impedances. It is normally more suitable to be used fordriving capacitive loads. Nevertheless, OTA could be used to drive resistive loadsby introducing a buffer stage. A good example of an OTA is the current-mirroramplifier shown in Figure 3.5.

As seen in Figure 3.5, all the internal nodes have low impedances, some of thenodes are diode connected devices and the others have a source connected to them.The highest value that the output current can achieve is K · Iss where K is themirror rate. This explains the slew-rate issues when the OTA is used as a firststage in an op amp.

The output impedance of the ideal OTA should be infinite, meaning that all ofthe output current proceeds in the capacitive load and no current proceeds in theoutput impedance of the OTA. An ideal OTA can be represented with a voltage-dependent current source, it is sometimes called a GM stage [13].

The previous OTA output impedance could be increased by cascoding thecurrent mirrors. Figure 3.6 shows the suggested circuit to increase the output


Figure 3.5. A simple current-mirror operational transconductance amplifier circuit [11].


impedance. Also, the tail current source has been changed to four transistorsinstead of two.

Figure 3.6. A cascode current-mirror operational transconductance amplifier circuit[11].

The unity gain frequency is reduced when the load capacitance is increased,resulting in a better stability. The OTA gains more stability by increasing theload capacitance, contrarily to the two-stage op amp where big load capacitancecauses stability problems. In addition, the phase margin improves with larger loadcapacitance. Moreover, the OTA has a first-order step response.All of the those features make the OTA suitable for a lot of on chip applications,when it is configured in a closed-loop circuit.

3.3.6 Selecting a suitable Operational AmplifierAs mentioned in section 3.3, when designing an amplifier, the designer bumpsmainly into the problem of where to start from since there is a lot of effectingparameters. Therefore a general guideline is to go through the needed requirementsin order to select a suitable architecture.


The DC-gain, the bandwidth, the phase margin and the power consumptionare the main features to consider in the op amp performance when it comes to theregulator design.

Different op amp topologies have been shown, their advantages and their draw-backs have been briefly mentioned. It has been concluded that the current mirrorOTA shown in Figure 3.5 is the most suitable architecture to be implemented inthe regulator circuit, since the current mirror OTA is able to supply the requiredDC-gain, bandwidth, etc. And it is more suitable for on chip applications thathave capacitive loads. In the regulator circuit, the output of the amplifier will beconnected to the gate of an NMOS which requires a high output impedance.

However, the amplifier needs to deal with supply voltages that are higher thanthe nominal supply voltages of the used transistors. Moreover, obtaining a decentamount of DC gain is needed. Therefore, cascoding the current mirrors in Figure3.5 is required.The design of the amplifier will be discussed in chapter 4 while the next sectionwill briefly present some current mirror techniques.

3.4 Current Mirrors Techniques3.4.1 Basic Current MirrorsFigure 3.7(a) shows a basic current mirror circuit. Assuming that both transistorsare equal in size and are operating in the saturation region then the current goingthrough Q1 ,Iin, should be equal to the current going through Q2 ,Iout, since bothtransistors have the same gate-source voltage Vgs. It has also been assumed thatthe transistors’ output impedance is infinite. This means that the input currenthas been mirrored or copied to the output branch.The current values are sligthly different when considering again the precise outputimpedances of the transistors. The transistor with the higher drain-source voltagedrop will have the higher current. Furthermore, the fact that the transistors’output impedances are not infinite means that the the current mirror’s small-signal output impedance is also confined.

The current mirror’s small-signal output impedance is the small-signal impedanceseen from the drain of Q2, like shown in Figure 3.7 (b) The value of this impedanceis estimated to be rds2 after approximating Q1 output impedance to 1/gm1. Inorder to obtain a higher output impedance and eventually a more 'ideal' currentmirror, other techniques such as cascode current mirrors are used [14].

3.4.2 Cascode Current MirrorsAs mentioned in the previous section, cascode current mirrors have a higher small-signal output impedance. Figure 3.8 shows an example of a cascode current mirrorcircuit. Similarly to the basic current mirrors, the output impedance seen from thedrain of Q2 is rds2. Assuming Q4 is a current source with a source-degeneration1

1basic current mirror that has resistors connected to the source of the transistors

3.4 Current Mirrors Techniques 35

Figure 3.7. (a) A simple current-mirror. (b) A small-signal model of the current-mirrorcircuit shown in (a) [14].


resistor rds2, the output impedance can be written as:

rout = rds4 [1 + rds2 (gm4 + gs4 + gds4)] ∼= rds4 (rds2 · gm4) (3.6)

Figure 3.8. A cascode current-mirror circuit.

This means that the output impedance of the cascode current mirror is largerthan that of the basic current mirror with a factor of gm4 · rds2. This value is themaximum gain that can be achieved by a single-transistor gain stage. It can rangefrom 10 to 100, determined by the transistors dimensions, currents and the usedtechnology.

The main drawback of the cascode current mirror is that it lowers the availableupper-limit which the output-signal swing can reach while keeping the transistorsin the saturation region.It is known that in order to let NMOS operate in the saturation region, the drain-source voltage should be: Vds > VGS − Vtn = Veff .Therefore the minimum output voltage that both transistors Q4 and Q2 can stilloperate in the saturation region with is Vout = 2Veff , assuming equal dimensionsand gate-source voltages for both transistors. However, the minimum allowedvoltage for Vout is Vout = 2Veff+Vtn which is a Vtn higher than the usual minimum


value. This problem becomes severe for technologies that have relatively smallpower supply voltages.

3.4.3 Wide-Swing Current MirrorsAs seen in section 3.4.2, cascode current mirrors are required to obtain a higheroutput impedance, especially when it comes to designing an operational ampli-fier using recent transistor-technologies with short channel lengths. The outputimpedance is reduced proportionally with the channel length which makes thedesign of an amplifier with decent gain a big challenge. On the other hand, em-ploying typical cascode current mirrors such as illustrated in Figure 3.8 reducesthe possible signal swings.This presents another problem, namely that the power supplies of new technolo-gies are reduced proportionally as well. To overcome this problem another currentmirror technique known as "Wide-swing cascode current mirror" is used.Figure 3.9 shows a wide-swing current mirror circuit. This circuit does not reducethe signal swing like the cascode current mirror shown in figure 3.8. The mainprinciple of this technique is to set Vds of Q2 and Q3 to the lowest value wherethe transistors are still in the saturation region. In this architecture Q3 and Q4behave like one diode-connected transistor for biasing VGS of Q3. The purposeof using Q4 in this architecture is to equal the drain-source voltages of Q2 andQ3 and thus having equal input and output currents. The output current valuewould be less than the input current in case Q4 was not used because the outputimpedance of Q2 and Q3 is not infinite. In addition, Q4 has a small contributionon the circuit’s function.

The lowest output voltage tolerated for the wide-swing current mirror circuitshown in figure 3.9, before the transistors move to the linear region, is:

Vout > (n+ 1)Veff (3.7)

where n is a number used for the transistors sizes as seen in Figure 3.9. By choos-ing n value to be 1, the minimum output voltage becomes: Vout > 2Veff .

Some points regarding the circuit shown in Figure 3.9 are presented as follows:The dimensions of Q5 are usually chosen slightly smaller than the value shown inFigure 3.9 by experienced designers. The reason is to set Vds of Q2 and Q3 to avalue that is a little bit higher than the minimum value which is needed to let thetransistors operate in the saturation region.The higher voltage is desirable when taking into account practical issues such asthe gradual move for real transistors from linear to saturation regions, also it isdone to shift second-order effects caused by the body of transistors Q1 and Q4.The circuit’s part of Ibias and Q5 could be adjusted to reduce the current goingthrough that branch while maintaining the same current density, hence the samegate-source voltage, in order to reduce the power consumption.Another typical adjustment is to select the value of the transistors’ length so thatVds is minimized, except for Q1 and Q4 for which the channel length value is usu-ally selected to be twice the lowest available channel length. This is done because


Figure 3.9. A wide-swing current-mirror circuit.


those transistors usually handle higher voltage drops. In addition, it helps gettingrid of short channel effects. Selecting the lowest channel length value for Q2 andQ3 results in a better frequency response.

In conclusion, this current mirror technique is the most preferred one to beused nowadays in CMOS analog circuits.

Chapter 4

Designing the Regulator

This chapter handles the design of the regulator, including the design considera-tions, calculations and the test benches used for simulation.

Before discussing the design, figure 4.1 previews the general regulator circuitthat was selected in section 2.3. The voltage supply is in the range between 1.8to 3.6 V while the regulated output voltage is a selectable voltage between thefollowing outputs [0.9, 0.8, 0.7, 0.6, 0.5 V]. The values of the resistors and thereference voltage have not been specified yet.

A reference voltage is needed in order to achieve a regulated output. The ref-erence voltage is obtained from a band-gap reference circuit. It is ideally constantand independent of both, power supply and temperature changes.For an ideal constant reference voltage, the output regulated voltage will be inde-pendent from process and temperature variations, since it is related to the resistorsproportion which is invariant with temperature and process fluctuations of the re-sistors. Also, it is invariant with the amplifier open-loop gain which is stabilizedusing a feedback [11].Considering an ideal amplifier (with infinite gain), the regulated output voltage isgiven by the following equation:

VOUT = VREF · (1 + R1

R2) (4.1)

Considering again a non-ideal amplifier, meaning that v+ 6= v− and assuming thevalue of the amplifier open-loop gain equals to A, then VOUT can be written as:

VOUT = Vamp,out − VGS

⇒ VOUT = A · (v+ − v−)− VGS

but v+ = VREF and v− = VOUT · R2R1+R2

⇒ VOUT = A · (VREF − VOUT · R2R1+R2

)− VGS

41

42 Designing the Regulator

Figure 4.1. The voltage regulator circuit.

4.1 The Resistors Ladder and the Transmission Gates 43

⇒ VOUT = A · VREF − VGS1 +A · R2

R1+R2

(4.2)

For very large values of A, equation 4.2 becomes equal to equation 4.1. This re-sult shows that designing an amplifier is very critical for the regulator. The more'ideal' the amplifier is, the better output regulated voltage is achieved [11].

Back to equation 4.1, the highest output voltage required in the specificationis 0.9 V, while the lowest output voltage required is 0.5 V. In the case of an idealamplifier, the node between R1 and R2 has a voltage that is equal to the referencevoltage. Therefore the reference voltage value should be selected to be less than0.5 V. By selecting the value of VREF = 0.3 V and assuming that the currentgoing through the resistors is 0.3µA, then the value of the resistor R2 becomes:

R2 = VREF − 00.3 · 10−6 = 1MΩ (4.3)

Hence, the value of R1 is decided according to the selected output regulated volt-age. For 0.9 V output R1 is calculated according to equation 4.1 [11].

R1 = R2 · (VOUTVREF

− 1) = 1MΩ · (0.9V0.3V − 1) = 2MΩ (4.4)

4.1 The Resistors Ladder and the TransmissionGates

As mentioned previously, the value of R1 varies with the output voltage, since fivedifferent output voltages are required, there will be five corresponding values forthe resistor R1. The values of R1 are calculated as follows:

R1,0.9V = 2MΩ

R1,0.8V = 1MΩ · ( 0.80.3 − 1) = 1.667MΩ

R1,0.7V = 1MΩ · ( 0.70.3 − 1) = 1.333MΩ

R1,0.6V = 1MΩ · ( 0.60.3 − 1) = 1MΩ

R1,0.5V = 1MΩ · ( 0.50.3 − 1) = 0.667MΩ

One possible solution to get all of the required output voltages is to divide R1into several resistors connected in series with each other. Where the sum of allthe resistors is the highest required value of R1. i.e: R1 is selected to be 2MΩand divided into the following series resistors [0.667, 0.333, 0.333, 0.334, 0.333MΩ].Figure 4.2(a) illustrates the resistors connection.

However, when selecting an output voltage less than 0.9 V, one or more resistorsneed to be shortcut to avoid increasing the load resistance. Therefore, transmission


gates are used in order to shortcut the undesired resistors for the output voltagevalues less than 0.9 V.Each resistor is connected in parallel with a transmission gate. The transmissiongate is controlled by a control signal (ctrl) that is connected to a multiplexer forselecting the desired output voltage. Figure 4.2(b) shows the connection of thetransmission gates with the resistors.

Figure 4.2. (a) The resistor ladder for several output values. (b) The transmission gateplacing in the regulator circuit.

The transmission gate works as a switch which is controlled by a control signal,i.e. it behaves like an open circuit or a shortcut, depending on the control signal.Each transmission gate consists of two transistors, an NMOS and a PMOS. Thosetransistors are always in the same state, either 'on' or 'off'. This can be doneby biasing the gates of the transistors in an opposite way, i.e. when one of thetransistors has a 'high' signal applied on its gate, a 'low' signal is applied on thegate of the other transistor. This can be achieved with the same ctrl signal usingan inverter.

When the ctrl signal is 'high' the NMOS state is 'on' and the PMOS is alsobiased to be in the state 'on' due to the inverted ctrl signal applied on its gate.This yields a very small on-resistance, i.e. the switch is closed. Meaning that allthe signal passes through the transmission gate. Hence, the parallel resistor is

4.2 Designing the OTA 45

shortcut.When the ctrl signal is 'low' then both transistors are 'off' in the same manner.This results into an almost infinite high-impedance by the transistors, i.e. theswitch is open. Meaning that all the signal passes through the resistor in parallelwith the transmission gate [15].

Figure 4.3 illustrates the whole transmission gate circuit, taking into consider-ation that the 'IN' and 'OUT' nodes are connected in parallel with the resistorsas shown in figure 4.2(b).

Figure 4.3. The transmission gate circuit [15].

The transistors sizes were selected to be of minimum size, i.e. the length is0.06µm and the width is 0.675µm. Since the transmission gates are connected inparallel with relatively large resistors, it was possible to achieve a good perfor-mance without needing to change the transistors dimensions. Simulations havebeen done to verify the performance of the transmission gates.

4.2 Designing the OTAAs mentioned at the beginning of chapter 4, designing the OTA is the most criticalpart of the regulator design. Building a good regulator circuit requires building ahigh performance amplifier.


In this project, the requirements which needed to be fulfilled by the OTA were tosupply a minimum DC gain of 30 dB and a phase margin larger than 45 degreesfor the whole input voltage range, using only core transistors.The main two points which had to be considered during the design were:

• The voltage drop on each core transistor should not exceed 1.4 V, in orderto guarantee a sufficient life-time.

• The input supply voltage is in the range 1.8 to 3.6 V. This means that thesupply voltage can get to its double minimum value. Obtaining the desiredDC gain and phase margin for such a relatively wide input range becomes achallenge.

The primary selected architecture that was used is the current mirror OTAshown in figure 3.5. However, some modifications were required in order to makeit suitable for the design.

Cascade current-mirrors were used to contain the voltage drops and to achievea higher gain. The input transistors should always be in the state 'on'. Sincethe input voltages are relatively low (0.3 V), an OTA with PMOS inputs had tobe used. Figure 4.4 shows the simple uncascoded OTA architecture with PMOSinput.

Figure 4.4. A simple current-mirror PMOS-input circuit.


The low level of the input voltages makes it very difficult to operate the inputtransistors in the 'saturation' region for higher supply voltages, which directly af-fects the DC gain. Therefore, the input levels were increased by using the circuitryshown in figure 4.5.

Figure 4.5. A circuit to increase the input level.

All transistors’ lengths were chosen to be 1µm in order to minimize the shortchannel effect. Handling the high voltage drops will be explained in the nextsection.

4.2.1 Cascading the OTACascading the amplifier, as mentioned in section 3.4.2, maximizes the gain thatcan be achieved by a single-transistor gain stage. Moreover, using cascoded currentmirrors increases the number of transistors in the same branch which is neededfor handling high supply voltages, since the voltage drop is divided over severaltransistors.The maximum supply voltage is 3.6 V while the maximum voltage drop on eachcore transistor is 1.4 V. This means that the minimum number of transistors in


one branch should be three.

The output of the amplifier is connected to the gate of the driving transistor.The driving transistor source voltage is the output regulated voltage which hasmaximum value of 0.9 V. It is known that Vgs should be larger than Vth in order tohave the transistor ON. For the core transistors used in this thesis, the thresholdvoltage for NMOS is approximately 0.3 V which means that the output of theamplifier should be at least 1.2 V in the case of 0.9 V output. This indicates thatthe maximum voltage drop on the PMOS transistors in the output branch of theamplifier is 2.4 V, which requires minimally two PMOS transistors to handle thatvoltage drop.

As mentioned in section 4.2, the input voltage levels are relatively low sincethe bandgap reference voltage is 0.3 V. The added level shifter circuitry seen infigure 4.5 increases the voltage level up to approximately 0.7 V, this makes thevoltage on the drain of the bias transistor equals to maximally 2.1 V. The biascurrent used is assumed to be 0.5µA in order to minimize the current consumption.

The current mirror principle, as explained in section 3.4, depends on a diode-connected transistor, i.e. the gate and drain of the mirroring transistor are con-nected together. For the same source, the drain voltage of the mirrored transistortends to equal the drain voltage of the mirroring transistor, making the transistoroperate in the saturation region.Based on the previous fact and the fact that the maximum voltage on the source ofthe input transistors is 2.1 V, it has been decided that cascading the bias currentcircuit is necessary. By tuning the sizes of the transistors and running simulationsit has been found that three PMOS transistors are needed for the bias circuit.The bias current circuit that consists of three cascoded current mirror PMOS tran-sistors is shown in figure 4.6. The bias current which is needed in the mirroredbranch is 25µA, 50 times greater than the current source used. This means thatthe mirror rate should be 50 in the ideal case, however, simulation results haveshown that the required mirror rate is 84.

The current passing through the mirrored bias branch is equally divided intothe input branches. Each branch of the input transistors has 12.5µA current goingthrough it.The current going through the output branch is decided to be 50µA, that is inorder to guarantee enough current is supplied to the load in case of unexpecteddrops in the input voltage. This means that the mirror rate from the right inputbranch (the positive input) to the output branch is four.

The left input branch current is mirrored to the output branch on two levels.First, it is mirrored to the left branch which is parallel to the output branch, thenit is mirrored to the output branch. The combination of both mirror rates shouldbe four.The mirror rate of the left input branch is decided to be one, making the upper


Figure 4.6. The cascoded bias current circuit of the OTA.

right mirror rate, from the left branch to the output, equals to four.

Considering the required output voltage and the fact that the value of thediode connected transistor’s drain voltage is equal to the mirrored transistor’sdrain voltage, it can be seen that three PMOS cascode transistors are needed inevery branch. This was concluded in a similar manner to the bias current mirrordesign.

When tuning the sizes of the transistors in order to achieve the desired voltages,it should be taken into consideration that the drain source voltage drop on thetransistor is minimized when the transistor is ON and vice versa. Also, as itis known, the PMOS transistors are ON when the voltage applied on the gate isminimum while the NMOS transistors are ON when the gate voltage is maximized.In order to balance the voltage drop on the transistors in the output and its parallelbranch, a third NMOS cascode level has been added to those branches. The voltagebetween the PMOS and NMOS transistors in the parallel branch is applied to thegates of those added transistors. Figure 4.7 shows the final design of the cascodedOTA used for the regulator.


Figure 4.7. The final circuit of the cascoded OTA.

4.3 The Pass Transistor

The pass transistor is the NMOS that has its gate connected to the output of theOTA, as shown in the general circuit of the regulator in figure 4.1. The outputof the regulator is the source of this NMOS and has a minimum value of 0.5Vand a maximum value of 0.9V . The drain is connected to the unregulated supplyvoltage which can be in the range of 1.8 to 3.6V . This means that the minimumdrain-source voltage drop for this transistor is 1.8 − 0.9 = 0.9V , while the maxi-mum voltage drop is 3.6− 0.5 = 3.1V .

Therefore, cascode transistors are required in order to handle the high voltagedrop on the pass transistor which guarantees a sufficient life time.The maximum voltage drop, as calculated at the beginning of this chapter, is 3.1Vwhich requires three core transistors to handle it. One of the three transistors isbiased by the OTA output and the remaining two cascoding transistors need tobe biased in a proper way.

4.3 The Pass Transistor 51

4.3.1 Biasing the Cascoding Transistors

The drain-source voltage drop across NMOS transistors can vary depending on thegate voltage. For a fixed current, biasing the NMOS transistors with a high volt-age leads to a low drain-source voltage and vice versa. The drain source voltagedrop on the two cascoding transistors should be minimum 1.7V , when the inputvoltage is 3.6V and the output regulated voltage is 0.5V .

The threshold voltage for the used NMOS core transistors is around 0.3V .This means that the minimum voltage at the drain of the pass transistor isVs + Vth = 0.9 + 0.3 = 1.2V . Hence the maximum drain source voltage dropacross the two cascoding transistors is 0.6V , in the case of 1.8V input voltage and0.9V output. This causes a voltage headroom issue which needs to be consideredduring the design.

To overcome this problem, the cascoding transistors should be biased withvoltages that vary with the input voltage, making their source-drain voltage varyaccordingly to fulfill the previous conditions. However, this means that the biasingvoltages should be decreased when the input voltage increases. Simulations haveshown that this condition is not possible to achieve for the given parameters.The simulations have been done by biasing the transistors with the OTA outputvoltage and introducing a level-shifter for each cascoding transistor, making thehighest voltage drop across the lowest transistor. The result, for the case of 1.8Vinput voltage and 0.9V output voltage, has shown that the cascoding transistorsmust be biased with voltages higher than the power supply. This is not possiblein reality.

Another possible solution is to make the drain voltage of the pass transistor1.2V constantly, making the voltage drop across the cascoding transistors rang-ing between 0.6 and 2.4V , depending on the input voltage. However, providing aconstant 1.2V voltage implies that a regulated or a referenced voltage needs to beobtained somehow. This might be possible to achieve theoretically by building an-other bandgap reference or regulator circuit which supplies this voltage constantly.However, the design area, power consumption and other parameters are affectedsignificantly. Therefore, the goals and requirements of the general project need tobe reconsidered before considering this as a proper solution.

Other solutions for this problem could exist but considering the limited timefor the research of this thesis, the core pass transistor was substituted with a thick-oxide NMOS which can handle the maximum voltage drop temporarily. All thesimulation results presented in chapter 5 were obtained from simulations includinga thick-oxide pass transistor.


4.4 The OTA Test-BenchFigure 4.8 shows the testbench of the OTA. The SignalToDiff box is used togenerate one signal on both ends so the OTA inputs are fed with a commonsignal, the load capacitance is 1pF , the VDD voltage source is the unregulatedsupply voltage which ranges between 1.8 and 3.6V . The reference current IREFhas a value of 500nA.

Figure 4.8. The test bench circuit of the OTA.

4.5 The Regulator Test-BenchFigure 4.9 shows the testbench used for running simulations of the regulator circuit.A 100pF capacitor is added to the output as a load capacitance, since the outputof the regulator is connected to many devices in the mote.The VDD voltage source is the unregulated supply voltage which ranges between1.8 and 3.6V . The reference voltage VREF is the bandgap reference voltage.The pulled current by the load is simulated using a PVCCS2 device which isobtained from CADENCE’s analog library. This device pulls current according tothe voltage VLOAD as seen in the figure. The maximum voltage that can be pulledis selected to be 50µA direct current and 100µA pulse-wave current, as has beenspecified in the requirements. When VLOAD is 1V the maximum specified currentis pulled and when VLOAD is 0V no current is pulled.

4.5 The Regulator Test-Bench 53

Figure 4.9. The test bench circuit of the regulator.

Chapter 5

Simulation Results

This chapter shows the performance of the regulator through simulations whichwere done using CADENCE. The results for various cases of simulations showwether the design is able, or close, to meet the requirements using a thick-oxidetransistor as the regulator’s pass transistor.

5.1 Voltage Drop Simulations

During the design it was considered that each branch in the OTA should containenough transistors in order to handle the maximum input voltage. However, thevoltage drop is not equally distributed on all the transistors in a branch. Thismeans that some transistors can have voltage drops higher than their tolerablevoltage.

There are several ways to change the voltage drop on a transistor, e.g. changingthe dimensions of a transistor. It should be taken into consideration that changingone parameter can affect the whole circuit. Therefore the voltage drops on everytransistor should be looked at during the simulations. Many simulations wereexecuted to assure that the voltage drop on each transistor will never exceed 1.4V.

Figure 5.1 shows the voltage drops on all the transistors of the OTA during thesimulation of the regulator. The simulation is done for the highest unregulatedvoltage which is 3.6 V and with maximum current pulled by the load.Changing the load current can affect the voltage drops in some cases. Figure 5.2shows the simulation results when the unregulated voltage is 3.6 V and there is nocurrent pulled by the load. It can be seen that the voltage drops on the transistorsof the OTA are slightly different from the full-load case shown in figure 5.1.

55

56 Simulation Results

Figure 5.1. The voltage drops on all the transistors of the OTA when the maximumcurrent is pulled by the load.

Figure 5.2. The voltage drops on all the transistors of the OTA when there is no currentpulled by the load.

5.2 DC Load Simulations 57

5.2 DC Load SimulationsAccording to the requirements, the regulator should be able to handle the DC loadcurrent changes between 0 and 50µA. Usually, changes in the load current causechanges in the output regulated voltage.In order to capture the output voltage changes, the output error has been calcu-lated during simulations. It generally indicates the error percentage in the outputvoltage which is introduced due to changes in some parameters. For the simu-lations that have been executed, the bandgap reference voltage used is an idealvoltage source. In practice, the reference voltage is obtained from a bandgap ref-erence circuit which usually introduces an error in the output voltage. Most ofthe devices can handle 10% error from their nominal supply voltage. Therefore,the error in the output voltage level generated by the regulator which can be tol-erated is decided to be maximally 5%. The output error for 0.9 V output voltageis defined in the following equation:

OutputError[%] =√

(Vout − 0.9)2

0.9 · 100 (5.1)

Figure 5.3 shows the output error for the unregulated voltages in the range 1.8to 3.6 V, where the DC load is 50µA. Figures 5.4 to 5.8 shows the variations of the

Figure 5.3. The output error for all unregulated voltage values and maximum DC loadcurrent.

output error with the load current changes for all possible unregulated voltages.All the simulations are done for the output voltage case of 0.9 V.

It can be seen from the figures that the output error varies differently fordifferent input voltages. Furthermore, simulations have shown that the outputvoltage increases when the DC load decreases.As seen in figures 5.4 and 5.8, the output voltage error exceeds the tolerable limitfor the input voltages of 1.8 V and 3.6 V. Table 5.1 summarizes the simulationresults seen by the previous figures. The table shows the DC load that was handledby the regulator, where the output voltage error is less than 5%, for each inputvoltage.


Figure 5.4. The output error variation against DC load current for 1.8 to 2.1 V unreg-ulated voltage.


5.2 DC Load Simulations 59


Figure 5.7. The output error variation against DC load current for 3 to 3.3 V unregu-lated voltage.



It can be seen from the table that the regulator is able to supply a proper outputvoltage for the required DC load currents within the input voltage range 1.9 to3.3 V.

Input Voltage Load Current Input Voltage Load Current1.8 V Ca∼ 0 to 15 µA 2.8 V 0 to 50 µA1.9 V 0 to 50 µA 2.9 V 0 to 50 µA2.0 V 0 to 50 µA 3.0 V 0 to 50 µA2.1 V 0 to 50 µA 3.1 V 0 to 50 µA2.2 V 0 to 50 µA 3.2 V 0 to 50 µA2.3 V 0 to 50 µA 3.3 V 0 to 50 µA2.4 V 0 to 50 µA 3.4 V Ca∼ 13 to 50 µA2.5 V 0 to 50 µA 3.5 V Ca∼ 38 to 50 µA2.6 V 0 to 50 µA 3.6 V Not available2.7 V 0 to 50 µA

Table 5.1. The DC-load range where the regulator supplies a regulated output fordifferent input voltages.

5.3 AC Load SimulationsThe regulator’s AC load is represented by the digital circuits in the mote, theirconsumed current is in the form of periodic spikes. The consumed current rangesbetween 0 and 100µA. The digital circuits in the mote are assumed to operate ina relatively low frequency.A load current with 100µA spikes is added to the output of the regulator forsimulations, the spikes period is 50µs and the simulations are done with no DC

5.3 AC Load Simulations 61

load. Figure 5.9 shows the AC load current used during the simulations. The

Figure 5.9. The AC current load on the regulator output.

output error that is defined in equation 5.1 is used to show the AC load effect on theoutput regulated voltage. Figure 5.10 shows the output error for the unregulatedvoltages in the range 1.8 to 3.6 V, where the load current applied is the AC currentshown in figure 5.9.As seen in the figure, the output error exceeds 5% for input voltages higher than

Figure 5.10. The output error for all unregulated voltage values and AC current load.

3.3 V. Transient simulations have been done also for several input voltages to seethe output voltage signal form. Figures 5.11 to 5.14 show the transient response


for 0.9 V output voltage and 1.8, 2.7, 3.3, 3.6 V input voltages respectively.

Figure 5.11. The output voltage for 1.8 V unregulated voltage and AC current load.


As seen in the previous figures, the voltage level slightly drops at the spikespositions for 1.8, 3.3 and 3.6 V, while it seems like it oscillates for the 2.7 V.

5.3 AC Load Simulations 63




The change in the voltage level is maximally 0.002 mV for all tested input voltageswhich is extremely small and has no effect on the performance of digital parts inthe mote.

It can be concluded that the regulator is able to supply a proper output reg-ulated voltage for the required AC load current in the input voltage range 1.8 to3.3 V.

5.4 Transient Response SimulationsThe load transient response can be defined as how fast the regulator responds tochanges in the load. The regulator should be able to handle load changes in lessthan 10µs.For simulating load transients, the normal voltage source connected to the pvccs2device of the regulator testbench, shown in figure 4.9, is substituted with a voltagesource named vpwl which is obtained from CADENCE’s analog library. The vpwlused in the simulations has four parameters: time1, voltage1, time2 and voltage2.At the beginning (time1=0 s), the chosen voltage will be 0.5 V which refers topulling half of the maximum load current, i.e. 25µA. Then the voltage willrise/fall until it reaches voltage2 at time2. Figure 5.15 shows the form of thevpwl generated signal. The load transient response simulations are done for 0.9 V

Figure 5.15. The vpwl signal used to cause load transient.

output voltage and input voltages of 1.9 and 3.3 V, where the output error doesnot exceed 5%.Figures 5.16 and 5.17 show the output voltage transient signal where the load hasbeen changed from half-load to full-load DC current during 10µs.

As seen in the figures, the signal is stable at 12.8µs, just 2.8µs after the DCload current has been stabilized. This means that the output voltage signal isstabilized in less than 10µs.

5.4 Transient Response Simulations 65

Figure 5.16. The output voltage load transient response for 1.9 V, load changes fromhalf-load to full-load.

Figure 5.17. The output voltage load transient response for 3.3 V, load changes fromhalf-load to full-load.


In a similar manner, simulations are done again for 1.9 and 3.3 V input voltages,with the load current being changed from half-load to no-load current.

Figure 5.18. The output voltage load transient response for 1.9 V, load changes fromhalf-load to no-load.

Figure 5.19. The output voltage load transient response for 3.3 V, load changes fromhalf-load to no-load.

As shown in the figures, the regulator’s output voltage takes longer time before

5.5 Temperature Changes Simulations 67

it gets stabilized for the case of half-load to no-load.Figure 5.18 shows that the signal gets stable around 22µs, meaning that the tran-sient response for this case is more than 10µs. While figure 5.19 shows that thesignal is stable around 17µs, meaning that the regulator transient response isaround 7µs for 3.3 V input voltage.

The transient response simulation results can be summarized in table 5.2. Al-though the required transient response is not achieved in one case, the achievedresult is close to the requirements. There might be a room to improve that resultby tweaking the transistor sizes until the required transient response is achieved.

The simulation case Achieved resultLoad current changes from half-load to full-load for1.9 V input voltage

around 2.8 µS

Load current changes from half-load to full-load for3.3 V input voltage

around 2 µS

Load current drops from half-load to no-load for 1.9V input voltage

around 12 µS

Load current drops from half-load to no-load for 3.3V input voltage

around 7 µS

Table 5.2. A summary of the transient response simulation results.

5.5 Temperature Changes SimulationsThe wide variety of potential applications that employ the smart dust put moredemands on the mote to be able to operate in different environments. Therefore,the mote designed in this project is required to handle various temperatures. Theregulator circuit is required to operate in the temperature range -20 to 70 C.The following simulations show the effect of temperature changes on the regulatorperformance. Simulations are done for temperatures between -20 C and 70 C. Theresults are shown using the output error, which indicates the error in the outputvoltage for different input voltages, in a specific temperature. Figure 5.20 showsthe output error for temperatures between -20 and 70 C with 10 C step change.The input voltages are between 1.8 and 3.6 V and the selected output voltage is0.9 V. The applied DC load current is 50µA. It can be seen from figure 5.20 thatthe output error of temperature changes behaves differently with different inputvoltages.

• When the input voltage is between 1.8 V and 2.2 V, the lower temperatureshave higher output error.

• The temperature effect is minimized at the input voltage 2.2 V as the outputerrors of all temperatures drop down to zero.


Figure 5.20. The output error for temperatures between -20-70 C and input voltagesbetween 1.8-3.6 V.

• The output error increases accordingly until the input voltage 3.25 V wherethe temperature effect is minimized again.

• Finally, the output error of lower temperatures becomes lower than the out-put error of higher temperatures for input voltages 3.25 to 3.6 V, oppositeto the low input voltages.

Simulations that show the output error versus DC load current changes for varioustemperatures have been done as well. Figures 5.21 to 5.23 show the output erroragainst the load current changes for temperatures between -20 C and 70 C. Theselected input voltages are 1.8, 2.7 and 3.6 V respectively and the selected outputvoltage is 0.9 V.

It can be seen that the output error effect by the load current is differentfor the different input voltages. The output error decreases proportionally withthe load current for 1.8 V input voltage, while it doesn’t differ for 2.7 V and itdecreases when the load current increases for 3.6 V. It can also be seen that highertemperatures have less output error in figures 5.21 and 5.22, while they have higheroutput error for the 3.6 V input voltage.

Those temperature changes simulations which are done above show the regu-lator performance in different temperatures. It can be concluded from the simu-lations that the regulator is able to supply a regulated output voltage within allthe specified temperature range, for input voltages between 2 and 3.5 V.

5.5 Temperature Changes Simulations 69

Figure 5.21. The output error for temperatures between -20-70 C and DC-load between0-50 uA ,1.8 V input voltage.

Figure 5.22. The output error for temperatures between -20-70 C and DC-load between0-50 uA, 2.7 V input voltage.


Figure 5.23. The output error for temperatures between -20-70 C and DC-load between0-50 uA, 3.6 V input voltage.

5.6 Ctrl-bit Settings Simulations

All the previous simulations have been done with the selected output voltage 0.9V. According to the requirements, it should be possible to select different outputvoltage levels. Transmission gates are employed in the regulator design for thispurpose.Ideally, the regulator performance should be identical for the different outputs.However, this can change in reality. Therefore, simulations should be run to testthe performance of the regulator when selecting different output voltages. Thefollowing sections show the simulation results of different selected output levels.

5.6.1 0.5 V Output

The 0.5 V output voltage is obtained by turning the four transmission gatesON,ON,ON,ON. This changes the value of 'R1' accordingly to get the desiredoutput. Figure 5.24 shows the output error for 1.8 to 3.6 V unregulated voltageand full DC load. The output error increases significantly after 3 V, where thevoltage drop on the pass transistor becomes higher than 2.5 V. Figure 5.25 showsthe output error for input voltages between 1.8 and 3 V, the DC load current ischanging between 0 and 50µA. It can be seen that the output error exceeds 5% forinput voltages higher than 2.7 V when there is no load current pulled. The outputerror also differs significantly for higher voltages while it is relatively constant forlow voltages.

5.6 Ctrl-bit Settings Simulations 71

Figure 5.24. The output error for input voltages between 1.8-3.6 V and full DC load,0.5 V regulated voltage.

Figure 5.25. The output error for input voltages between 1.8-3 V and DC-load between0-50 uA, 0.5 V regulated voltage.


5.6.2 0.6 V OutputThe 0.6 V output voltage is acquired by configuring the transmission gates toON,ON,ON,OFF. Similarly to section 5.6.1, figures 5.26 and 5.27 show the outputerror with variations of input voltages and DC load current. The results are verysimilar to the 0.5 V output voltage configuration, but slightly improved regardinginput voltages. The output error exceeds 5% for input voltages higher than 2.9 V.

Figure 5.26. The output error for input voltages between 1.8-3.6 V and full DC-load,0.6 V regulated voltage.

Figure 5.27. The output error for input voltages between 1.8-3.2 V and DC-load be-tween 0-50 uA, 0.6 V regulated voltage.


5.6.3 0.7 V OutputSimilarly to the previous cases, the 0.7 V output voltage is acquired by setting thetransmission gates ON,ON,OFF,OFF. Figure 5.28 shows the output error versusinput voltage changes, where the load current pulled is full DC load current. It canbe seen in figure 5.28 that the output error is slightly improved for higher inputvoltages, comparing to lower output voltage levels. However, the output error doesnot increase proportionally with the input voltage as it slightly decreases between1.8 and 1.9 V, where the voltage drop on the pass transistor becomes less than 1.2V. Figure 5.29 shows the output error with variation of the DC load current for


input voltages between 1.8 and 3.3 V. It can be seen that the 1.8 V curve behavesdifferently from the others as it decreases and increases again.



5.6.4 0.8 V Output

Figure 5.30 illustrates the output error for the 0.8 V output voltage. The curveis decreasing from 1.8 to 2 V, then starts to slightly increase until 3.2 V whereit starts to increase sharply. The 0.8 V output voltage is obtained by settingthe transmission gates ON,OFF,OFF,OFF. The output error versus the DC load


current variation shows a different behavior for different input voltages. In Figure5.31, the output error increases when the DC load current is more than 10% ofthe full load for 1.8 V, while it increases after 25% for 1.9 V input voltage. Thelowest output error point moves towards higher load current by increasing theinput voltage. In figure 5.32, the output error for the highest voltages shownis increasing sharply when there is no DC load, similarly to the lower selectedoutputs.

Simulations show that the maximum input voltage, for which the regulator is stillable to provide a regulated output voltage, is increasing with the output increment.Table 5.3 shows the maximum input voltage and the adequate output regulatedvoltage. It can be concluded from all previous simulation results that the outputerror increases (in a proportional way) when the voltage drop on the pass transistoris higher than 1.2 V and lower than 2.4 V. The simulation results also show thatthe regulator achieves an output regulated voltage with an error that is within thetolerable range when the voltage drop on the pass transistor is lower than 2.5 V.The reason behind the increment of the regulator’s output error for low inputvoltages is the pass transistor used during simulations. The threshold voltageof the thick-oxide transistor used in this case is 0.7 V; higher than that of coretransistors. This causes a low drop out case for low input voltages. Since the passtransistor is NMOS, the voltage drop on the pass transistor Vds should be higherthan the gate over drive voltage Vovn = VGS−VTHN in order to set the transistor’sstate to ON. This explains the regulator’s inability to deliver an acceptable outputvoltage for the case of 1.8 V input voltage and 0.9 V output voltage.


Selected outputvoltage

maximum inputvoltage for whichthe output is reg-ulated

Comments

0.5 V 2.7 V Output error increases proportionally0.6 V 2.9 V Output error increases proportionally0.7 V 3.0 V Output error for 1.8 V input voltage is higher than

1.9 V input voltage0.8 V 3.1 V Output error for 1.8 V is higher than previous case

(0.7 V output voltage)0.9 V 3.3 V Output error for 1.8 V is more than 5 %

Table 5.3. The maximum input voltage versus the output voltage for which the regulatoris still able to provide a good output regulated voltage.

5.7 Sleep Mode Simulations

Sleep mode is a necessary feature for the smart dust application. It saves thebattery power and increases the mote’s life time. Cutting/connecting the power isdone through a switch. When there is no need for the mote to operate, the switchis switched off and the mote goes into sleep mode. The current consumption dur-ing the sleep mode should be zero according to the requirements. The switch usedfor the sleep mode is a transmission gate that is placed on the regulator’s inputvoltage line. The ctrl signal of the transmission gate is used to turn the sleepmode ON or OFF. In order to get back to normal mode from sleep mode, whenthere is no power going through the circuits of the mote, the ctrl signal shouldbe independent from the input voltage. One solution is to add a power on resetcircuit. The purpose of this circuit is to handle the ctrl signal until the regulatoris able to take over again. The simulations that have been executed serve to checkthe current consumption when the sleep mode is ON and OFF.

Figure 5.33 shows the current consumption of the regulator when the circuit isoperating. The current consumption rises with the input voltage. The results aremuch higher than the required current consumption. Further work needs to bedone to improve the current consumption of the regulator. Simulation results havebeen improved by tweaking the sizes of the transistors; other possible changes needto be investigated. Figure 5.34 shows the current consumption during sleep mode.The consumed current is a leaked current which is almost impossible to avoid.However, this current is insignificant compared to the actual current consumption.During simulations it was noticed that a better sleep mode current consumptionis achieved if the ctrl signal is higher than the input voltage.

5.7 Sleep Mode Simulations 77

Figure 5.33. The current consumption for the regulator when Ctrl equals VDD.

Figure 5.34. The current consumption for the regulator in sleep mode.


5.8 Power Down Simulations

The purpose of the following simulations is to check the behavior of the regulatorwhen the input voltage changes dramatically in a short time. Simulations havebeen done using vpwl voltage source, which is explained in section 5.4, as the inputvoltage. The input voltage changes from 1.9 V to 3.6 V at the specified time2.Figure 5.35 shows the output voltage signal during simulation with input voltagethat changes periodically every 10µs. As seen in the figure the maximum changein the output voltage is 40 mV.

Figure 5.35. The output voltage versus time during periodic VDD change every 10µs.

Figure 5.36 shows the simulated output voltage result when the input voltagechanges every 200µs with a pulse width of 1µs. The input voltage changes from1.9 V to 3.6 V.As seen in the figure, the maximum drop in the output voltage is only 4 mV. Thisresult can be explained by the regulator’s response to the changes in the inputvoltage; it is probably not fast enough to settle during 1µs. Hence, it can beconcluded that the output voltage stays almost constant if a power in the motedropped down for a short time. This guarantees safety for the other devices in themote in cases of power fluctuations.

5.9 Corner Analyze Simulations 79

Figure 5.36. The output voltage versus time during VDD change with period of 200µsand a pulse width of 1µs.

5.9 Corner Analyze SimulationsCorner analyze simulations were run in order to verify the regulator’s performancein different process variations. The transistor’ performance can differ dependingon the process variations. Hence, the whole design could be affected by the processvariations. Therefore running a number of simulations with different process casesmakes it possible to estimate the potential effects of the process variations on thedesign.The results shown below are achieved during simulations with several combina-tions of three different transistor process variations: typical, slow and fast. Inaddition to the case where all transistors process is typical, there have been eightdifferent simulations with eight different process variation possibilities that havebeen executed for this regulator design.Figures 5.37 to 5.45 show the output error against input voltage variations. Thecurrent pulled from the load is a full DC current and the selected output volt-age is 0.9 V. The figures represent the following process variation combinationsrespectively:

1. Typical

2. Fast-Fast-Fast

3. Slow-Slow-Slow

4. Fast-Slow-Typical

5. Slow-Fast-Typical


6. Fast-Slow-Slow

7. Slow-Fast-Slow

8. Fast-Slow-Fast

9. Slow-Fast-Fast

Figure 5.37. The output error for full DC load in corner analyze typical case.

Figure 5.38. The output error for full DC load in corner analyze fast-fast-fast case.

As seen in the figures, the graphs differ according to the process variations. Table5.4 shows the variation effect on the input voltage range, where the regulator is ableto supply a regulated voltage within the acceptable range. Different behavior ofthe output error can be clearly seen for the fast-fast-fast case and the slow-slow-slow case, where slow transistors improve the regulator performance for higherinput voltages.


Figure 5.39. The output error for full DC load in corner analyze slow-slow-slow case.

Figure 5.40. The output error for full DC load in corner analyze fast-slow-typical case.

Figure 5.41. The output error for full DC load in corner analyze slow-fast-typical case.


Figure 5.42. The output error for full DC load in corner analyze fast-slow-slow case.

Figure 5.43. The output error for full DC load in corner analyze slow-fast-slow case.

Figure 5.44. The output error for full DC load in corner analyze fast-slow-fast case.


Figure 5.45. The output error for full DC load in corner analyze slow-fast-fast case.

Corner analyze case The input volt-age range forwhich the out-put is regulated

Typical case 1.9 to 3.3 VFast-fast-fast case 1.9 to 3.3 VSlow-slow-slow case 2.0 to 3.6 VFast-slow-typical case 1.9 to 3.6 VSlow-fast-typical case 2.0 to 3.3 VFast-slow-slow case 1.9 to 3.6 VSlow-fast-slow case 2.0 to 3.4 VFast-slow-fast case 1.9 to 3.6 VSlow-fast-fast case 2.0 to 3.4 V

Table 5.4. The corner cases and the respective input voltage range for which theregulator is still able to provide a good output regulated voltage.

Chapter 6

Conclusion

This chapter concludes the work and the investigation that has been done duringthis thesis. At the beginning, the achieved results are compared with the require-ments. The comparison is followed by the final results that have been achievedduring the work. To simplify the comparison between the simulation results andthe requirements, the input voltage range for each simulation made in chapter 5has been used to indicate the regulator’s performance. Table 6.1 shows each sim-ulation type and the according input voltage range for which the regulator is ableto deliver acceptable results according to the requirements.

Simulation Type Requirement The input voltagerange for which theoutput is regulated

DC-load simulations 0 to 50 µA 1.9 to 3.3 VAC-load simulations 0 to 100 µA 1.8 to 3.3 VTransient response simulations less than 10ms 2.0 to 3.3 VTemperature changes simula-tions

-20 to 70 C 2.0 to 3.5 V

Ctrl-bit simulations 0.5, 0.6, 0.7, 0.8 and 0.9 V 1.9 to 2.7 VCorner Analyze All possible process varia-

tions2.0 to 3.3 V

Table 6.1. The simulation type and the respective input voltage range for which theregulator is still able to provide a good output regulated voltage.

The input range for each of the simulations in the table is the range in whichthe regulator is able to fulfill the requirements. This means that this regulatordesign is able to fulfill all the requirements of the simulation types shown in theprevious table within the input range 2 to 2.7 V. However, as mentioned before, itwas not possible to use a core transistor as a driving transistor for the regulator andthe driving transistor was substituted with a thick-oxide transistor. The currentconsumption was also significantly higher than the targeted current consumption.Based on these results, a final conclusion could be drawn as follows:

85

86 Conclusion

During this thesis work, the design and implementation of an extreme lowpower regulator using 65-nm core transistors has been investigated. In chapter 3.2it has been shown that using core transistors has several advantages, especiallywhen it comes to chip manufacturing, which made it attractive for the smart dustproject. However, as seen in the design, it was not possible to use a core transistoras the driving transistor in the regulator, due to the relatively large range of thespecified input voltage. The simulation results, which have been achieved witha thick-oxide driving transistor, have also shown that a regulated voltage wasobtained for a smaller input voltage range than the specified input voltage rangein the requirements.

It is widely known in the analog design world that there is no perfect solution.In the power supply cook book it is said: "The engineer’s motto to life is 'Life isa tradeoff' and it comes into play here. It is impossible to design a power supplysystem that meets all the requirements that are initially set out by the otherengineers and management and keep it within cost, space, and weight limits. Thetypical initial requirement of a power supply is to provide infinitely adaptablefunctions, deliver kilowatts within zero space, and cost no money. Obviously,some compromise is in order."

Therefore, there should be a case study for the smart dust project to checkthe possibility of reducing the requirements on the regulator while having a betterperformance battery, or changing the regulator design. Cost, area, power con-sumption and the other factors must be considered on general basis to reach themost suitable solution for the project.

Chapter 7

Future Work

Based on the conclusion of this thesis work, the suggested design does not meetall the requirements, yet it could be used in the smart dust project if the followingpoints are taken into consideration as a future work:

• The general project requirements must be reviewed, and the possibility ofchanging the requirements should be considered in order to make a decisionwether this regulator design is going to be implemented. After all, it isnot uncommon to change the requirements when it comes to power supplydesign. It might be better in some cases to change some of the requirementsrather than changing the whole regulator design.

• Once the requirements have been negotiated and it has been decided toselect this design, improving the design performance to meet the new re-quirements should be the next step. Improvements can be started by furthertrying to tune the transistors’ sizes, which can notably improve the results.More specifically the transistor sizes must be optimized to reduce the cur-rent consumption. Even though the number of parameters to be changedis relatively high, optimizing the transistors’ sizes, if the requirements areedited, can highly improve the circuit’s performance.

• The power on reset circuit that is needed to supply the voltage of the ctrlsignal on startup needs to be implemented in order to enable sleep modefeature for the mote.

• The bandgap reference circuit is an important part of the power managementdesign. The required reference voltage used for this design is 0.3 V. Althoughit was considered during the design that the bandgap reference circuit couldintroduce an error in the output voltage that is up to 5%, simulations shouldpreferably be run with a transistor level bandgap reference circuit.

• The ideal current source used during simulations should be implemented ontransistor level since the current source circuit can significantly affect thesimulation results.

87

88 Future Work

• A big number of simulations have been executed during this thesis work.However, more simulations and more test cases are required in order toassure that the results are as close as possible to the real time performance.

• When the whole regulator circuit has been implemented and simulated ontransistor level including the sub-circuits, then the layout level of the designshould be the next step towards producing the real time chip. Layout designcan be very challenging and requires good analog design experience. Mainlybecause the circuit contains a lot of cascoded current mirrors, transmissiongates and other components that produce further complications on the layoutlevel.

Finally, combining other systems of the smart dust mote and simulating on alayout level provides the most precise results before the mote is manufactured andtested on a real time level.

Bibliography

[1] K. S. J. Pister, “Smart dust-hardware limits to wireless sensor networks,” inDistributed Computing Systems, 2003. Proceedings. 23rd International Con-ference on, p. 2, 2003. ID: 1.

[2] B. W. Cook, S. Lanzisera, and K. S. J. Pister, “Soc issues for rf smart dust,”Proceedings of the IEEE, vol. 94, no. 6, pp. 1177–1196, 2006. ID: 1.

[3] P. F. Gorder, “Sizing up smart dust,” Computing in Science & Engineering,vol. 5, no. 6, pp. 6–9, 2003. ID: 1.

[4] S. Bazarjani, L. Mathe, D. Yuan, J. Hinrichs, and G. Miao, “High-voltage low-power analog design in nanometer cmos technologies,” in Bipolar/BiCMOSCircuits and Technology Meeting, 2007. BCTM ’07. IEEE, pp. 149–154, 2007.ID: 1.

[5] J. Gjanci and M. Chowdhury, “Investigating issues of on-chip voltage regu-lator in nanoscale integrated circuits,” in Microelectronics, 2008. ICM 2008.International Conference on, pp. 123–126, 2008. ID: 1.

[6] K. Swan, “What are voltage regulators?.”

[7] K. A. Kuhn, “Introduction to voltage regulators,” 2009.

[8] M. Brown, Power Supply Cookbook. Elsevier Newnes, 2001. Compilationand indexing terms, Copyright 2012 Elsevier Inc.

[9] G. A. Rincon-Mora, “current efficient, low voltage, low dropout regulators,”1996.

[10] M. K. Kazimierczuk, Pulse-width Modulated DC-DC Power Converters.United Kingdom: John Wiley & Sons, Ltd, september 2008 ed.

[11] R. J. Baker, CMOS : circuit design, layout, and simulation. Hoboken, N.J:IEEE Press/Wiley, 3rd ed. ed., 2010.

[12] A. J. Annema, G. J. G. M. Geelen, and P. C. de Jong, “5.5-v i/o in a 2.5-v0.25-μm cmos technology,” Solid-State Circuits, IEEE Journal of, vol. 36,no. 3, pp. 528–538, 2001. ID: 1.

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[13] B. Razavi, Design of analog CMOS integrated circuits. Singapore: McGraw-Hill Education, 2001.

[14] D. Johns and K. W. Martin, Analog integrated circuit design. New York:Wiley, cop., 1997.

[15] M. I. Products, “What is a transmission gate (analog switch)?,” 2008.

[16] R. G. Raghavendra, “A low power, moderate accurate, single stage drivercircuit for on-chip voltage regulator,” in Circuits and Systems, 2005. 48thMidwest Symposium on, pp. 1798–1801 Vol. 2, 2005. ID: 1.

[17] R. Wies, B. Satavalekar, A. Agrawal, J. Mahdavi, A. Agah, A. Emadi, andJ. S. Daniel, DC-DC Converters. The Power Electronics Handbook, CRCPress, 11/20; 2012/05 2001. 11; M1: 0; doi:10.1201/9781420037067.pt2; M3:doi:10.1201/9781420037067.pt2.

Appendix A

Permission of using thephoto of the Mica mote

The photo of the Mica mote (figure 1.1) was taken from the authors of [2]. Manythanks to Steven Lanzisera for replying my email request about a permission forusing the photo, he has provided me with the original colored photo to use it inmy thesis. He wrote:

"The copyright is held be IEEE for those figures, so we can’t give permissionfor you to reuse them. However, you can use the original image that we providedto IEEE because it is in color. See attached."

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