designing circuits – synthesis -...

MAE140 Linear Circuits190

Designing Circuits – Synthesis - Lego

Port = a pair of terminals to a cctOne-port cct; measure I(s) and V(s) at same port

Driving-point impedance = input impedance = equiv impedance =Z(s)

Two-portsTransfer function; measure input at one port, output at

another

I(s)

V(s)+

-sCR

sLsIsVsZ

++==

!11

)()()(

I1(s)

V1(s)+

-V2(s)

I2(s)+

-

InputsOutputs


Example 11-2, T&R, 6th ed

!

TV(s) =

V2(s)

V1(s)

=R

1

R1+1sC

1

=s

s+1R

1C

1

Transfer function?

Input impedance?

!

Z(s) =V

1(s)

I1(s)

= R1+1sC

1


Cascade Connections

We want to apply a chain rule of processing

When can we do this by cascade connection of OpAmp ccts?Cascade means output of ccti is input of ccti+1

This makes the design and analysis much easier

This rule works if stage i+1 does not load stage iVoltage is not changed because of next stage

EitherOutput impedance of source stage is zero

OrInput impedance of load stage is infinite

Works well if Zout,source<<Zin,load

)(...)()()()( 321 sTsTsTsTsT VkVVVV !!!!=


Cascade Connections

Look for chain rule+_ R1V1(s)R2

2

1sC

1

1sC

V2(s) V3(s)

+++

Mesh analysis

!

TVtotal(s)=?T

V 1(s)"T

V 2(s) =

R1C

1s

R1C

1s+1

"1

R2C

2s+1

=R

1C

1s

R1R

2C

1C

2( )s 2 + R1C

1+ R

2C

2( )s+1

I2(s)I1(s)

0)(1)(

)()()(1

22

2111

121111

=!!"

#$$%

&+++'

='!!"

#$$%

&+

sIsC

RRsIR

sVsIRsIRsC

!"

#$%

&

!!!!

"

#

$$$$

%

&

++'

'+=!!

"

#$$%

&

'

0)(

1

1

)()( 1

1

212

1

111

2

1 sV

RRsC

R

RRsC

sIsI

( ) ( )

( ) ( ))(

1)(1)(

)(1

)(

1222111

22121

112

23

1221211

22121

1212

2

sVsCRCRCRsCCRR

sCRsIsC

sV

sVsRCRCRCsCCRR

RCCssI

++++==

++++=

No! Why?


Cascade Connections – OpAmp ccts

OpAmps can be used to achieve the chain ruleproperty for cascade connectionsThe input to the next stage needs to be driven by the

OpAmp outputConsider standard configurations

Noninverting amplifierNo current drawn from V1 – no load

Inverting amplifierCurrent provided by V1(s)

Need to make sure that stage isdriven by OpAmp output toavoid loading V1(s)

V1(s)+-

V2(s)+

Z2+

Z1

V1(s) +-

Z1 Z2

V2(s)

++I(s)

)()()(

11sZsVsI =


OpAmp Ccts and transfer functionsNode B:

Node B:

+_V1(s) +-

Z1 Z2

V2(s)

+A B C

)()(

)()()(0)(

0)()()(

)()()(

12

12

22

11

sZsZ

sVsVsTsV

sZsVsV

sZsVsV

VB

BB

!=="=

=!

+!

+_V1(s)

-+

V2(s)+A

B

C

Z2

Z1

)()()()()()(

0)()(

)()()(

121

1

122

sZsZsZsTsVsV

sZsV

sZsVsV

VB

BB

+=!=

=+"


Example 11-4, T&R, 5th ed, p511

Find the transfer function from V1(s) to V2(s)

111

11

11)(sCCsR

sCRsZ1

+=+=

2211 )1)(1()( 12

++−=

CsRCsRCsRsTV

R2

R1

V1(s)

+-

1

1sC

2

1sC

V2(s)

++

11)(222

22

22

2 +=

+=

sCRR

sCRsC

RsZ


Circuits as Signal Processors

Design a circuit with transfer function

R1=R2=100Ω, C1=C2=1µF, C3=100µF, L=70mH, R3=1Ω

( )( )

( )24842

52

10101021042.1

+

−+=

+×+

×+

s

jsjsss

s 408408

VO(s)

R2

R1

VI(s)

+-1

1sC

2

1sC

V2(s)

+

+-+

3

1sC

R3

sL

( )( )( )LssLCR

CsRCsRCsRsTV

111

)(2

332211

12 +−×

++−

=


Transfer Function Design – OpAmp Stages

First order stages

α

+-

1 Κγ Κ

αγ

++

−=ssKsTV )(

Series RL design

Series RC design

1

+-

Κ !K1

!1


First-order stages

αγ

++

−=ssKsTV )(

1

+-

!K1

!1

K1

Parallel RL design

1

+-

!K1

!1

Κ

Parallel RC design


Design Example 11-20, T&R, 5th ed, p 542

Design two ccts to realize

Unrealistic component values – scaling needed

)4000)(1000(3000)( ++

=ssssTV

1000µF

+-

1Ω1Ω

+-250µF

1Ω 3Ω

Stage 1 Stage 2

[ ]100010001

1011101

)( 1

3

31 +

!=

"""

#

$

%%%

&

'

+!= !

!

!

ss

ssTV [ ][ ]40003400013)(

12 +

!=+!=

!

ss

ssTV


Design Example 11-19, T&R, 5th ed, p 539

Non-inverting amplifier design

Less OpAmps but more difficult designThree stage: last stage not driven

Unrealistic component values still – scaling needed

1Ω+-

1000µF

1Ω2Ω

250µF

1Ω

Stage 1VoltageDivider

Stage 2OpAmp

Stage 3VoltageDivider

)4000)(1000(3000)(

++=

ssssTV


Scaled Design Example 11-21, T&R, 5th ed, p 544

More realistic values for components

Need to play games with elements to scaleThe ratio formulas for TV help permit this scaling

It certainly is possible to demand a design TV which isunrealizable with sensible component values

Like a pole at 10-3 Hz

100nF

+-

10ΚΩ10ΚΩ

+-25nF

10ΚΩ 30ΚΩ


Second-order Stage Design

Circuit stages to yield

02!"=R 1=L KC

!= 20

11

"

KC 12=2

0!"K

+-

120!

"

K1Ω Ω

1Η !02"#

F20

1

! +-

!02

1"#

H20

1

!

F1HK1

!

TV(s) =

Ks 2 + 2"#

0s+#

0

2


Circuit Synthesis

Given a stable transfer function TV(s), realize it via acct using first-order and second-order stages

We are limited to stable transfer functions to keep within thelinear range of the OpAmpsThere is an exception

When the unstable TV(s) is part of a stable feedbacksystem

Come to MAE143B to find out

Transistor cct design is conceptually similar

cbsassssTV++

++= 2

2)( !"#

basssTV ++

=!")(

designing circuits – synthesis -...

Documents